From 353fc6ec8e64d91f0b4410efa90173ec945bc75d Mon Sep 17 00:00:00 2001
From: Guo Ren <guoren@linux.alibaba.com>
Date: Sat, 15 Jul 2023 20:15:06 -0400
Subject: [PATCH 01/72] riscv: stack: Fixup independent softirq stack for
 CONFIG_FRAME_POINTER=n

The independent softirq stack uses s0 to save & restore sp, but s0 would
be corrupted when CONFIG_FRAME_POINTER=n. So add s0 in the clobber list
to fix the problem.

Fixes: dd69d07a5a6c ("riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK")
Cc: stable@vger.kernel.org
Reported-by: Zhangjin Wu <falcon@tinylab.org>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20230716001506.3506041-3-guoren@kernel.org
---
 arch/riscv/kernel/irq.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
index d0577cc6a081..a8efa053c4a5 100644
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@ -84,6 +84,9 @@ void do_softirq_own_stack(void)
 		: [sp] "r" (sp)
 		: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
 		  "t0", "t1", "t2", "t3", "t4", "t5", "t6",
+#ifndef CONFIG_FRAME_POINTER
+		  "s0",
+#endif
 		  "memory");
 	} else
 #endif
-- 
2.41.0


From 50cc8202f1272681fcddc71f7d1467ae360abe12 Mon Sep 17 00:00:00 2001
From: Celeste Liu <coelacanthushex@gmail.com>
Date: Thu, 20 Jul 2023 21:56:29 +0800
Subject: [PATCH 02/72] riscv: entry: set a0 = -ENOSYS only when syscall != -1
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When we test seccomp with 6.4 kernel, we found errno has wrong value.
If we deny NETLINK_AUDIT with EAFNOSUPPORT, after f0bddf50586d, we will
get ENOSYS instead. We got same result with commit 9c2598d43510 ("riscv: entry:
Save a0 prior syscall_enter_from_user_mode()").

After analysing code, we think that regs->a0 = -ENOSYS should only be executed
when syscall != -1 In __seccomp_filter, when seccomp rejected this syscall with
specified errno, they will set a0 to return number as syscall ABI, and then
return -1. This return number is finally pass as return number of
syscall_enter_from_user_mode, and then is compared with NR_syscalls after
converted to ulong (so it will be ULONG_MAX). The condition
syscall < NR_syscalls will always be false, so regs->a0 = -ENOSYS is always
executed. It covered a0 set by seccomp, so we always get ENOSYS when match
seccomp RET_ERRNO rule.

Fixes: f0bddf50586d ("riscv: entry: Convert to generic entry")
Reported-by: Felix Yan <felixonmars@archlinux.org>
Co-developed-by: Ruizhe Pan <c141028@gmail.com>
Signed-off-by: Ruizhe Pan <c141028@gmail.com>
Co-developed-by: Shiqi Zhang <shiqi@isrc.iscas.ac.cn>
Signed-off-by: Shiqi Zhang <shiqi@isrc.iscas.ac.cn>
Signed-off-by: Celeste Liu <CoelacanthusHex@gmail.com>
Tested-by: Felix Yan <felixonmars@archlinux.org>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Message-ID: <20230720140348.4716-1-CoelacanthusHex@gmail.com>
---
 arch/riscv/kernel/traps.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 927347a19847..f798c853bede 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -297,7 +297,7 @@ asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs)
 asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs)
 {
 	if (user_mode(regs)) {
-		ulong syscall = regs->a7;
+		long syscall = regs->a7;
 
 		regs->epc += 4;
 		regs->orig_a0 = regs->a0;
@@ -306,9 +306,9 @@ asmlinkage __visible __trap_section void do_trap_ecall_u(struct pt_regs *regs)
 
 		syscall = syscall_enter_from_user_mode(regs, syscall);
 
-		if (syscall < NR_syscalls)
+		if (syscall >= 0 && syscall < NR_syscalls)
 			syscall_handler(regs, syscall);
-		else
+		else if (syscall != -1)
 			regs->a0 = -ENOSYS;
 
 		syscall_exit_to_user_mode(regs);
-- 
2.41.0


From 4cbca71c72781280f6334a3e453420ecb654dbda Mon Sep 17 00:00:00 2001
From: Hal Feng <hal.feng@starfivetech.com>
Date: Tue, 18 Jul 2023 11:49:35 +0800
Subject: [PATCH 03/72] riscv: dts: starfive: jh7100: Add temperature sensor
 node and thermal-zones

Add temperature sensor and thermal-zones support for
the StarFive JH7100 SoC.

Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
(cherry picked from commit 0417c587420f41e357aa1ebb9e86810faac8fd06)
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi | 37 ++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 4218621ea3b9..35ab54fb235f 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -80,6 +80,31 @@ core1 {
 		};
 	};
 
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <15000>;
+
+			thermal-sensors = <&sfctemp>;
+
+			trips {
+				cpu_alert0 {
+					/* milliCelsius */
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit {
+					/* milliCelsius */
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
 	osc_sys: osc_sys {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -248,5 +273,17 @@ watchdog@12480000 {
 			resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
 				 <&rstgen JH7100_RSTN_WDT>;
 		};
+
+		sfctemp: temperature-sensor@124a0000 {
+			compatible = "starfive,jh7100-temp";
+			reg = <0x0 0x124a0000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
+				 <&clkgen JH7100_CLK_TEMP_APB>;
+			clock-names = "sense", "bus";
+			resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
+				 <&rstgen JH7100_RSTN_TEMP_APB>;
+			reset-names = "sense", "bus";
+			#thermal-sensor-cells = <0>;
+		};
 	};
 };
-- 
2.41.0


From 84b12ad9068f1a888a161d62cb1fa3a5d29962e8 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:12:57 +0200
Subject: [PATCH 04/72] openrisc: dma-mapping: flush bidirectional mappings

The cache management operations on DMA are different from the
other architectures:

 - on DMA_TO_DEVICE, Openrisc currently invalidates the cache
   after the writeback, where a simple writeback without
   invalidation should be sufficient.

 - on DMA_BIDIRECTIONAL, Openrisc does nothing, while most
   architectures either flush before DMA, or writeback before
   and invalidate after DMA. The separate invalidation for
   DMA_BIDIRECTIONAL/DMA_FROM_DEVICE is only required on CPUs
   that can do speculative prefetches.

Change both to have the normal set of operations.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-2-arnd@kernel.org
---
 arch/openrisc/kernel/dma.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
index b3edbb33b621..91a00d09ffad 100644
--- a/arch/openrisc/kernel/dma.c
+++ b/arch/openrisc/kernel/dma.c
@@ -103,10 +103,10 @@ void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
 
 	switch (dir) {
 	case DMA_TO_DEVICE:
-		/* Flush the dcache for the requested range */
+		/* Write back the dcache for the requested range */
 		for (cl = addr; cl < addr + size;
 		     cl += cpuinfo->dcache_block_size)
-			mtspr(SPR_DCBFR, cl);
+			mtspr(SPR_DCBWR, cl);
 		break;
 	case DMA_FROM_DEVICE:
 		/* Invalidate the dcache for the requested range */
@@ -114,12 +114,13 @@ void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
 		     cl += cpuinfo->dcache_block_size)
 			mtspr(SPR_DCBIR, cl);
 		break;
+	case DMA_BIDIRECTIONAL:
+		/* Flush the dcache for the requested range */
+		for (cl = addr; cl < addr + size;
+		     cl += cpuinfo->dcache_block_size)
+			mtspr(SPR_DCBFR, cl);
+		break;
 	default:
-		/*
-		 * NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
-		 * flush nor invalidate the cache here as the area will need
-		 * to be manually synced anyway.
-		 */
 		break;
 	}
 }
-- 
2.41.0


From 3ea1db994ab76d2c2a69927827a43769ef5a1604 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:12:58 +0200
Subject: [PATCH 05/72] xtensa: dma-mapping: use normal cache invalidation
 rules

xtensa is one of the platforms that has both write-back and write-through
caches, and needs to account for both in its DMA mapping operations.

It does this through a set of operations that is different from any
architecture. This is not a problem by itself, but it makes it rather
hard to figure out whether this is correct or not, and to unify this
implementation with the others.

Change the semantics to the usual ones for non-speculating CPUs:

 - On DMA_TO_DEVICE, call __flush_dcache_range() to perform the
   writeback even on writethrough caches, where this is a nop.

 - On DMA_FROM_DEVICE, invalidate the mapping before the DMA rather
   than afterwards.

 - On DMA_BIDIRECTIONAL, combine the pre-writeback with the
   post-invalidate into a call to __flush_invalidate_dcache_range()
   that turns into a simple invalidate on writeback caches.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Link: https://lore.kernel.org/r/20230327121317.4081816-3-arnd@kernel.org
---
 arch/xtensa/Kconfig                  |  1 -
 arch/xtensa/include/asm/cacheflush.h |  6 +++---
 arch/xtensa/kernel/pci-dma.c         | 29 +++++-----------------------
 3 files changed, 8 insertions(+), 28 deletions(-)

diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 2a51a466779f..006754b12022 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -8,7 +8,6 @@ config XTENSA
 	select ARCH_HAS_DMA_PREP_COHERENT if MMU
 	select ARCH_HAS_GCOV_PROFILE_ALL
 	select ARCH_HAS_KCOV
-	select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
 	select ARCH_HAS_DMA_SET_UNCACHED if MMU
 	select ARCH_HAS_STRNCPY_FROM_USER if !KASAN
diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index 7b4359312c25..2f645d25565a 100644
--- a/arch/xtensa/include/asm/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
@@ -61,9 +61,9 @@ static inline void __flush_dcache_page(unsigned long va)
 static inline void __flush_dcache_range(unsigned long va, unsigned long sz)
 {
 }
-# define __flush_invalidate_dcache_all()	__invalidate_dcache_all()
-# define __flush_invalidate_dcache_page(p)	__invalidate_dcache_page(p)
-# define __flush_invalidate_dcache_range(p,s)	__invalidate_dcache_range(p,s)
+# define __flush_invalidate_dcache_all		__invalidate_dcache_all
+# define __flush_invalidate_dcache_page		__invalidate_dcache_page
+# define __flush_invalidate_dcache_range	__invalidate_dcache_range
 #endif
 
 #if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c
index 94955caa4488..ff3bf015eca4 100644
--- a/arch/xtensa/kernel/pci-dma.c
+++ b/arch/xtensa/kernel/pci-dma.c
@@ -43,38 +43,19 @@ static void do_cache_op(phys_addr_t paddr, size_t size,
 		}
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
 	switch (dir) {
-	case DMA_BIDIRECTIONAL:
+	case DMA_TO_DEVICE:
+		do_cache_op(paddr, size, __flush_dcache_range);
+		break;
 	case DMA_FROM_DEVICE:
 		do_cache_op(paddr, size, __invalidate_dcache_range);
 		break;
-
-	case DMA_NONE:
-		BUG();
-		break;
-
-	default:
-		break;
-	}
-}
-
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
-{
-	switch (dir) {
 	case DMA_BIDIRECTIONAL:
-	case DMA_TO_DEVICE:
-		if (XCHAL_DCACHE_IS_WRITEBACK)
-			do_cache_op(paddr, size, __flush_dcache_range);
+		do_cache_op(paddr, size, __flush_invalidate_dcache_range);
 		break;
-
-	case DMA_NONE:
-		BUG();
-		break;
-
 	default:
 		break;
 	}
-- 
2.41.0


From b2fc76298c6eca1f8104684753cc16d7fc536f67 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:12:59 +0200
Subject: [PATCH 06/72] sparc32: flush caches in dma_sync_*for_device

Leon has a very minimalistic cache that has no range operations
and requires being flushed entirely to deal with noncoherent
DMA. Most in-order architectures do their cache management in
the dma_sync_*for_device() operations rather than dma_sync_*for_cpu.

Since the cache is write-through only, both should have the same
effect, so change it for consistency with the other architectures.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-4-arnd@kernel.org
---
 arch/sparc/Kconfig         | 2 +-
 arch/sparc/kernel/ioport.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 49849790e66d..068bf425c4fd 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -53,7 +53,7 @@ config SPARC32
 	def_bool !64BIT
 	select ARCH_32BIT_OFF_T
 	select ARCH_HAS_CPU_FINALIZE_INIT if !SMP
-	select ARCH_HAS_SYNC_DMA_FOR_CPU
+	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
 	select CLZ_TAB
 	select DMA_DIRECT_REMAP
 	select GENERIC_ATOMIC64
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index a8cbe403301f..9c20cd833d3c 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -306,7 +306,7 @@ arch_initcall(sparc_register_ioport);
  * On LEON systems without cache snooping, the entire D-CACHE must be flushed to
  * make DMA to cacheable memory coherent.
  */
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
 	if (dir != DMA_TO_DEVICE &&
-- 
2.41.0


From c35291eedd2f5d658c4ddd026f154267b9b282ab Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:00 +0200
Subject: [PATCH 07/72] microblaze: dma-mapping: skip extra DMA flushes

The microblaze dma_sync_* implementation uses the same function
for both _for_cpu() and _for_device(), which is inconsistent
with other architectures and slightly more expensive.

Split it up into separate functions and skip the parts that
are not needed:

 - on dma_sync_*_for_cpu(..., DMA_TO_DEVICE), skip the second
   writeback, which does nothing.

 - on dma_sync_*_for_cpu(..., DMA_BIDIRECTIONAL), only invalidate
   the cache to clear out cache lines that got loaded speculatively,
   but skip the extraneous writeback.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-5-arnd@kernel.org
---
 arch/microblaze/kernel/dma.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/arch/microblaze/kernel/dma.c b/arch/microblaze/kernel/dma.c
index 04d091ade417..b4c4e45fd45e 100644
--- a/arch/microblaze/kernel/dma.c
+++ b/arch/microblaze/kernel/dma.c
@@ -14,8 +14,8 @@
 #include <linux/bug.h>
 #include <asm/cacheflush.h>
 
-static void __dma_sync(phys_addr_t paddr, size_t size,
-		enum dma_data_direction direction)
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
+		enum dma_data_direction dir)
 {
 	switch (direction) {
 	case DMA_TO_DEVICE:
@@ -30,14 +30,16 @@ static void __dma_sync(phys_addr_t paddr, size_t size,
 	}
 }
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
-{
-	__dma_sync(paddr, size, dir);
-}
-
 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
-	__dma_sync(paddr, size, dir);
-}
+	switch (direction) {
+	case DMA_TO_DEVICE:
+		break;
+	case DMA_BIDIRECTIONAL:
+	case DMA_FROM_DEVICE:
+		invalidate_dcache_range(paddr, paddr + size);
+		break;
+	default:
+		BUG();
+	}}
-- 
2.41.0


From 84f453497b73842c33dd66823a66099c0d717a70 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:01 +0200
Subject: [PATCH 08/72] powerpc: dma-mapping: split out cache operation logic

The powerpc arch_sync_dma_for_device()/arch_sync_dma_for_cpu() functions
behave differently from all other architectures, at least for some of
the operations.

As a preparation for making the behavior more consistent, reorder the
logic in which they decide whether to flush, invalidate or clean the.
No change in behavior is intended.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-6-arnd@kernel.org
---
 arch/powerpc/mm/dma-noncoherent.c | 91 +++++++++++++++++++++----------
 1 file changed, 63 insertions(+), 28 deletions(-)

diff --git a/arch/powerpc/mm/dma-noncoherent.c b/arch/powerpc/mm/dma-noncoherent.c
index 30260b5d146d..f10869d27de5 100644
--- a/arch/powerpc/mm/dma-noncoherent.c
+++ b/arch/powerpc/mm/dma-noncoherent.c
@@ -16,31 +16,28 @@
 #include <asm/tlbflush.h>
 #include <asm/dma.h>
 
+enum dma_cache_op {
+	DMA_CACHE_CLEAN,
+	DMA_CACHE_INVAL,
+	DMA_CACHE_FLUSH,
+};
+
 /*
  * make an area consistent.
  */
-static void __dma_sync(void *vaddr, size_t size, int direction)
+static void __dma_op(void *vaddr, size_t size, enum dma_cache_op op)
 {
 	unsigned long start = (unsigned long)vaddr;
 	unsigned long end   = start + size;
 
-	switch (direction) {
-	case DMA_NONE:
-		BUG();
-	case DMA_FROM_DEVICE:
-		/*
-		 * invalidate only when cache-line aligned otherwise there is
-		 * the potential for discarding uncommitted data from the cache
-		 */
-		if ((start | end) & (L1_CACHE_BYTES - 1))
-			flush_dcache_range(start, end);
-		else
-			invalidate_dcache_range(start, end);
-		break;
-	case DMA_TO_DEVICE:		/* writeback only */
+	switch (op) {
+	case DMA_CACHE_CLEAN:
 		clean_dcache_range(start, end);
 		break;
-	case DMA_BIDIRECTIONAL:	/* writeback and invalidate */
+	case DMA_CACHE_INVAL:
+		invalidate_dcache_range(start, end);
+		break;
+	case DMA_CACHE_FLUSH:
 		flush_dcache_range(start, end);
 		break;
 	}
@@ -48,16 +45,16 @@ static void __dma_sync(void *vaddr, size_t size, int direction)
 
 #ifdef CONFIG_HIGHMEM
 /*
- * __dma_sync_page() implementation for systems using highmem.
+ * __dma_highmem_op() implementation for systems using highmem.
  * In this case, each page of a buffer must be kmapped/kunmapped
- * in order to have a virtual address for __dma_sync(). This must
+ * in order to have a virtual address for __dma_op(). This must
  * not sleep so kmap_atomic()/kunmap_atomic() are used.
  *
  * Note: yes, it is possible and correct to have a buffer extend
  * beyond the first page.
  */
-static inline void __dma_sync_page_highmem(struct page *page,
-		unsigned long offset, size_t size, int direction)
+static inline void __dma_highmem_op(struct page *page,
+		unsigned long offset, size_t size, enum dma_cache_op op)
 {
 	size_t seg_size = min((size_t)(PAGE_SIZE - offset), size);
 	size_t cur_size = seg_size;
@@ -71,7 +68,7 @@ static inline void __dma_sync_page_highmem(struct page *page,
 		start = (unsigned long)kmap_atomic(page + seg_nr) + seg_offset;
 
 		/* Sync this buffer segment */
-		__dma_sync((void *)start, seg_size, direction);
+		__dma_op((void *)start, seg_size, op);
 		kunmap_atomic((void *)start);
 		seg_nr++;
 
@@ -88,32 +85,70 @@ static inline void __dma_sync_page_highmem(struct page *page,
 #endif /* CONFIG_HIGHMEM */
 
 /*
- * __dma_sync_page makes memory consistent. identical to __dma_sync, but
- * takes a struct page instead of a virtual address
+ * __dma_phys_op makes memory consistent. identical to __dma_op, but
+ * takes a phys_addr_t instead of a virtual address
  */
-static void __dma_sync_page(phys_addr_t paddr, size_t size, int dir)
+static void __dma_phys_op(phys_addr_t paddr, size_t size, enum dma_cache_op op)
 {
 	struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
 	unsigned offset = paddr & ~PAGE_MASK;
 
 #ifdef CONFIG_HIGHMEM
-	__dma_sync_page_highmem(page, offset, size, dir);
+	__dma_highmem_op(page, offset, size, op);
 #else
 	unsigned long start = (unsigned long)page_address(page) + offset;
-	__dma_sync((void *)start, size, dir);
+	__dma_op((void *)start, size, op);
 #endif
 }
 
 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
-	__dma_sync_page(paddr, size, dir);
+	switch (direction) {
+	case DMA_NONE:
+		BUG();
+	case DMA_FROM_DEVICE:
+		/*
+		 * invalidate only when cache-line aligned otherwise there is
+		 * the potential for discarding uncommitted data from the cache
+		 */
+		if ((start | end) & (L1_CACHE_BYTES - 1))
+			__dma_phys_op(start, end, DMA_CACHE_FLUSH);
+		else
+			__dma_phys_op(start, end, DMA_CACHE_INVAL);
+		break;
+	case DMA_TO_DEVICE:		/* writeback only */
+		__dma_phys_op(start, end, DMA_CACHE_CLEAN);
+		break;
+	case DMA_BIDIRECTIONAL:	/* writeback and invalidate */
+		__dma_phys_op(start, end, DMA_CACHE_FLUSH);
+		break;
+	}
 }
 
 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
-	__dma_sync_page(paddr, size, dir);
+	switch (direction) {
+	case DMA_NONE:
+		BUG();
+	case DMA_FROM_DEVICE:
+		/*
+		 * invalidate only when cache-line aligned otherwise there is
+		 * the potential for discarding uncommitted data from the cache
+		 */
+		if ((start | end) & (L1_CACHE_BYTES - 1))
+			__dma_phys_op(start, end, DMA_CACHE_FLUSH);
+		else
+			__dma_phys_op(start, end, DMA_CACHE_INVAL);
+		break;
+	case DMA_TO_DEVICE:		/* writeback only */
+		__dma_phys_op(start, end, DMA_CACHE_CLEAN);
+		break;
+	case DMA_BIDIRECTIONAL:	/* writeback and invalidate */
+		__dma_phys_op(start, end, DMA_CACHE_FLUSH);
+		break;
+	}
 }
 
 void arch_dma_prep_coherent(struct page *page, size_t size)
-- 
2.41.0


From 57f1b34f23bd23cb335cf79751d22b30956d9c4e Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:02 +0200
Subject: [PATCH 09/72] powerpc: dma-mapping: minimize for_cpu flushing

The powerpc dma_sync_*_for_cpu() variants do more flushes than on other
architectures. Reduce it to what everyone else does:

 - No flush is needed after data has been sent to a device

 - When data has been received from a device, the cache only needs to
   be invalidated to clear out cache lines that were speculatively
   prefetched.

In particular, the second flushing of partial cache lines of bidirectional
buffers is actively harmful -- if a single cache line is written by both
the CPU and the device, flushing it again does not maintain coherency
but instead overwrite the data that was just received from the device.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-7-arnd@kernel.org
---
 arch/powerpc/mm/dma-noncoherent.c | 18 ++++--------------
 1 file changed, 4 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/mm/dma-noncoherent.c b/arch/powerpc/mm/dma-noncoherent.c
index f10869d27de5..e108cacf877f 100644
--- a/arch/powerpc/mm/dma-noncoherent.c
+++ b/arch/powerpc/mm/dma-noncoherent.c
@@ -132,21 +132,11 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 	switch (direction) {
 	case DMA_NONE:
 		BUG();
-	case DMA_FROM_DEVICE:
-		/*
-		 * invalidate only when cache-line aligned otherwise there is
-		 * the potential for discarding uncommitted data from the cache
-		 */
-		if ((start | end) & (L1_CACHE_BYTES - 1))
-			__dma_phys_op(start, end, DMA_CACHE_FLUSH);
-		else
-			__dma_phys_op(start, end, DMA_CACHE_INVAL);
-		break;
-	case DMA_TO_DEVICE:		/* writeback only */
-		__dma_phys_op(start, end, DMA_CACHE_CLEAN);
+	case DMA_TO_DEVICE:
 		break;
-	case DMA_BIDIRECTIONAL:	/* writeback and invalidate */
-		__dma_phys_op(start, end, DMA_CACHE_FLUSH);
+	case DMA_FROM_DEVICE:
+	case DMA_BIDIRECTIONAL:
+		__dma_phys_op(start, end, DMA_CACHE_INVAL);
 		break;
 	}
 }
-- 
2.41.0


From 6d1340cca959ce20dc6b3bfb170301047d0a3672 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:03 +0200
Subject: [PATCH 10/72] powerpc: dma-mapping: always clean cache in
 _for_device() op

The powerpc implementation of arch_sync_dma_for_device() is unique in that
it sometimes performs a full flush for the arch_sync_dma_for_device(paddr,
size, DMA_FROM_DEVICE) operation when the address is unaligned, but
otherwise invalidates the caches.

Since the _for_cpu() counterpart has to invalidate the cache already
in order to avoid stale data from prefetching, this operation only really
needs to ensure that there are no dirty cache lines, which can be done
using either invalidation or cleaning the cache, but not necessarily
both.

Most architectures traditionally go for invalidation here, but as
Will Deacon points out, this can leak old data to user space if
a DMA is started but the device ends up not actually filling the
entire buffer, see the link below.

The same argument applies to DMA_BIDIRECTIONAL transfers. Using
a cache-clean operation is the safe choice here, followed by
invalidating the cache after the DMA to get rid of stale data
that was prefetched before the completion of the DMA.

Link: https://lore.kernel.org/all/20220606152150.GA31568@willie-the-truck/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-8-arnd@kernel.org
---
 arch/powerpc/mm/dma-noncoherent.c | 21 +--------------------
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/arch/powerpc/mm/dma-noncoherent.c b/arch/powerpc/mm/dma-noncoherent.c
index e108cacf877f..00e59a4faa2b 100644
--- a/arch/powerpc/mm/dma-noncoherent.c
+++ b/arch/powerpc/mm/dma-noncoherent.c
@@ -104,26 +104,7 @@ static void __dma_phys_op(phys_addr_t paddr, size_t size, enum dma_cache_op op)
 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
-	switch (direction) {
-	case DMA_NONE:
-		BUG();
-	case DMA_FROM_DEVICE:
-		/*
-		 * invalidate only when cache-line aligned otherwise there is
-		 * the potential for discarding uncommitted data from the cache
-		 */
-		if ((start | end) & (L1_CACHE_BYTES - 1))
-			__dma_phys_op(start, end, DMA_CACHE_FLUSH);
-		else
-			__dma_phys_op(start, end, DMA_CACHE_INVAL);
-		break;
-	case DMA_TO_DEVICE:		/* writeback only */
-		__dma_phys_op(start, end, DMA_CACHE_CLEAN);
-		break;
-	case DMA_BIDIRECTIONAL:	/* writeback and invalidate */
-		__dma_phys_op(start, end, DMA_CACHE_FLUSH);
-		break;
-	}
+	__dma_phys_op(start, end, DMA_CACHE_CLEAN);
 }
 
 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-- 
2.41.0


From 99ab482a94ec8f191e4b3732f52e9a0fda40b476 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:04 +0200
Subject: [PATCH 11/72] riscv: dma-mapping: only invalidate after DMA, not
 flush

No other architecture intentionally writes back dirty cache lines into
a buffer that a device has just finished writing into. If the cache is
clean, this has no effect at all, but if a cacheline in the buffer has
actually been written by the CPU,  there is a drive bug that is likely
made worse by overwriting that buffer.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 1631ba1259d6 ("riscv: Add support for non-coherent devices using zicbom extension")
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230327121317.4081816-9-arnd@kernel.org
---
 arch/riscv/mm/dma-noncoherent.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index d51a75864e53..94614cf61cdd 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -42,7 +42,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 		break;
 	case DMA_FROM_DEVICE:
 	case DMA_BIDIRECTIONAL:
-		ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+		ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
 		break;
 	default:
 		break;
-- 
2.41.0


From af5f161110b1c8d3bedb142d58017f101641620f Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:05 +0200
Subject: [PATCH 12/72] riscv: dma-mapping: skip invalidation before
 bidirectional DMA

For a DMA_BIDIRECTIONAL transfer, the caches have to be cleaned
first to let the device see data written by the CPU, and invalidated
after the transfer to let the CPU see data written by the device.

riscv also invalidates the caches before the transfer, which does
not appear to serve any purpose.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20230327121317.4081816-10-arnd@kernel.org
---
 arch/riscv/mm/dma-noncoherent.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index 94614cf61cdd..fc6377a64c8d 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -25,7 +25,7 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
 		break;
 	case DMA_BIDIRECTIONAL:
-		ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+		ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
 		break;
 	default:
 		break;
-- 
2.41.0


From c162b6108c5d9339ec7e0e315b7c91e6cc180571 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:06 +0200
Subject: [PATCH 13/72] csky: dma-mapping: skip invalidating before DMA from
 device

csky is the only architecture that does a full flush for the
dma_sync_*_for_device(..., DMA_FROM_DEVICE) operation. The requirement
is only make sure there are no dirty cache lines for the buffer,
which can be either done through an invalidate operation (as on most
architectures including arm32, mips and arc), or a writeback (as on
arm64 and riscv). The cache also has to be invalidated eventually but
csky already does that after the transfer.

Use a 'clean' operation here for consistency with arm64 and riscv.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20230327121317.4081816-11-arnd@kernel.org
---
 arch/csky/mm/dma-mapping.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/csky/mm/dma-mapping.c b/arch/csky/mm/dma-mapping.c
index 82447029feb4..c90f912e2822 100644
--- a/arch/csky/mm/dma-mapping.c
+++ b/arch/csky/mm/dma-mapping.c
@@ -60,11 +60,9 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 {
 	switch (dir) {
 	case DMA_TO_DEVICE:
-		cache_op(paddr, size, dma_wb_range);
-		break;
 	case DMA_FROM_DEVICE:
 	case DMA_BIDIRECTIONAL:
-		cache_op(paddr, size, dma_wbinv_range);
+		cache_op(paddr, size, dma_wb_range);
 		break;
 	default:
 		BUG();
-- 
2.41.0


From 2082a7fe5ce53eb25588dcd9673269091d0d8295 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:07 +0200
Subject: [PATCH 14/72] mips: dma-mapping: skip invalidating before
 bidirectional DMA

Some architectures that need to invalidate buffers after bidirectional
DMA because of speculative prefetching only do a simpler writeback
before that DMA, while architectures that don't need to do the second
invalidate tend to have a combined writeback+invalidate before the
DMA.

The behavior on mips is slightly inconsistent, as it always
does the invalidation before bidirectional DMA and conditionally
does it a second time.

In order to make the behavior the same as the rest, change it
so that there is exactly one invalidation here, either before
or after the DMA.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-12-arnd@kernel.org
---
 arch/mips/mm/dma-noncoherent.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 3c4fc97b9f39..b4350faf4f1e 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -65,7 +65,11 @@ static inline void dma_sync_virt_for_device(void *addr, size_t size,
 		dma_cache_inv((unsigned long)addr, size);
 		break;
 	case DMA_BIDIRECTIONAL:
-		dma_cache_wback_inv((unsigned long)addr, size);
+		if (IS_ENABLED(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) &&
+		    cpu_needs_post_dma_flush())
+			dma_cache_wback((unsigned long)addr, size);
+		else
+			dma_cache_wback_inv((unsigned long)addr, size);
 		break;
 	default:
 		BUG();
-- 
2.41.0


From 24be0de1015dffe72a1757edc7de990c1206e6ba Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:08 +0200
Subject: [PATCH 15/72] mips: dma-mapping: split out cache operation logic

The mips arch_sync_dma_for_device()/arch_sync_dma_for_cpu() functions
behave the same way as on other architectures, but in order to unify
the implementations, the code needs to be rearranged to pick the type
of cache operation in the outermost function.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-13-arnd@kernel.org
---
 arch/mips/mm/dma-noncoherent.c | 75 ++++++++++++++--------------------
 1 file changed, 30 insertions(+), 45 deletions(-)

diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index b4350faf4f1e..b9d68bcc5d53 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -54,50 +54,13 @@ void *arch_dma_set_uncached(void *addr, size_t size)
 	return (void *)(__pa(addr) + UNCAC_BASE);
 }
 
-static inline void dma_sync_virt_for_device(void *addr, size_t size,
-		enum dma_data_direction dir)
-{
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		dma_cache_wback((unsigned long)addr, size);
-		break;
-	case DMA_FROM_DEVICE:
-		dma_cache_inv((unsigned long)addr, size);
-		break;
-	case DMA_BIDIRECTIONAL:
-		if (IS_ENABLED(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) &&
-		    cpu_needs_post_dma_flush())
-			dma_cache_wback((unsigned long)addr, size);
-		else
-			dma_cache_wback_inv((unsigned long)addr, size);
-		break;
-	default:
-		BUG();
-	}
-}
-
-static inline void dma_sync_virt_for_cpu(void *addr, size_t size,
-		enum dma_data_direction dir)
-{
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		break;
-	case DMA_FROM_DEVICE:
-	case DMA_BIDIRECTIONAL:
-		dma_cache_inv((unsigned long)addr, size);
-		break;
-	default:
-		BUG();
-	}
-}
-
 /*
  * A single sg entry may refer to multiple physically contiguous pages.  But
  * we still need to process highmem pages individually.  If highmem is not
  * configured then the bulk of this loop gets optimized out.
  */
 static inline void dma_sync_phys(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir, bool for_device)
+		void(*cache_op)(unsigned long start, unsigned long size))
 {
 	struct page *page = pfn_to_page(paddr >> PAGE_SHIFT);
 	unsigned long offset = paddr & ~PAGE_MASK;
@@ -113,10 +76,7 @@ static inline void dma_sync_phys(phys_addr_t paddr, size_t size,
 		}
 
 		addr = kmap_atomic(page);
-		if (for_device)
-			dma_sync_virt_for_device(addr + offset, len, dir);
-		else
-			dma_sync_virt_for_cpu(addr + offset, len, dir);
+		cache_op((unsigned long)addr + offset, len);
 		kunmap_atomic(addr);
 
 		offset = 0;
@@ -128,15 +88,40 @@ static inline void dma_sync_phys(phys_addr_t paddr, size_t size,
 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
-	dma_sync_phys(paddr, size, dir, true);
+	switch (dir) {
+	case DMA_TO_DEVICE:
+		dma_sync_phys(paddr, size, _dma_cache_wback);
+		break;
+	case DMA_FROM_DEVICE:
+		dma_sync_phys(paddr, size, _dma_cache_inv);
+		break;
+	case DMA_BIDIRECTIONAL:
+		if (IS_ENABLED(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) &&
+		    cpu_needs_post_dma_flush())
+			dma_sync_phys(paddr, size, _dma_cache_wback);
+		else
+			dma_sync_phys(paddr, size, _dma_cache_wback_inv);
+		break;
+	default:
+		break;
+	}
 }
 
 #ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
-	if (cpu_needs_post_dma_flush())
-		dma_sync_phys(paddr, size, dir, false);
+	switch (dir) {
+	case DMA_TO_DEVICE:
+		break;
+	case DMA_FROM_DEVICE:
+	case DMA_BIDIRECTIONAL:
+		if (cpu_needs_post_dma_flush())
+			dma_sync_phys(paddr, size, _dma_cache_inv);
+		break;
+	default:
+		break;
+	}
 }
 #endif
 
-- 
2.41.0


From 1fee98ec891a5b6ca6a7cf1a4502032e960c829e Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:09 +0200
Subject: [PATCH 16/72] arc: dma-mapping: skip invalidating before
 bidirectional DMA

Some architectures that need to invalidate buffers after bidirectional
DMA because of speculative prefetching only do a simpler writeback
before that DMA, while architectures that don't need to do the second
invalidate tend to have a combined writeback+invalidate before the
DMA.

arc is one of the architectures that does both, which seems unnecessary.

Change it to behave like arm/arm64/xtensa instead, and use just a
writeback before the DMA when we do the invalidate afterwards.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Vineet Gupta <vgupta@kernel.org>
Tested-by: Shahab Vahedi <shahab@synopsys.com>
Link: https://lore.kernel.org/r/20230327121317.4081816-14-arnd@kernel.org
---
 arch/arc/mm/dma.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c
index 2a7fbbb83b70..ddb96786f765 100644
--- a/arch/arc/mm/dma.c
+++ b/arch/arc/mm/dma.c
@@ -40,7 +40,7 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
  *          |----------------------------------------------------------------
  * TO_DEV   |   writeback        writeback      |   none          none
  * FROM_DEV |   invalidate       invalidate     |   invalidate*   invalidate*
- * BIDIR    |   writeback+inv    writeback+inv  |   invalidate    invalidate
+ * BIDIR    |   writeback        writeback      |   invalidate    invalidate
  *
  *     [*] needed for CPU speculative prefetches
  *
@@ -61,7 +61,7 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		break;
 
 	case DMA_BIDIRECTIONAL:
-		dma_cache_wback_inv(paddr, size);
+		dma_cache_wback(paddr, size);
 		break;
 
 	default:
-- 
2.41.0


From 37958798b1bc14b582796f0c5b2c84b98106f655 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:11 +0200
Subject: [PATCH 17/72] ARM: dma-mapping: always invalidate WT caches before
 DMA

Most ARM CPUs can have write-back caches and that require
cache management to be done in the dma_sync_*_for_device()
operation. This is typically done in both writeback and
writethrough mode.

The cache-v4.S (arm720/740/7tdmi/9tdmi) and cache-v4wt.S
(arm920t, arm940t) implementations are the exception here,
and only do the cache management after the DMA is complete,
in the dma_sync_*_for_cpu() operation.

Change this for consistency with the other platforms. This
should have no user visible effect.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230327121317.4081816-16-arnd@kernel.org
---
 arch/arm/mm/cache-v4.S   | 8 ++++----
 arch/arm/mm/cache-v4wt.S | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 7787057e4990..e2b104876340 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -117,23 +117,23 @@ ENTRY(v4_dma_flush_range)
 	ret	lr
 
 /*
- *	dma_unmap_area(start, size, dir)
+ *	dma_map_area(start, size, dir)
  *	- start	- kernel virtual start address
  *	- size	- size of region
  *	- dir	- DMA direction
  */
-ENTRY(v4_dma_unmap_area)
+ENTRY(v4_dma_map_area)
 	teq	r2, #DMA_TO_DEVICE
 	bne	v4_dma_flush_range
 	/* FALLTHROUGH */
 
 /*
- *	dma_map_area(start, size, dir)
+ *	dma_unmap_area(start, size, dir)
  *	- start	- kernel virtual start address
  *	- size	- size of region
  *	- dir	- DMA direction
  */
-ENTRY(v4_dma_map_area)
+ENTRY(v4_dma_unmap_area)
 	ret	lr
 ENDPROC(v4_dma_unmap_area)
 ENDPROC(v4_dma_map_area)
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 0b290c25a99d..652218752f88 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -172,24 +172,24 @@ v4wt_dma_inv_range:
 	.equ	v4wt_dma_flush_range, v4wt_dma_inv_range
 
 /*
- *	dma_unmap_area(start, size, dir)
+ *	dma_map_area(start, size, dir)
  *	- start	- kernel virtual start address
  *	- size	- size of region
  *	- dir	- DMA direction
  */
-ENTRY(v4wt_dma_unmap_area)
+ENTRY(v4wt_dma_map_area)
 	add	r1, r1, r0
 	teq	r2, #DMA_TO_DEVICE
 	bne	v4wt_dma_inv_range
 	/* FALLTHROUGH */
 
 /*
- *	dma_map_area(start, size, dir)
+ *	dma_unmap_area(start, size, dir)
  *	- start	- kernel virtual start address
  *	- size	- size of region
  *	- dir	- DMA direction
  */
-ENTRY(v4wt_dma_map_area)
+ENTRY(v4wt_dma_unmap_area)
 	ret	lr
 ENDPROC(v4wt_dma_unmap_area)
 ENDPROC(v4wt_dma_map_area)
-- 
2.41.0


From 3111b2054180d01e9f536b8b085fda08af7812e5 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:12 +0200
Subject: [PATCH 18/72] ARM: dma-mapping: bring back dmac_{clean,inv}_range

These were remove ages ago in commit 702b94bff3c5 ("ARM: dma-mapping:
remove dmac_clean_range and dmac_inv_range") in an effort to sanitize
the dma-mapping API.

Now this logic is getting moved into the generic dma-mapping
implementation in order to give architectures less control over
it, which requires reverting that earlier work.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-17-arnd@kernel.org
---
 arch/arm/include/asm/cacheflush.h | 21 +++++++++++++++++++++
 arch/arm/include/asm/glue-cache.h |  4 ++++
 arch/arm/mm/cache-fa.S            |  4 ++--
 arch/arm/mm/cache-nop.S           |  6 ++++++
 arch/arm/mm/cache-v4.S            |  5 +++++
 arch/arm/mm/cache-v4wb.S          |  4 ++--
 arch/arm/mm/cache-v4wt.S          | 14 +++++++++++++-
 arch/arm/mm/cache-v6.S            |  4 ++--
 arch/arm/mm/cache-v7.S            |  6 ++++--
 arch/arm/mm/cache-v7m.S           |  4 ++--
 arch/arm/mm/proc-arm1020.S        |  4 ++--
 arch/arm/mm/proc-arm1020e.S       |  4 ++--
 arch/arm/mm/proc-arm1022.S        |  4 ++--
 arch/arm/mm/proc-arm1026.S        |  4 ++--
 arch/arm/mm/proc-arm920.S         |  4 ++--
 arch/arm/mm/proc-arm922.S         |  4 ++--
 arch/arm/mm/proc-arm925.S         |  4 ++--
 arch/arm/mm/proc-arm926.S         |  4 ++--
 arch/arm/mm/proc-arm940.S         |  4 ++--
 arch/arm/mm/proc-arm946.S         |  4 ++--
 arch/arm/mm/proc-feroceon.S       |  8 ++++----
 arch/arm/mm/proc-macros.S         |  2 ++
 arch/arm/mm/proc-mohawk.S         |  4 ++--
 arch/arm/mm/proc-xsc3.S           |  4 ++--
 arch/arm/mm/proc-xscale.S         |  6 ++++--
 25 files changed, 95 insertions(+), 41 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index a094f964c869..04462bfe9130 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -91,6 +91,21 @@
  *	DMA Cache Coherency
  *	===================
  *
+ *	dma_inv_range(start, end)
+ *
+ *		Invalidate (discard) the specified virtual address range.
+ *		May not write back any entries.  If 'start' or 'end'
+ *		are not cache line aligned, those lines must be written
+ *		back.
+ *		- start  - virtual start address
+ *		- end    - virtual end address
+ *
+ *	dma_clean_range(start, end)
+ *
+ *		Clean (write back) the specified virtual address range.
+ *		- start  - virtual start address
+ *		- end    - virtual end address
+ *
  *	dma_flush_range(start, end)
  *
  *		Clean and invalidate the specified virtual address range.
@@ -112,6 +127,8 @@ struct cpu_cache_fns {
 	void (*dma_map_area)(const void *, size_t, int);
 	void (*dma_unmap_area)(const void *, size_t, int);
 
+	void (*dma_clean_range)(const void *, const void *);
+	void (*dma_inv_range)(const void *, const void *);
 	void (*dma_flush_range)(const void *, const void *);
 } __no_randomize_layout;
 
@@ -137,6 +154,8 @@ extern struct cpu_cache_fns cpu_cache;
  * is visible to DMA, or data written by DMA to system memory is
  * visible to the CPU.
  */
+#define dmac_clean_range		cpu_cache.dma_clean_range
+#define dmac_inv_range			cpu_cache.dma_inv_range
 #define dmac_flush_range		cpu_cache.dma_flush_range
 
 #else
@@ -156,6 +175,8 @@ extern void __cpuc_flush_dcache_area(void *, size_t);
  * is visible to DMA, or data written by DMA to system memory is
  * visible to the CPU.
  */
+extern void dmac_clean_range(const void *, const void *);
+extern void dmac_inv_range(const void *, const void *);
 extern void dmac_flush_range(const void *, const void *);
 
 #endif
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index 724f8dac1e5b..d8c93b483adf 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -139,6 +139,8 @@ static inline int nop_coherent_user_range(unsigned long a,
 		unsigned long b) { return 0; }
 static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
 
+static inline void nop_dma_clean_range(const void *a, const void *b) { }
+static inline void nop_dma_inv_range(const void *a, const void *b) { }
 static inline void nop_dma_flush_range(const void *a, const void *b) { }
 
 static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
@@ -155,6 +157,8 @@ static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
 #define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
 #define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
 
+#define dmac_clean_range		__glue(_CACHE,_dma_clean_range)
+#define dmac_inv_range			__glue(_CACHE,_dma_inv_range)
 #define dmac_flush_range		__glue(_CACHE,_dma_flush_range)
 #endif
 
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index 71c64e92dead..b99071577940 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -165,7 +165,7 @@ ENTRY(fa_flush_kern_dcache_area)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-fa_dma_inv_range:
+ENTRY(fa_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c14, 1		@ clean & invalidate D entry
@@ -188,7 +188,7 @@ fa_dma_inv_range:
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-fa_dma_clean_range:
+ENTRY(fa_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
diff --git a/arch/arm/mm/cache-nop.S b/arch/arm/mm/cache-nop.S
index 72d939ef8798..a058544d6c2b 100644
--- a/arch/arm/mm/cache-nop.S
+++ b/arch/arm/mm/cache-nop.S
@@ -32,6 +32,12 @@ ENDPROC(nop_coherent_user_range)
 	.globl nop_flush_kern_dcache_area
 	.equ nop_flush_kern_dcache_area, nop_flush_icache_all
 
+	.globl nop_dma_clean_range
+	.equ nop_dma_clean_range, nop_flush_icache_all
+
+	.globl nop_dma_inv_range
+	.equ nop_dma_inv_range, nop_flush_icache_all
+
 	.globl nop_dma_flush_range
 	.equ nop_dma_flush_range, nop_flush_icache_all
 
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index e2b104876340..b747e591109c 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -103,17 +103,22 @@ ENTRY(v4_flush_kern_dcache_area)
 
 /*
  *	dma_flush_range(start, end)
+ *	dma_inv_range(start, end)
  *
  *	Clean and invalidate the specified virtual address range.
+ *	As only write-through caches are supported here, this is the
+ *	same as invalidate, while the clean operation does nothing.
  *
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
+ENTRY(v4_dma_inv_range)
 ENTRY(v4_dma_flush_range)
 #ifdef CONFIG_CPU_CP15
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c7, 0		@ flush ID cache
 #endif
+ENTRY(v4_dma_clean_range)
 	ret	lr
 
 /*
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index ad382cee0fdb..11794eb305f2 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -182,7 +182,7 @@ ENTRY(v4wb_coherent_user_range)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-v4wb_dma_inv_range:
+ENTRY(v4wb_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -203,7 +203,7 @@ v4wb_dma_inv_range:
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-v4wb_dma_clean_range:
+ENTRY(v4wb_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 652218752f88..1a88627ec09b 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -152,7 +152,7 @@ ENTRY(v4wt_flush_kern_dcache_area)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-v4wt_dma_inv_range:
+ENTRY(v4wt_dma_inv_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
 	add	r0, r0, #CACHE_DLINESIZE
@@ -171,6 +171,18 @@ v4wt_dma_inv_range:
 	.globl	v4wt_dma_flush_range
 	.equ	v4wt_dma_flush_range, v4wt_dma_inv_range
 
+/*
+ *	dma_clean_range(start, end)
+ *
+ *	Clean the specified virtual address range.
+ *	Empty implementation for writethrough caches.
+ *
+ *	- start  - virtual start address
+ *	- end	 - virtual end address
+ */
+	.globl	v4wt_dma_clean_range
+	.equ	v4wt_dma_clean_range, v4wt_dma_unmap_area
+
 /*
  *	dma_map_area(start, size, dir)
  *	- start	- kernel virtual start address
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 250c83bf7158..abae7ff5defc 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -200,7 +200,7 @@ ENTRY(v6_flush_kern_dcache_area)
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v6_dma_inv_range:
+ENTRY(v6_dma_inv_range)
 #ifdef CONFIG_DMA_CACHE_RWFO
 	ldrb	r2, [r0]			@ read for ownership
 	strb	r2, [r0]			@ write for ownership
@@ -245,7 +245,7 @@ v6_dma_inv_range:
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v6_dma_clean_range:
+ENTRY(v6_dma_clean_range)
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
 #ifdef CONFIG_DMA_CACHE_RWFO
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 127afe2096ba..b16a0d2a7cce 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -361,7 +361,7 @@ ENDPROC(v7_flush_kern_dcache_area)
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v7_dma_inv_range:
+ENTRY(v7_dma_inv_range)
 	dcache_line_size r2, r3
 	sub	r3, r2, #1
 	tst	r0, r3
@@ -391,7 +391,7 @@ ENDPROC(v7_dma_inv_range)
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v7_dma_clean_range:
+ENTRY(v7_dma_clean_range)
 	dcache_line_size r2, r3
 	sub	r3, r2, #1
 	bic	r0, r0, r3
@@ -477,6 +477,8 @@ ENDPROC(v7_dma_unmap_area)
 
 	globl_equ	b15_dma_map_area,		v7_dma_map_area
 	globl_equ	b15_dma_unmap_area,		v7_dma_unmap_area
+	globl_equ	b15_dma_clean_range,		v7_dma_clean_range
+	globl_equ	b15_dma_inv_range,		v7_dma_inv_range
 	globl_equ	b15_dma_flush_range,		v7_dma_flush_range
 
 	define_cache_functions b15
diff --git a/arch/arm/mm/cache-v7m.S b/arch/arm/mm/cache-v7m.S
index eb60b5e5e2ad..4fc6e0028e40 100644
--- a/arch/arm/mm/cache-v7m.S
+++ b/arch/arm/mm/cache-v7m.S
@@ -364,7 +364,7 @@ ENDPROC(v7m_flush_kern_dcache_area)
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v7m_dma_inv_range:
+ENTRY(v7m_dma_inv_range)
 	dcache_line_size r2, r3
 	sub	r3, r2, #1
 	tst	r0, r3
@@ -390,7 +390,7 @@ ENDPROC(v7m_dma_inv_range)
  *	- start   - virtual start address of region
  *	- end     - virtual end address of region
  */
-v7m_dma_clean_range:
+ENTRY(v7m_dma_clean_range)
 	dcache_line_size r2, r3
 	sub	r3, r2, #1
 	bic	r0, r0, r3
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 6837cf7a4812..0089e366f4e8 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -263,7 +263,7 @@ ENTRY(arm1020_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm1020_dma_inv_range:
+ENTRY(arm1020_dma_inv_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	tst	r0, #CACHE_DLINESIZE - 1
@@ -293,7 +293,7 @@ arm1020_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm1020_dma_clean_range:
+ENTRY(arm1020_dma_clean_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	bic	r0, r0, #CACHE_DLINESIZE - 1
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index df49b10250b8..c662e55a76fa 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -256,7 +256,7 @@ ENTRY(arm1020e_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm1020e_dma_inv_range:
+ENTRY(arm1020e_dma_inv_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	tst	r0, #CACHE_DLINESIZE - 1
@@ -282,7 +282,7 @@ arm1020e_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm1020e_dma_clean_range:
+ENTRY(arm1020e_dma_clean_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	bic	r0, r0, #CACHE_DLINESIZE - 1
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index e89ce467f672..e77328906bc5 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -256,7 +256,7 @@ ENTRY(arm1022_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm1022_dma_inv_range:
+ENTRY(arm1022_dma_inv_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	tst	r0, #CACHE_DLINESIZE - 1
@@ -282,7 +282,7 @@ arm1022_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm1022_dma_clean_range:
+ENTRY(arm1022_dma_clean_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	bic	r0, r0, #CACHE_DLINESIZE - 1
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 7fdd1a205e8e..a23f9fa28d07 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -250,7 +250,7 @@ ENTRY(arm1026_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm1026_dma_inv_range:
+ENTRY(arm1026_dma_inv_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	tst	r0, #CACHE_DLINESIZE - 1
@@ -276,7 +276,7 @@ arm1026_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm1026_dma_clean_range:
+ENTRY(arm1026_dma_clean_range)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
 	bic	r0, r0, #CACHE_DLINESIZE - 1
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index a234cd8ba5e6..4c918ab106f3 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -232,7 +232,7 @@ ENTRY(arm920_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm920_dma_inv_range:
+ENTRY(arm920_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -255,7 +255,7 @@ arm920_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm920_dma_clean_range:
+ENTRY(arm920_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 53c029dcfd83..6ac7bb7d94a4 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -234,7 +234,7 @@ ENTRY(arm922_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm922_dma_inv_range:
+ENTRY(arm922_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -257,7 +257,7 @@ arm922_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm922_dma_clean_range:
+ENTRY(arm922_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 0bfad62ea858..860f0074ff81 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -280,7 +280,7 @@ ENTRY(arm925_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm925_dma_inv_range:
+ENTRY(arm925_dma_inv_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -305,7 +305,7 @@ arm925_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm925_dma_clean_range:
+ENTRY(arm925_dma_clean_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 0487a2c3439b..519f62e023c5 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -243,7 +243,7 @@ ENTRY(arm926_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-arm926_dma_inv_range:
+ENTRY(arm926_dma_inv_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -268,7 +268,7 @@ arm926_dma_inv_range:
  *
  * (same as v4wb)
  */
-arm926_dma_clean_range:
+ENTRY(arm926_dma_clean_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index cf9bfcc825ca..14dda5c5ee4a 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -177,7 +177,7 @@ ENTRY(arm940_flush_kern_dcache_area)
  *	- start	- virtual start address
  *	- end	- virtual end address
  */
-arm940_dma_inv_range:
+ENTRY(arm940_dma_inv_range)
 	mov	ip, #0
 	mov	r1, #(CACHE_DSEGMENTS - 1) << 4	@ 4 segments
 1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -198,7 +198,7 @@ arm940_dma_inv_range:
  *	- start	- virtual start address
  *	- end	- virtual end address
  */
-arm940_dma_clean_range:
+ENTRY(arm940_dma_clean_range)
 ENTRY(cpu_arm940_dcache_clean_area)
 	mov	ip, #0
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 6fb3898ad1cd..91f62a7d334b 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -222,7 +222,7 @@ ENTRY(arm946_flush_kern_dcache_area)
  *	- end	- virtual end address
  * (same as arm926)
  */
-arm946_dma_inv_range:
+ENTRY(arm946_dma_inv_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -247,7 +247,7 @@ arm946_dma_inv_range:
  *
  * (same as arm926)
  */
-arm946_dma_clean_range:
+ENTRY(arm946_dma_clean_range)
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 61ce82aca6f0..86122bad6d9b 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -271,7 +271,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area)
  * (same as v4wb)
  */
 	.align	5
-feroceon_dma_inv_range:
+ENTRY(feroceon_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -285,7 +285,7 @@ feroceon_dma_inv_range:
 	ret	lr
 
 	.align	5
-feroceon_range_dma_inv_range:
+ENTRY(feroceon_range_dma_inv_range)
 	mrs	r2, cpsr
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -311,7 +311,7 @@ feroceon_range_dma_inv_range:
  * (same as v4wb)
  */
 	.align	5
-feroceon_dma_clean_range:
+ENTRY(feroceon_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
@@ -321,7 +321,7 @@ feroceon_dma_clean_range:
 	ret	lr
 
 	.align	5
-feroceon_range_dma_clean_range:
+ENTRY(feroceon_range_dma_clean_range)
 	mrs	r2, cpsr
 	cmp	r1, r0
 	subne	r1, r1, #1			@ top address is inclusive
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index e43f6d716b4b..c1328955fd2a 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -334,6 +334,8 @@ ENTRY(\name\()_cache_fns)
 	.long	\name\()_flush_kern_dcache_area
 	.long	\name\()_dma_map_area
 	.long	\name\()_dma_unmap_area
+	.long	\name\()_dma_clean_range
+	.long	\name\()_dma_inv_range
 	.long	\name\()_dma_flush_range
 	.size	\name\()_cache_fns, . - \name\()_cache_fns
 .endm
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 1645ccaffe96..db3a2f00372a 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -216,7 +216,7 @@ ENTRY(mohawk_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-mohawk_dma_inv_range:
+ENTRY(mohawk_dma_inv_range)
 	tst	r0, #CACHE_DLINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
 	tst	r1, #CACHE_DLINESIZE - 1
@@ -239,7 +239,7 @@ mohawk_dma_inv_range:
  *
  * (same as v4wb)
  */
-mohawk_dma_clean_range:
+ENTRY(mohawk_dma_clean_range)
 	bic	r0, r0, #CACHE_DLINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHE_DLINESIZE
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index a17afe7e195a..6db611a945f3 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -263,7 +263,7 @@ ENTRY(xsc3_flush_kern_dcache_area)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-xsc3_dma_inv_range:
+ENTRY(xsc3_dma_inv_range)
 	tst	r0, #CACHELINESIZE - 1
 	bic	r0, r0, #CACHELINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean L1 D line
@@ -284,7 +284,7 @@ xsc3_dma_inv_range:
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-xsc3_dma_clean_range:
+ENTRY(xsc3_dma_clean_range)
 	bic	r0, r0, #CACHELINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
 	add	r0, r0, #CACHELINESIZE
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index d82590aa71c0..291dec830714 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -323,7 +323,7 @@ ENTRY(xscale_flush_kern_dcache_area)
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-xscale_dma_inv_range:
+ENTRY(xscale_dma_inv_range)
 	tst	r0, #CACHELINESIZE - 1
 	bic	r0, r0, #CACHELINESIZE - 1
 	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
@@ -344,7 +344,7 @@ xscale_dma_inv_range:
  *	- start  - virtual start address
  *	- end	 - virtual end address
  */
-xscale_dma_clean_range:
+ENTRY(xscale_dma_clean_range)
 	bic	r0, r0, #CACHELINESIZE - 1
 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
 	add	r0, r0, #CACHELINESIZE
@@ -445,6 +445,8 @@ ENDPROC(xscale_dma_unmap_area)
 	a0_alias coherent_kern_range
 	a0_alias coherent_user_range
 	a0_alias flush_kern_dcache_area
+	a0_alias dma_clean_range
+	a0_alias dma_inv_range
 	a0_alias dma_flush_range
 	a0_alias dma_unmap_area
 
-- 
2.41.0


From 313b703a908a8035ce8af04d679e6154086b8aec Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:13 +0200
Subject: [PATCH 19/72] ARM: dma-mapping: use arch_sync_dma_for_{device,cpu}()
 internally

The arm specific iommu code in dma-mapping.c uses the page+offset based
__dma_page_cpu_to_dev()/__dma_page_dev_to_cpu() helpers in place of the
phys_addr_t based arch_sync_dma_for_device()/arch_sync_dma_for_cpu()
wrappers around the.

In order to be able to move the latter part set of functions into
common code, change the iommu implementation to use them directly
and remove the internal ones as a separate interface.

As page+offset and phys_address are equivalent, but are used in
different parts of the code here, this allows removing some of
the conversion but adds them elsewhere.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230327121317.4081816-18-arnd@kernel.org
---
 arch/arm/mm/dma-mapping.c | 93 ++++++++++++++-------------------------
 1 file changed, 33 insertions(+), 60 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 033a1bce2b17..442d69198fbc 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -624,16 +624,14 @@ static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 	kfree(buf);
 }
 
-static void dma_cache_maint_page(struct page *page, unsigned long offset,
+static void dma_cache_maint(phys_addr_t paddr,
 	size_t size, enum dma_data_direction dir,
 	void (*op)(const void *, size_t, int))
 {
-	unsigned long pfn;
+	unsigned long pfn = PFN_DOWN(paddr);
+	unsigned long offset = paddr % PAGE_SIZE;
 	size_t left = size;
 
-	pfn = page_to_pfn(page) + offset / PAGE_SIZE;
-	offset %= PAGE_SIZE;
-
 	/*
 	 * A single sg entry may refer to multiple physically contiguous
 	 * pages.  But we still need to process highmem pages individually.
@@ -643,8 +641,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
 	do {
 		size_t len = left;
 		void *vaddr;
-
-		page = pfn_to_page(pfn);
+		struct page *page = pfn_to_page(pfn);
 
 		if (PageHighMem(page)) {
 			if (len + offset > PAGE_SIZE)
@@ -676,14 +673,11 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
  * Note: Drivers should NOT use this function directly.
  * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
  */
-static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
-	size_t size, enum dma_data_direction dir)
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
+		enum dma_data_direction dir)
 {
-	phys_addr_t paddr;
+	dma_cache_maint(paddr, size, dir, dmac_map_area);
 
-	dma_cache_maint_page(page, off, size, dir, dmac_map_area);
-
-	paddr = page_to_phys(page) + off;
 	if (dir == DMA_FROM_DEVICE) {
 		outer_inv_range(paddr, paddr + size);
 	} else {
@@ -692,34 +686,30 @@ static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
 	/* FIXME: non-speculating: flush on bidirectional mappings? */
 }
 
-static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
-	size_t size, enum dma_data_direction dir)
+void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
+		enum dma_data_direction dir)
 {
-	phys_addr_t paddr = page_to_phys(page) + off;
-
 	/* FIXME: non-speculating: not required */
 	/* in any case, don't bother invalidating if DMA to device */
 	if (dir != DMA_TO_DEVICE) {
 		outer_inv_range(paddr, paddr + size);
 
-		dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+		dma_cache_maint(paddr, size, dir, dmac_unmap_area);
 	}
 
 	/*
 	 * Mark the D-cache clean for these pages to avoid extra flushing.
 	 */
 	if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
-		unsigned long pfn;
+		unsigned long pfn = PFN_UP(paddr);
+		unsigned long off = paddr & (PAGE_SIZE - 1);
 		size_t left = size;
 
-		pfn = page_to_pfn(page) + off / PAGE_SIZE;
-		off %= PAGE_SIZE;
-		if (off) {
-			pfn++;
+		if (off)
 			left -= PAGE_SIZE - off;
-		}
+
 		while (left >= PAGE_SIZE) {
-			page = pfn_to_page(pfn++);
+			struct page *page = pfn_to_page(pfn++);
 			set_bit(PG_dcache_clean, &page->flags);
 			left -= PAGE_SIZE;
 		}
@@ -1206,7 +1196,7 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
 		unsigned int len = PAGE_ALIGN(s->offset + s->length);
 
 		if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
-			__dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
+			arch_sync_dma_for_device(phys + s->offset, s->length, dir);
 
 		prot = __dma_info_to_prot(dir, attrs);
 
@@ -1308,8 +1298,7 @@ static void arm_iommu_unmap_sg(struct device *dev,
 			__iommu_remove_mapping(dev, sg_dma_address(s),
 					       sg_dma_len(s));
 		if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
-			__dma_page_dev_to_cpu(sg_page(s), s->offset,
-					      s->length, dir);
+			arch_sync_dma_for_cpu(sg_phys(s), s->length, dir);
 	}
 }
 
@@ -1331,7 +1320,7 @@ static void arm_iommu_sync_sg_for_cpu(struct device *dev,
 		return;
 
 	for_each_sg(sg, s, nents, i)
-		__dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
+		arch_sync_dma_for_cpu(sg_phys(s), s->length, dir);
 
 }
 
@@ -1353,7 +1342,8 @@ static void arm_iommu_sync_sg_for_device(struct device *dev,
 		return;
 
 	for_each_sg(sg, s, nents, i)
-		__dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
+		arch_sync_dma_for_device(page_to_phys(sg_page(s)) + s->offset,
+					 s->length, dir);
 }
 
 /**
@@ -1375,7 +1365,8 @@ static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
 	int ret, prot, len = PAGE_ALIGN(size + offset);
 
 	if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
-		__dma_page_cpu_to_dev(page, offset, size, dir);
+		arch_sync_dma_for_device(page_to_phys(page) + offset,
+					 size, dir);
 
 	dma_addr = __alloc_iova(mapping, len);
 	if (dma_addr == DMA_MAPPING_ERROR)
@@ -1408,7 +1399,7 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
 {
 	struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
 	dma_addr_t iova = handle & PAGE_MASK;
-	struct page *page;
+	phys_addr_t phys;
 	int offset = handle & ~PAGE_MASK;
 	int len = PAGE_ALIGN(size + offset);
 
@@ -1416,8 +1407,8 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
 		return;
 
 	if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
-		page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
-		__dma_page_dev_to_cpu(page, offset, size, dir);
+		phys = iommu_iova_to_phys(mapping->domain, handle);
+		arch_sync_dma_for_cpu(phys, size, dir);
 	}
 
 	iommu_unmap(mapping->domain, iova, len);
@@ -1485,30 +1476,26 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
 		dma_addr_t handle, size_t size, enum dma_data_direction dir)
 {
 	struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
-	dma_addr_t iova = handle & PAGE_MASK;
-	struct page *page;
-	unsigned int offset = handle & ~PAGE_MASK;
+	phys_addr_t phys;
 
-	if (dev->dma_coherent || !iova)
+	if (dev->dma_coherent || !(handle & PAGE_MASK))
 		return;
 
-	page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
-	__dma_page_dev_to_cpu(page, offset, size, dir);
+	phys = iommu_iova_to_phys(mapping->domain, handle);
+	arch_sync_dma_for_cpu(phys, size, dir);
 }
 
 static void arm_iommu_sync_single_for_device(struct device *dev,
 		dma_addr_t handle, size_t size, enum dma_data_direction dir)
 {
 	struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
-	dma_addr_t iova = handle & PAGE_MASK;
-	struct page *page;
-	unsigned int offset = handle & ~PAGE_MASK;
+	phys_addr_t phys;
 
-	if (dev->dma_coherent || !iova)
+	if (dev->dma_coherent || !(handle & PAGE_MASK))
 		return;
 
-	page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
-	__dma_page_cpu_to_dev(page, offset, size, dir);
+	phys = iommu_iova_to_phys(mapping->domain, handle);
+	arch_sync_dma_for_device(phys, size, dir);
 }
 
 static const struct dma_map_ops iommu_ops = {
@@ -1791,20 +1778,6 @@ void arch_teardown_dma_ops(struct device *dev)
 	set_dma_ops(dev, NULL);
 }
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
-{
-	__dma_page_cpu_to_dev(phys_to_page(paddr), paddr & (PAGE_SIZE - 1),
-			      size, dir);
-}
-
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
-{
-	__dma_page_dev_to_cpu(phys_to_page(paddr), paddr & (PAGE_SIZE - 1),
-			      size, dir);
-}
-
 void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
 		gfp_t gfp, unsigned long attrs)
 {
-- 
2.41.0


From 70fc47ae2e44aec4ae7905e6a8449a3aca13b1ea Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:15 +0200
Subject: [PATCH 20/72] ARM: dma-mapping: use generic form of arch_sync_dma_*
 helpers

As the final step of the conversion to generic arch_sync_dma_*
helpers, change the Arm implementation to look the same as the
new generic version, by calling the dmac_{clean,inv,flush}_area
low-level functions instead of the abstracted dmac_{map,unmap}_area
version.

On ARMv6/v7, this invalidates the caches after a DMA transfer from
a device because of speculative prefetching, while on earlier versions
it only needs to do this before the transfer.

This should not change any of the current behavior.

FIXME: address CONFIG_DMA_CACHE_RWFO properly.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-20-arnd@kernel.org
---
 arch/arm/mm/dma-mapping-nommu.c | 11 +++----
 arch/arm/mm/dma-mapping.c       | 53 +++++++++++++++++++++++----------
 2 files changed, 43 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c
index cfd9c933d2f0..12b5c6ae93fc 100644
--- a/arch/arm/mm/dma-mapping-nommu.c
+++ b/arch/arm/mm/dma-mapping-nommu.c
@@ -16,12 +16,13 @@
 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
-	dmac_map_area(__va(paddr), size, dir);
-
-	if (dir == DMA_FROM_DEVICE)
+	if (dir == DMA_FROM_DEVICE) {
+		dmac_inv_range(__va(paddr), __va(paddr + size));
 		outer_inv_range(paddr, paddr + size);
-	else
+	} else {
+		dmac_clean_range(__va(paddr), __va(paddr + size));
 		outer_clean_range(paddr, paddr + size);
+	}
 }
 
 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
@@ -29,7 +30,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 {
 	if (dir != DMA_TO_DEVICE) {
 		outer_inv_range(paddr, paddr + size);
-		dmac_unmap_area(__va(paddr), size, dir);
+		dmac_inv_range(__va(paddr), __va(paddr));
 	}
 }
 
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 442d69198fbc..64b813a547ec 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -625,8 +625,7 @@ static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 }
 
 static void dma_cache_maint(phys_addr_t paddr,
-	size_t size, enum dma_data_direction dir,
-	void (*op)(const void *, size_t, int))
+	size_t size, void (*op)(const void *, const void *))
 {
 	unsigned long pfn = PFN_DOWN(paddr);
 	unsigned long offset = paddr % PAGE_SIZE;
@@ -649,18 +648,18 @@ static void dma_cache_maint(phys_addr_t paddr,
 
 			if (cache_is_vipt_nonaliasing()) {
 				vaddr = kmap_atomic(page);
-				op(vaddr + offset, len, dir);
+				op(vaddr + offset, vaddr + offset + len);
 				kunmap_atomic(vaddr);
 			} else {
 				vaddr = kmap_high_get(page);
 				if (vaddr) {
-					op(vaddr + offset, len, dir);
+					op(vaddr + offset, vaddr + offset + len);
 					kunmap_high(page);
 				}
 			}
 		} else {
 			vaddr = page_address(page) + offset;
-			op(vaddr, len, dir);
+			op(vaddr, vaddr + len);
 		}
 		offset = 0;
 		pfn++;
@@ -668,6 +667,18 @@ static void dma_cache_maint(phys_addr_t paddr,
 	} while (left);
 }
 
+static bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_V6) ||
+	    IS_ENABLED(CONFIG_CPU_V6K) ||
+	    IS_ENABLED(CONFIG_CPU_V7) ||
+	    IS_ENABLED(CONFIG_CPU_V7M))
+		return true;
+
+	/* FIXME: runtime detection */
+	return false;
+}
+
 /*
  * Make an area consistent for devices.
  * Note: Drivers should NOT use this function directly.
@@ -676,25 +687,35 @@ static void dma_cache_maint(phys_addr_t paddr,
 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
-	dma_cache_maint(paddr, size, dir, dmac_map_area);
-
-	if (dir == DMA_FROM_DEVICE) {
-		outer_inv_range(paddr, paddr + size);
-	} else {
+	switch (dir) {
+	case DMA_TO_DEVICE:
+		dma_cache_maint(paddr, size, dmac_clean_range);
 		outer_clean_range(paddr, paddr + size);
+		break;
+	case DMA_FROM_DEVICE:
+		dma_cache_maint(paddr, size, dmac_inv_range);
+		outer_inv_range(paddr, paddr + size);
+		break;
+	case DMA_BIDIRECTIONAL:
+		if (arch_sync_dma_cpu_needs_post_dma_flush()) {
+			dma_cache_maint(paddr, size, dmac_clean_range);
+			outer_clean_range(paddr, paddr + size);
+		} else {
+			dma_cache_maint(paddr, size, dmac_flush_range);
+			outer_flush_range(paddr, paddr + size);
+		}
+		break;
+	default:
+		break;
 	}
-	/* FIXME: non-speculating: flush on bidirectional mappings? */
 }
 
 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 		enum dma_data_direction dir)
 {
-	/* FIXME: non-speculating: not required */
-	/* in any case, don't bother invalidating if DMA to device */
-	if (dir != DMA_TO_DEVICE) {
+	if (dir != DMA_TO_DEVICE && arch_sync_dma_cpu_needs_post_dma_flush()) {
 		outer_inv_range(paddr, paddr + size);
-
-		dma_cache_maint(paddr, size, dir, dmac_unmap_area);
+		dma_cache_maint(paddr, size, dmac_inv_range);
 	}
 
 	/*
-- 
2.41.0


From 2b9ab2ba7741334c5d1645c9c8f54547481c18eb Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:16 +0200
Subject: [PATCH 21/72] ARM: dma-mapping: split out arch_dma_mark_clean()
 helper

The arm version of the arch_sync_dma_for_cpu() function annotates pages as
PG_dcache_clean after a DMA, but no other architecture does this here. On
ia64, the same thing is done in arch_sync_dma_for_cpu(), so it makes sense
to use the same hook in order to have identical arch_sync_dma_for_cpu()
semantics as all other architectures.

Splitting this out has multiple effects:

 - for dma-direct, this now gets called after arch_sync_dma_for_cpu()
   for DMA_FROM_DEVICE mappings, but not for DMA_BIDIRECTIONAL. While
   it would not be harmful to keep doing it for bidirectional mappings,
   those are apparently not used in any callers that care about the flag.

 - Since arm has its own dma-iommu abstraction, this now also needs to
   call the same function, so the calls are added there to mirror the
   dma-direct version.

 - Like dma-direct, the dma-iommu version now marks the dcache clean
   for both coherent and noncoherent devices after a DMA, but it only
   does this for DMA_FROM_DEVICE, not DMA_BIDIRECTIONAL.

[ HELP NEEDED: can anyone confirm that it is a correct assumption
  on arm that a cache-coherent device writing to a page always results
  in it being in a PG_dcache_clean state like on ia64, or can a device
  write directly into the dcache?]

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230327121317.4081816-21-arnd@kernel.org
---
 arch/arm/Kconfig          |  1 +
 arch/arm/mm/dma-mapping.c | 71 +++++++++++++++++++++++----------------
 2 files changed, 43 insertions(+), 29 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a27550ff3c1..d16842e6a342 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -8,6 +8,7 @@ config ARM
 	select ARCH_HAS_CPU_FINALIZE_INIT if MMU
 	select ARCH_HAS_CURRENT_STACK_POINTER
 	select ARCH_HAS_DEBUG_VIRTUAL if MMU
+	select ARCH_HAS_DMA_MARK_CLEAN if MMU
 	select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
 	select ARCH_HAS_ELF_RANDOMIZE
 	select ARCH_HAS_FORTIFY_SOURCE
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 64b813a547ec..71fc2a0283f8 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -667,6 +667,28 @@ static void dma_cache_maint(phys_addr_t paddr,
 	} while (left);
 }
 
+/*
+ * Mark the D-cache clean for these pages to avoid extra flushing.
+ */
+void arch_dma_mark_clean(phys_addr_t paddr, size_t size)
+{
+	unsigned long pfn = PFN_UP(paddr);
+	unsigned long off = paddr & (PAGE_SIZE - 1);
+	size_t left = size;
+
+	if (size < PAGE_SIZE)
+		return;
+
+	if (off)
+		left -= PAGE_SIZE - off;
+
+	while (left >= PAGE_SIZE) {
+		struct page *page = pfn_to_page(pfn++);
+		set_bit(PG_dcache_clean, &page->flags);
+		left -= PAGE_SIZE;
+	}
+}
+
 static bool arch_sync_dma_cpu_needs_post_dma_flush(void)
 {
 	if (IS_ENABLED(CONFIG_CPU_V6) ||
@@ -717,24 +739,6 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
 		outer_inv_range(paddr, paddr + size);
 		dma_cache_maint(paddr, size, dmac_inv_range);
 	}
-
-	/*
-	 * Mark the D-cache clean for these pages to avoid extra flushing.
-	 */
-	if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
-		unsigned long pfn = PFN_UP(paddr);
-		unsigned long off = paddr & (PAGE_SIZE - 1);
-		size_t left = size;
-
-		if (off)
-			left -= PAGE_SIZE - off;
-
-		while (left >= PAGE_SIZE) {
-			struct page *page = pfn_to_page(pfn++);
-			set_bit(PG_dcache_clean, &page->flags);
-			left -= PAGE_SIZE;
-		}
-	}
 }
 
 #ifdef CONFIG_ARM_DMA_USE_IOMMU
@@ -1296,6 +1300,17 @@ static int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
 	return -EINVAL;
 }
 
+static void arm_iommu_sync_dma_for_cpu(phys_addr_t phys, size_t len,
+				       enum dma_data_direction dir,
+				       bool dma_coherent)
+{
+	if (!dma_coherent)
+		arch_sync_dma_for_cpu(phys, len, dir);
+
+	if (dir == DMA_FROM_DEVICE)
+		arch_dma_mark_clean(phys, len);
+}
+
 /**
  * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
  * @dev: valid struct device pointer
@@ -1318,8 +1333,9 @@ static void arm_iommu_unmap_sg(struct device *dev,
 		if (sg_dma_len(s))
 			__iommu_remove_mapping(dev, sg_dma_address(s),
 					       sg_dma_len(s));
-		if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
-			arch_sync_dma_for_cpu(sg_phys(s), s->length, dir);
+		if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
+			arm_iommu_sync_dma_for_cpu(sg_phys(s), s->length, dir,
+						   dev->dma_coherent);
 	}
 }
 
@@ -1337,12 +1353,9 @@ static void arm_iommu_sync_sg_for_cpu(struct device *dev,
 	struct scatterlist *s;
 	int i;
 
-	if (dev->dma_coherent)
-		return;
-
 	for_each_sg(sg, s, nents, i)
-		arch_sync_dma_for_cpu(sg_phys(s), s->length, dir);
-
+		arm_iommu_sync_dma_for_cpu(sg_phys(s), s->length, dir,
+					   dev->dma_coherent);
 }
 
 /**
@@ -1427,9 +1440,9 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
 	if (!iova)
 		return;
 
-	if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
+	if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
 		phys = iommu_iova_to_phys(mapping->domain, handle);
-		arch_sync_dma_for_cpu(phys, size, dir);
+		arm_iommu_sync_dma_for_cpu(phys, size, dir, dev->dma_coherent);
 	}
 
 	iommu_unmap(mapping->domain, iova, len);
@@ -1499,11 +1512,11 @@ static void arm_iommu_sync_single_for_cpu(struct device *dev,
 	struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
 	phys_addr_t phys;
 
-	if (dev->dma_coherent || !(handle & PAGE_MASK))
+	if (!(handle & PAGE_MASK))
 		return;
 
 	phys = iommu_iova_to_phys(mapping->domain, handle);
-	arch_sync_dma_for_cpu(phys, size, dir);
+	arm_iommu_sync_dma_for_cpu(phys, size, dir, dev->dma_coherent);
 }
 
 static void arm_iommu_sync_single_for_device(struct device *dev,
-- 
2.41.0


From e21544cf39619f4f2427770939eb71b8f19c5094 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 27 Mar 2023 14:13:17 +0200
Subject: [PATCH 22/72] dma-mapping: replace custom code with generic
 implementation

Now that all of these have consistent behavior, replace them with
a single shared implementation of arch_sync_dma_for_device() and
arch_sync_dma_for_cpu() and three parameters to pick how they should
operate:

 - If the CPU has speculative prefetching, then the cache
   has to be invalidated after a transfer from the device.
   On the rarer CPUs without prefetching, this can be skipped,
   with all cache management happening before the transfer.
   This flag can be runtime detected, but is usually fixed
   per architecture.

 - Some architectures currently clean the caches before DMA
   from a device, while others invalidate it. There has not
   been a conclusion regarding whether we should change all
   architectures to use clean instead, so this adds an
   architecture specific flag that we can change later on.

 - On 32-bit Arm, the arch_sync_dma_for_cpu() function keeps
   track pages that are marked clean in the page cache, to
   avoid flushing them again. The implementation for this is
   generic enough to work on all architectures that use the
   PG_dcache_clean page flag, but a Kconfig symbol is used
   to only enable it on Arm to preserve the existing behavior.

For the function naming, I picked 'wback' over 'clean', and 'wback_inv'
over 'flush', to avoid any ambiguity of what the helper functions are
supposed to do.

Moving the global functions into a header file is usually a bad idea
as it prevents the header from being included more than once, but it
helps keep the behavior as close as possible to the previous state,
including the possibility of inlining most of it into these functions
where that was done before. This also helps keep the global namespace
clean, by hiding the new arch_dma_cache{_wback,_inv,_wback_inv} from
device drivers that might use them incorrectly.

It would be possible to do this one architecture at a time, but
as the change is the same everywhere, the combined patch helps
explain it better once.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20230327121317.4081816-22-arnd@kernel.org
---
 arch/arc/mm/dma.c                    |  66 +++++------------
 arch/arm/Kconfig                     |   3 +
 arch/arm/mm/dma-mapping-nommu.c      |  39 ++++++----
 arch/arm/mm/dma-mapping.c            |  64 +++++++---------
 arch/arm64/mm/dma-mapping.c          |  28 ++++---
 arch/csky/mm/dma-mapping.c           |  44 ++++++-----
 arch/hexagon/kernel/dma.c            |  44 ++++++-----
 arch/m68k/kernel/dma.c               |  43 +++++++----
 arch/microblaze/kernel/dma.c         |  48 ++++++------
 arch/mips/mm/dma-noncoherent.c       |  60 ++++++---------
 arch/nios2/mm/dma-mapping.c          |  57 +++++++-------
 arch/openrisc/kernel/dma.c           |  63 ++++++++++------
 arch/parisc/include/asm/cacheflush.h |   2 +
 arch/parisc/kernel/pci-dma.c         |  39 ++++++----
 arch/powerpc/mm/dma-noncoherent.c    |  36 +++++----
 arch/riscv/mm/dma-noncoherent.c      |  51 ++++++-------
 arch/sh/kernel/dma-coherent.c        |  43 +++++++----
 arch/sparc/kernel/ioport.c           |  38 +++++++---
 arch/xtensa/kernel/pci-dma.c         |  40 ++++++----
 include/linux/dma-sync.h             | 107 +++++++++++++++++++++++++++
 20 files changed, 530 insertions(+), 385 deletions(-)
 create mode 100644 include/linux/dma-sync.h

diff --git a/arch/arc/mm/dma.c b/arch/arc/mm/dma.c
index ddb96786f765..61cd01646222 100644
--- a/arch/arc/mm/dma.c
+++ b/arch/arc/mm/dma.c
@@ -30,63 +30,33 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
 	dma_cache_wback_inv(page_to_phys(page), size);
 }
 
-/*
- * Cache operations depending on function and direction argument, inspired by
- * https://lore.kernel.org/lkml/20180518175004.GF17671@n2100.armlinux.org.uk
- * "dma_sync_*_for_cpu and direction=TO_DEVICE (was Re: [PATCH 02/20]
- * dma-mapping: provide a generic dma-noncoherent implementation)"
- *
- *          |   map          ==  for_device     |   unmap     ==  for_cpu
- *          |----------------------------------------------------------------
- * TO_DEV   |   writeback        writeback      |   none          none
- * FROM_DEV |   invalidate       invalidate     |   invalidate*   invalidate*
- * BIDIR    |   writeback        writeback      |   invalidate    invalidate
- *
- *     [*] needed for CPU speculative prefetches
- *
- * NOTE: we don't check the validity of direction argument as it is done in
- * upper layer functions (in include/linux/dma-mapping.h)
- */
-
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		dma_cache_wback(paddr, size);
-		break;
-
-	case DMA_FROM_DEVICE:
-		dma_cache_inv(paddr, size);
-		break;
-
-	case DMA_BIDIRECTIONAL:
-		dma_cache_wback(paddr, size);
-		break;
+	dma_cache_wback(paddr, size);
+}
 
-	default:
-		break;
-	}
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	dma_cache_inv(paddr, size);
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
 {
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		break;
+	dma_cache_wback_inv(paddr, size);
+}
 
-	/* FROM_DEVICE invalidate needed if speculative CPU prefetch only */
-	case DMA_FROM_DEVICE:
-	case DMA_BIDIRECTIONAL:
-		dma_cache_inv(paddr, size);
-		break;
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
 
-	default:
-		break;
-	}
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return true;
 }
 
+#include <linux/dma-sync.h>
+
 /*
  * Plug in direct dma map ops.
  */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d16842e6a342..3096c77fd891 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -215,6 +215,9 @@ config LOCKDEP_SUPPORT
 	bool
 	default y
 
+config ARCH_DMA_MARK_DCACHE_CLEAN
+	def_bool y
+
 config ARCH_HAS_ILOG2_U32
 	bool
 
diff --git a/arch/arm/mm/dma-mapping-nommu.c b/arch/arm/mm/dma-mapping-nommu.c
index 12b5c6ae93fc..0817274aed15 100644
--- a/arch/arm/mm/dma-mapping-nommu.c
+++ b/arch/arm/mm/dma-mapping-nommu.c
@@ -13,27 +13,36 @@
 
 #include "dma.h"
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	if (dir == DMA_FROM_DEVICE) {
-		dmac_inv_range(__va(paddr), __va(paddr + size));
-		outer_inv_range(paddr, paddr + size);
-	} else {
-		dmac_clean_range(__va(paddr), __va(paddr + size));
-		outer_clean_range(paddr, paddr + size);
-	}
+	dmac_clean_range(__va(paddr), __va(paddr + size));
+	outer_clean_range(paddr, paddr + size);
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
-	if (dir != DMA_TO_DEVICE) {
-		outer_inv_range(paddr, paddr + size);
-		dmac_inv_range(__va(paddr), __va(paddr));
-	}
+	dmac_inv_range(__va(paddr), __va(paddr + size));
+	outer_inv_range(paddr, paddr + size);
 }
 
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	dmac_flush_range(__va(paddr), __va(paddr + size));
+	outer_flush_range(paddr, paddr + size);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return true;
+}
+
+#include <linux/dma-sync.h>
+
 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 			const struct iommu_ops *iommu, bool coherent)
 {
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 71fc2a0283f8..a7fd0d05d047 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -689,6 +689,30 @@ void arch_dma_mark_clean(phys_addr_t paddr, size_t size)
 	}
 }
 
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
+{
+	dma_cache_maint(paddr, size, dmac_clean_range);
+	outer_clean_range(paddr, paddr + size);
+}
+
+
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	dma_cache_maint(paddr, size, dmac_inv_range);
+	outer_inv_range(paddr, paddr + size);
+}
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	dma_cache_maint(paddr, size, dmac_flush_range);
+	outer_flush_range(paddr, paddr + size);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
+
 static bool arch_sync_dma_cpu_needs_post_dma_flush(void)
 {
 	if (IS_ENABLED(CONFIG_CPU_V6) ||
@@ -701,45 +725,7 @@ static bool arch_sync_dma_cpu_needs_post_dma_flush(void)
 	return false;
 }
 
-/*
- * Make an area consistent for devices.
- * Note: Drivers should NOT use this function directly.
- * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
- */
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
-{
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		dma_cache_maint(paddr, size, dmac_clean_range);
-		outer_clean_range(paddr, paddr + size);
-		break;
-	case DMA_FROM_DEVICE:
-		dma_cache_maint(paddr, size, dmac_inv_range);
-		outer_inv_range(paddr, paddr + size);
-		break;
-	case DMA_BIDIRECTIONAL:
-		if (arch_sync_dma_cpu_needs_post_dma_flush()) {
-			dma_cache_maint(paddr, size, dmac_clean_range);
-			outer_clean_range(paddr, paddr + size);
-		} else {
-			dma_cache_maint(paddr, size, dmac_flush_range);
-			outer_flush_range(paddr, paddr + size);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
-{
-	if (dir != DMA_TO_DEVICE && arch_sync_dma_cpu_needs_post_dma_flush()) {
-		outer_inv_range(paddr, paddr + size);
-		dma_cache_maint(paddr, size, dmac_inv_range);
-	}
-}
+#include <linux/dma-sync.h>
 
 #ifdef CONFIG_ARM_DMA_USE_IOMMU
 
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 3cb101e8cb29..97b7cea5eb23 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -13,25 +13,33 @@
 #include <asm/cacheflush.h>
 #include <asm/xen/xen-ops.h>
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-			      enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	unsigned long start = (unsigned long)phys_to_virt(paddr);
+	dcache_clean_poc(paddr, paddr + size);
+}
 
-	dcache_clean_poc(start, start + size);
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	dcache_inval_poc(paddr, paddr + size);
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-			   enum dma_data_direction dir)
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
 {
-	unsigned long start = (unsigned long)phys_to_virt(paddr);
+	dcache_clean_inval_poc(paddr, paddr + size);
+}
 
-	if (dir == DMA_TO_DEVICE)
-		return;
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return true;
+}
 
-	dcache_inval_poc(start, start + size);
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return true;
 }
 
+#include <linux/dma-sync.h>
+
 void arch_dma_prep_coherent(struct page *page, size_t size)
 {
 	unsigned long start = (unsigned long)page_address(page);
diff --git a/arch/csky/mm/dma-mapping.c b/arch/csky/mm/dma-mapping.c
index c90f912e2822..9402e101b363 100644
--- a/arch/csky/mm/dma-mapping.c
+++ b/arch/csky/mm/dma-mapping.c
@@ -55,31 +55,29 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
 	cache_op(page_to_phys(page), size, dma_wbinv_set_zero_range);
 }
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	switch (dir) {
-	case DMA_TO_DEVICE:
-	case DMA_FROM_DEVICE:
-	case DMA_BIDIRECTIONAL:
-		cache_op(paddr, size, dma_wb_range);
-		break;
-	default:
-		BUG();
-	}
+	cache_op(paddr, size, dma_wb_range);
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		return;
-	case DMA_FROM_DEVICE:
-	case DMA_BIDIRECTIONAL:
-		cache_op(paddr, size, dma_inv_range);
-		break;
-	default:
-		BUG();
-	}
+	cache_op(paddr, size, dma_inv_range);
 }
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	cache_op(paddr, size, dma_wbinv_range);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return true;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return true;
+}
+
+#include <linux/dma-sync.h>
diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c
index 882680e81a30..033d06074618 100644
--- a/arch/hexagon/kernel/dma.c
+++ b/arch/hexagon/kernel/dma.c
@@ -9,29 +9,33 @@
 #include <linux/memblock.h>
 #include <asm/page.h>
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	void *addr = phys_to_virt(paddr);
-
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		hexagon_clean_dcache_range((unsigned long) addr,
-		(unsigned long) addr + size);
-		break;
-	case DMA_FROM_DEVICE:
-		hexagon_inv_dcache_range((unsigned long) addr,
-		(unsigned long) addr + size);
-		break;
-	case DMA_BIDIRECTIONAL:
-		flush_dcache_range((unsigned long) addr,
-		(unsigned long) addr + size);
-		break;
-	default:
-		BUG();
-	}
+	hexagon_clean_dcache_range(paddr, paddr + size);
 }
 
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	hexagon_inv_dcache_range(paddr, paddr + size);
+}
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	flush_dcache_range(paddr, paddr + size);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return false;
+}
+
+#include <linux/dma-sync.h>
+
 /*
  * Our max_low_pfn should have been backed off by 16MB in mm/init.c to create
  * DMA coherent space.  Use that for the pool.
diff --git a/arch/m68k/kernel/dma.c b/arch/m68k/kernel/dma.c
index 2e192a5df949..aa9b434e6df8 100644
--- a/arch/m68k/kernel/dma.c
+++ b/arch/m68k/kernel/dma.c
@@ -58,20 +58,33 @@ void arch_dma_free(struct device *dev, size_t size, void *vaddr,
 
 #endif /* CONFIG_MMU && !CONFIG_COLDFIRE */
 
-void arch_sync_dma_for_device(phys_addr_t handle, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	switch (dir) {
-	case DMA_BIDIRECTIONAL:
-	case DMA_TO_DEVICE:
-		cache_push(handle, size);
-		break;
-	case DMA_FROM_DEVICE:
-		cache_clear(handle, size);
-		break;
-	default:
-		pr_err_ratelimited("dma_sync_single_for_device: unsupported dir %u\n",
-				   dir);
-		break;
-	}
+	/*
+	 * cache_push() always invalidates in addition to cleaning
+	 * write-back caches.
+	 */
+	cache_push(paddr, size);
+}
+
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	cache_clear(paddr, size);
+}
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	cache_push(paddr, size);
 }
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return false;
+}
+
+#include <linux/dma-sync.h>
diff --git a/arch/microblaze/kernel/dma.c b/arch/microblaze/kernel/dma.c
index b4c4e45fd45e..01110d4aa5b0 100644
--- a/arch/microblaze/kernel/dma.c
+++ b/arch/microblaze/kernel/dma.c
@@ -14,32 +14,30 @@
 #include <linux/bug.h>
 #include <asm/cacheflush.h>
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	switch (direction) {
-	case DMA_TO_DEVICE:
-	case DMA_BIDIRECTIONAL:
-		flush_dcache_range(paddr, paddr + size);
-		break;
-	case DMA_FROM_DEVICE:
-		invalidate_dcache_range(paddr, paddr + size);
-		break;
-	default:
-		BUG();
-	}
+	/* writeback plus invalidate, could be a nop on WT caches */
+	flush_dcache_range(paddr, paddr + size);
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
-	switch (direction) {
-	case DMA_TO_DEVICE:
-		break;
-	case DMA_BIDIRECTIONAL:
-	case DMA_FROM_DEVICE:
-		invalidate_dcache_range(paddr, paddr + size);
-		break;
-	default:
-		BUG();
-	}}
+	invalidate_dcache_range(paddr, paddr + size);
+}
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	flush_dcache_range(paddr, paddr + size);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return true;
+}
+
+#include <linux/dma-sync.h>
diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index b9d68bcc5d53..902d4b7c1f85 100644
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -85,50 +85,38 @@ static inline void dma_sync_phys(phys_addr_t paddr, size_t size,
 	} while (left);
 }
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		dma_sync_phys(paddr, size, _dma_cache_wback);
-		break;
-	case DMA_FROM_DEVICE:
-		dma_sync_phys(paddr, size, _dma_cache_inv);
-		break;
-	case DMA_BIDIRECTIONAL:
-		if (IS_ENABLED(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) &&
-		    cpu_needs_post_dma_flush())
-			dma_sync_phys(paddr, size, _dma_cache_wback);
-		else
-			dma_sync_phys(paddr, size, _dma_cache_wback_inv);
-		break;
-	default:
-		break;
-	}
+	dma_sync_phys(paddr, size, _dma_cache_wback);
 }
 
-#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		break;
-	case DMA_FROM_DEVICE:
-	case DMA_BIDIRECTIONAL:
-		if (cpu_needs_post_dma_flush())
-			dma_sync_phys(paddr, size, _dma_cache_inv);
-		break;
-	default:
-		break;
-	}
+	dma_sync_phys(paddr, size, _dma_cache_inv);
 }
-#endif
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	dma_sync_phys(paddr, size, _dma_cache_wback_inv);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return IS_ENABLED(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) &&
+                    cpu_needs_post_dma_flush();
+}
+
+#include <linux/dma-sync.h>
 
 #ifdef CONFIG_ARCH_HAS_SETUP_DMA_OPS
 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
-		const struct iommu_ops *iommu, bool coherent)
+               const struct iommu_ops *iommu, bool coherent)
 {
-	dev->dma_coherent = coherent;
+       dev->dma_coherent = coherent;
 }
 #endif
diff --git a/arch/nios2/mm/dma-mapping.c b/arch/nios2/mm/dma-mapping.c
index fd887d5f3f9a..29978970955e 100644
--- a/arch/nios2/mm/dma-mapping.c
+++ b/arch/nios2/mm/dma-mapping.c
@@ -13,53 +13,46 @@
 #include <linux/types.h>
 #include <linux/mm.h>
 #include <linux/string.h>
+#include <linux/dma-map-ops.h>
 #include <linux/dma-mapping.h>
 #include <linux/io.h>
 #include <linux/cache.h>
 #include <asm/cacheflush.h>
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
+	/*
+	 * We just need to write back the caches here, but Nios2 flush
+	 * instruction will do both writeback and invalidate.
+	 */
 	void *vaddr = phys_to_virt(paddr);
+	flush_dcache_range((unsigned long)vaddr, (unsigned long)(vaddr + size));
+}
 
-	switch (dir) {
-	case DMA_FROM_DEVICE:
-		invalidate_dcache_range((unsigned long)vaddr,
-			(unsigned long)(vaddr + size));
-		break;
-	case DMA_TO_DEVICE:
-		/*
-		 * We just need to flush the caches here , but Nios2 flush
-		 * instruction will do both writeback and invalidate.
-		 */
-	case DMA_BIDIRECTIONAL: /* flush and invalidate */
-		flush_dcache_range((unsigned long)vaddr,
-			(unsigned long)(vaddr + size));
-		break;
-	default:
-		BUG();
-	}
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	unsigned long vaddr = (unsigned long)phys_to_virt(paddr);
+	invalidate_dcache_range(vaddr, (unsigned long)(vaddr + size));
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
 {
 	void *vaddr = phys_to_virt(paddr);
+	flush_dcache_range((unsigned long)vaddr, (unsigned long)(vaddr + size));
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
 
-	switch (dir) {
-	case DMA_BIDIRECTIONAL:
-	case DMA_FROM_DEVICE:
-		invalidate_dcache_range((unsigned long)vaddr,
-			(unsigned long)(vaddr + size));
-		break;
-	case DMA_TO_DEVICE:
-		break;
-	default:
-		BUG();
-	}
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return true;
 }
 
+#include <linux/dma-sync.h>
+
 void arch_dma_prep_coherent(struct page *page, size_t size)
 {
 	unsigned long start = (unsigned long)page_address(page);
diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
index 91a00d09ffad..aba2258e62eb 100644
--- a/arch/openrisc/kernel/dma.c
+++ b/arch/openrisc/kernel/dma.c
@@ -95,32 +95,47 @@ void arch_dma_clear_uncached(void *cpu_addr, size_t size)
 	mmap_write_unlock(&init_mm);
 }
 
-void arch_sync_dma_for_device(phys_addr_t addr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
 	unsigned long cl;
 	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
 
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		/* Write back the dcache for the requested range */
-		for (cl = addr; cl < addr + size;
-		     cl += cpuinfo->dcache_block_size)
-			mtspr(SPR_DCBWR, cl);
-		break;
-	case DMA_FROM_DEVICE:
-		/* Invalidate the dcache for the requested range */
-		for (cl = addr; cl < addr + size;
-		     cl += cpuinfo->dcache_block_size)
-			mtspr(SPR_DCBIR, cl);
-		break;
-	case DMA_BIDIRECTIONAL:
-		/* Flush the dcache for the requested range */
-		for (cl = addr; cl < addr + size;
-		     cl += cpuinfo->dcache_block_size)
-			mtspr(SPR_DCBFR, cl);
-		break;
-	default:
-		break;
-	}
+	/* Write back the dcache for the requested range */
+	for (cl = paddr; cl < paddr + size;
+	     cl += cpuinfo->dcache_block_size)
+		mtspr(SPR_DCBWR, cl);
 }
+
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	unsigned long cl;
+	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
+
+	/* Invalidate the dcache for the requested range */
+	for (cl = paddr; cl < paddr + size;
+	     cl += cpuinfo->dcache_block_size)
+		mtspr(SPR_DCBIR, cl);
+}
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	unsigned long cl;
+	struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
+
+	/* Flush the dcache for the requested range */
+	for (cl = paddr; cl < paddr + size;
+	     cl += cpuinfo->dcache_block_size)
+		mtspr(SPR_DCBFR, cl);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return false;
+}
+
+#include <linux/dma-sync.h>
diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h
index c8b6928cee1e..a0fc71f8789c 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++ b/arch/parisc/include/asm/cacheflush.h
@@ -35,6 +35,8 @@ void flush_kernel_dcache_page_addr(const void *addr);
 
 #define flush_kernel_dcache_range(start,size) \
 	flush_kernel_dcache_range_asm((start), (start)+(size));
+#define purge_kernel_dcache_range(start,size) \
+	purge_kernel_dcache_range_asm((start), (start)+(size));
 
 #define ARCH_IMPLEMENTS_FLUSH_KERNEL_VMAP_RANGE 1
 void flush_kernel_vmap_range(void *vaddr, int size);
diff --git a/arch/parisc/kernel/pci-dma.c b/arch/parisc/kernel/pci-dma.c
index d818ece23b4a..cc029d6775e1 100644
--- a/arch/parisc/kernel/pci-dma.c
+++ b/arch/parisc/kernel/pci-dma.c
@@ -443,8 +443,7 @@ void arch_dma_free(struct device *dev, size_t size, void *vaddr,
 	free_pages((unsigned long)__va(dma_handle), order);
 }
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
 	/*
 	 * fdc: The data cache line is written back to memory, if and only if
@@ -453,20 +452,28 @@ void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
 	flush_kernel_dcache_range((unsigned long)phys_to_virt(paddr), size);
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
-	unsigned long addr = (unsigned long) phys_to_virt(paddr);
+	unsigned long virt = (unsigned long)phys_to_virt(paddr);
 
-	switch (dir) {
-	case DMA_TO_DEVICE:
-	case DMA_BIDIRECTIONAL:
-		flush_kernel_dcache_range(addr, size);
-		return;
-	case DMA_FROM_DEVICE:
-		purge_kernel_dcache_range_asm(addr, addr + size);
-		return;
-	default:
-		BUG();
-	}
+	purge_kernel_dcache_range(virt, size);
+}
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	unsigned long virt = (unsigned long)phys_to_virt(paddr);
+
+	flush_kernel_dcache_range(virt, size);
 }
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return true;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return true;
+}
+
+#include <linux/dma-sync.h>
diff --git a/arch/powerpc/mm/dma-noncoherent.c b/arch/powerpc/mm/dma-noncoherent.c
index 00e59a4faa2b..668d8ec58f1c 100644
--- a/arch/powerpc/mm/dma-noncoherent.c
+++ b/arch/powerpc/mm/dma-noncoherent.c
@@ -101,27 +101,33 @@ static void __dma_phys_op(phys_addr_t paddr, size_t size, enum dma_cache_op op)
 #endif
 }
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	__dma_phys_op(start, end, DMA_CACHE_CLEAN);
+	__dma_phys_op(paddr, size, DMA_CACHE_CLEAN);
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
-	switch (direction) {
-	case DMA_NONE:
-		BUG();
-	case DMA_TO_DEVICE:
-		break;
-	case DMA_FROM_DEVICE:
-	case DMA_BIDIRECTIONAL:
-		__dma_phys_op(start, end, DMA_CACHE_INVAL);
-		break;
-	}
+	__dma_phys_op(paddr, size, DMA_CACHE_INVAL);
 }
 
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	__dma_phys_op(paddr, size, DMA_CACHE_FLUSH);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return true;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return true;
+}
+
+#include <linux/dma-sync.h>
+
 void arch_dma_prep_coherent(struct page *page, size_t size)
 {
 	unsigned long kaddr = (unsigned long)page_address(page);
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index fc6377a64c8d..a72f152b7dbe 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -12,43 +12,40 @@
 
 static bool noncoherent_supported __ro_after_init;
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-			      enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
 	void *vaddr = phys_to_virt(paddr);
 
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
-		break;
-	case DMA_FROM_DEVICE:
-		ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
-		break;
-	case DMA_BIDIRECTIONAL:
-		ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
-		break;
-	default:
-		break;
-	}
+	ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
 }
 
-void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
-			   enum dma_data_direction dir)
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
 	void *vaddr = phys_to_virt(paddr);
 
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		break;
-	case DMA_FROM_DEVICE:
-	case DMA_BIDIRECTIONAL:
-		ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
-		break;
-	default:
-		break;
-	}
+	ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
 }
 
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	void *vaddr = phys_to_virt(paddr);
+
+	ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return true;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return true;
+}
+
+#include <linux/dma-sync.h>
+
+
 void arch_dma_prep_coherent(struct page *page, size_t size)
 {
 	void *flush_addr = page_address(page);
diff --git a/arch/sh/kernel/dma-coherent.c b/arch/sh/kernel/dma-coherent.c
index 6a44c0e7ba40..41f031ae7609 100644
--- a/arch/sh/kernel/dma-coherent.c
+++ b/arch/sh/kernel/dma-coherent.c
@@ -12,22 +12,35 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
 	__flush_purge_region(page_address(page), size);
 }
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
 	void *addr = sh_cacheop_vaddr(phys_to_virt(paddr));
 
-	switch (dir) {
-	case DMA_FROM_DEVICE:		/* invalidate only */
-		__flush_invalidate_region(addr, size);
-		break;
-	case DMA_TO_DEVICE:		/* writeback only */
-		__flush_wback_region(addr, size);
-		break;
-	case DMA_BIDIRECTIONAL:		/* writeback and invalidate */
-		__flush_purge_region(addr, size);
-		break;
-	default:
-		BUG();
-	}
+	__flush_wback_region(addr, size);
 }
+
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	void *addr = sh_cacheop_vaddr(phys_to_virt(paddr));
+
+	__flush_invalidate_region(addr, size);
+}
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	void *addr = sh_cacheop_vaddr(phys_to_virt(paddr));
+
+	__flush_purge_region(addr, size);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return false;
+}
+
+#include <linux/dma-sync.h>
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 9c20cd833d3c..725b9a5a1d01 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -300,21 +300,39 @@ arch_initcall(sparc_register_ioport);
 
 #endif /* CONFIG_SBUS */
 
-/*
- * IIep is write-through, not flushing on cpu to device transfer.
- *
- * On LEON systems without cache snooping, the entire D-CACHE must be flushed to
- * make DMA to cacheable memory coherent.
- */
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	if (dir != DMA_TO_DEVICE &&
-	    sparc_cpu_model == sparc_leon &&
+	/* IIep is write-through, not flushing on cpu to device transfer. */
+}
+
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	/*
+	 * On LEON systems without cache snooping, the entire D-CACHE must be
+	 * flushed to make DMA to cacheable memory coherent.
+	 */
+	if (sparc_cpu_model == sparc_leon &&
 	    !sparc_leon3_snooping_enabled())
 		leon_flush_dcache_all();
 }
 
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	arch_dma_cache_inv(paddr, size);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return true;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return false;
+}
+
+#include <linux/dma-sync.h>
+
 #ifdef CONFIG_PROC_FS
 
 static int sparc_io_proc_show(struct seq_file *m, void *v)
diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c
index ff3bf015eca4..d4ff96585545 100644
--- a/arch/xtensa/kernel/pci-dma.c
+++ b/arch/xtensa/kernel/pci-dma.c
@@ -43,24 +43,34 @@ static void do_cache_op(phys_addr_t paddr, size_t size,
 		}
 }
 
-void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
-		enum dma_data_direction dir)
+static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
-	switch (dir) {
-	case DMA_TO_DEVICE:
-		do_cache_op(paddr, size, __flush_dcache_range);
-		break;
-	case DMA_FROM_DEVICE:
-		do_cache_op(paddr, size, __invalidate_dcache_range);
-		break;
-	case DMA_BIDIRECTIONAL:
-		do_cache_op(paddr, size, __flush_invalidate_dcache_range);
-		break;
-	default:
-		break;
-	}
+	do_cache_op(paddr, size, __flush_dcache_range);
 }
 
+static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
+{
+	do_cache_op(paddr, size, __invalidate_dcache_range);
+}
+
+static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
+{
+	do_cache_op(paddr, size, __flush_invalidate_dcache_range);
+}
+
+static inline bool arch_sync_dma_clean_before_fromdevice(void)
+{
+	return false;
+}
+
+static inline bool arch_sync_dma_cpu_needs_post_dma_flush(void)
+{
+	return false;
+}
+
+#include <linux/dma-sync.h>
+
+
 void arch_dma_prep_coherent(struct page *page, size_t size)
 {
 	__invalidate_dcache_range((unsigned long)page_address(page), size);
diff --git a/include/linux/dma-sync.h b/include/linux/dma-sync.h
new file mode 100644
index 000000000000..18e33d5e8eaf
--- /dev/null
+++ b/include/linux/dma-sync.h
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cache operations depending on function and direction argument, inspired by
+ * https://lore.kernel.org/lkml/20180518175004.GF17671@n2100.armlinux.org.uk
+ * "dma_sync_*_for_cpu and direction=TO_DEVICE (was Re: [PATCH 02/20]
+ * dma-mapping: provide a generic dma-noncoherent implementation)"
+ *
+ *          |   map          ==  for_device     |   unmap     ==  for_cpu
+ *          |----------------------------------------------------------------
+ * TO_DEV   |   writeback        writeback      |   none          none
+ * FROM_DEV |   invalidate       invalidate     |   invalidate*   invalidate*
+ * BIDIR    |   writeback        writeback      |   invalidate    invalidate
+ *
+ *     [*] needed for CPU speculative prefetches
+ *
+ * NOTE: we don't check the validity of direction argument as it is done in
+ * upper layer functions (in include/linux/dma-mapping.h)
+ *
+ * This file can be included by arch/.../kernel/dma-noncoherent.c to provide
+ * the respective high-level operations without having to expose the
+ * cache management ops to drivers.
+ */
+
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
+		enum dma_data_direction dir)
+{
+	switch (dir) {
+	case DMA_TO_DEVICE:
+		/*
+		 * This may be an empty function on write-through caches,
+		 * and it might invalidate the cache if an architecture has
+		 * a write-back cache but no way to write it back without
+		 * invalidating
+		 */
+		arch_dma_cache_wback(paddr, size);
+		break;
+
+	case DMA_FROM_DEVICE:
+		/*
+		 * FIXME: this should be handled the same across all
+		 * architectures, see
+		 * https://lore.kernel.org/all/20220606152150.GA31568@willie-the-truck/
+		 */
+		if (!arch_sync_dma_clean_before_fromdevice()) {
+			arch_dma_cache_inv(paddr, size);
+			break;
+		}
+		fallthrough;
+
+	case DMA_BIDIRECTIONAL:
+		/* Skip the invalidate here if it's done later */
+		if (IS_ENABLED(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) &&
+		    arch_sync_dma_cpu_needs_post_dma_flush())
+			arch_dma_cache_wback(paddr, size);
+		else
+			arch_dma_cache_wback_inv(paddr, size);
+		break;
+
+	default:
+		break;
+	}
+}
+
+#ifdef CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU
+/*
+ * Mark the D-cache clean for these pages to avoid extra flushing.
+ */
+static void arch_dma_mark_dcache_clean(phys_addr_t paddr, size_t size)
+{
+#ifdef CONFIG_ARCH_DMA_MARK_DCACHE_CLEAN
+	unsigned long pfn = PFN_UP(paddr);
+	unsigned long off = paddr & (PAGE_SIZE - 1);
+	size_t left = size;
+
+	if (off)
+		left -= PAGE_SIZE - off;
+
+	while (left >= PAGE_SIZE) {
+		struct page *page = pfn_to_page(pfn++);
+		set_bit(PG_dcache_clean, &page->flags);
+		left -= PAGE_SIZE;
+	}
+#endif
+}
+
+void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
+		enum dma_data_direction dir)
+{
+	switch (dir) {
+	case DMA_TO_DEVICE:
+		break;
+
+	case DMA_FROM_DEVICE:
+	case DMA_BIDIRECTIONAL:
+		/* FROM_DEVICE invalidate needed if speculative CPU prefetch only */
+		if (arch_sync_dma_cpu_needs_post_dma_flush())
+			arch_dma_cache_inv(paddr, size);
+
+		if (size > PAGE_SIZE)
+			arch_dma_mark_dcache_clean(paddr, size);
+		break;
+
+	default:
+		break;
+	}
+}
+#endif
-- 
2.41.0


From 8359e2ef7abcf144edb82acc2d24c19f29753586 Mon Sep 17 00:00:00 2001
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 2 Jul 2023 21:34:24 +0100
Subject: [PATCH 23/72] riscv: asm: vendorid_list: Add Andes Technology to the
 vendors list

Add Andes Technology to the vendors list.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230702203429.237615-2-prabhakar.mahadev-lad.rj@bp.renesas.com
---
 arch/riscv/include/asm/vendorid_list.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index cb89af3f0704..e55407ace0c3 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -5,6 +5,7 @@
 #ifndef ASM_VENDOR_LIST_H
 #define ASM_VENDOR_LIST_H
 
+#define ANDESTECH_VENDOR_ID	0x31e
 #define SIFIVE_VENDOR_ID	0x489
 #define THEAD_VENDOR_ID		0x5b7
 
-- 
2.41.0


From bc49d25b2175ba61193f5e2a2bd37a43f157e480 Mon Sep 17 00:00:00 2001
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 2 Jul 2023 21:34:25 +0100
Subject: [PATCH 24/72] riscv: errata: Add Andes alternative ports

Add required ports of the Alternative scheme for Andes CPU cores.

I/O Coherence Port (IOCP) provides an AXI interface for connecting external
non-caching masters, such as DMA controllers. IOCP is a specification
option and is disabled on the Renesas RZ/Five SoC due to this reason cache
management needs a software workaround.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230702203429.237615-3-prabhakar.mahadev-lad.rj@bp.renesas.com
---
 arch/riscv/Kconfig.errata            | 21 +++++++++
 arch/riscv/errata/Makefile           |  1 +
 arch/riscv/errata/andes/Makefile     |  1 +
 arch/riscv/errata/andes/errata.c     | 66 ++++++++++++++++++++++++++++
 arch/riscv/include/asm/alternative.h |  3 ++
 arch/riscv/include/asm/errata_list.h |  5 +++
 arch/riscv/kernel/alternative.c      |  5 +++
 7 files changed, 102 insertions(+)
 create mode 100644 arch/riscv/errata/andes/Makefile
 create mode 100644 arch/riscv/errata/andes/errata.c

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 0c8f4652cd82..92c779764b27 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -1,5 +1,26 @@
 menu "CPU errata selection"
 
+config ERRATA_ANDES
+	bool "Andes AX45MP errata"
+	depends on RISCV_ALTERNATIVE
+	help
+	  All Andes errata Kconfig depend on this Kconfig. Disabling
+	  this Kconfig will disable all Andes errata. Please say "Y"
+	  here if your platform uses Andes CPU cores.
+
+	  Otherwise, please say "N" here to avoid unnecessary overhead.
+
+config ERRATA_ANDES_CMO
+	bool "Apply Andes cache management errata"
+	depends on ERRATA_ANDES && MMU && ARCH_R9A07G043
+	select RISCV_DMA_NONCOHERENT
+	default y
+	help
+	  This will apply the cache management errata to handle the
+	  non-standard handling on non-coherent operations on Andes cores.
+
+	  If you don't know what to do here, say "Y".
+
 config ERRATA_SIFIVE
 	bool "SiFive errata"
 	depends on RISCV_ALTERNATIVE
diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
index 7b2637c8c332..8a2739485123 100644
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
@@ -2,5 +2,6 @@ ifdef CONFIG_RELOCATABLE
 KBUILD_CFLAGS += -fno-pie
 endif
 
+obj-$(CONFIG_ERRATA_ANDES) += andes/
 obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
 obj-$(CONFIG_ERRATA_THEAD) += thead/
diff --git a/arch/riscv/errata/andes/Makefile b/arch/riscv/errata/andes/Makefile
new file mode 100644
index 000000000000..2d644e19caef
--- /dev/null
+++ b/arch/riscv/errata/andes/Makefile
@@ -0,0 +1 @@
+obj-y += errata.o
diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
new file mode 100644
index 000000000000..197db68cc8da
--- /dev/null
+++ b/arch/riscv/errata/andes/errata.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Erratas to be applied for Andes CPU cores
+ *
+ *  Copyright (C) 2023 Renesas Electronics Corporation.
+ *
+ * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+ */
+
+#include <linux/memory.h>
+#include <linux/module.h>
+
+#include <asm/alternative.h>
+#include <asm/cacheflush.h>
+#include <asm/errata_list.h>
+#include <asm/patch.h>
+#include <asm/processor.h>
+#include <asm/sbi.h>
+#include <asm/vendorid_list.h>
+
+#define ANDESTECH_AX45MP_MARCHID	0x8000000000008a45UL
+#define ANDESTECH_AX45MP_MIMPID		0x500UL
+#define ANDESTECH_SBI_EXT_ANDES		0x0900031E
+
+#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND	1
+
+static long ax45mp_iocp_sw_workaround(void)
+{
+	struct sbiret ret;
+
+	/*
+	 * ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
+	 * cache is controllable only then CMO will be applied to the platform.
+	 */
+	ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
+			0, 0, 0, 0, 0, 0);
+
+	return ret.error ? 0 : ret.value;
+}
+
+static bool errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid)
+{
+	if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO))
+		return false;
+
+	if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)
+		return false;
+
+	if (!ax45mp_iocp_sw_workaround())
+		return false;
+
+	/* Set this just to make core cbo code happy */
+	riscv_cbom_block_size = 1;
+	riscv_noncoherent_supported();
+
+	return true;
+}
+
+void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+					      unsigned long archid, unsigned long impid,
+					      unsigned int stage)
+{
+	errata_probe_iocp(stage, archid, impid);
+
+	/* we have nothing to patch here ATM so just return back */
+}
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index 6a41537826a7..f6cfca939c92 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -46,6 +46,9 @@ struct alt_entry {
 	u32 patch_id;		/* The patch ID (erratum ID or cpufeature ID) */
 };
 
+void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+			     unsigned long archid, unsigned long impid,
+			     unsigned int stage);
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			      unsigned long archid, unsigned long impid,
 			      unsigned int stage);
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index fb1a810f3d8c..e2ecd01bfac7 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -11,6 +11,11 @@
 #include <asm/hwcap.h>
 #include <asm/vendorid_list.h>
 
+#ifdef CONFIG_ERRATA_ANDES
+#define ERRATA_ANDESTECH_NO_IOCP	0
+#define ERRATA_ANDESTECH_NUMBER		1
+#endif
+
 #ifdef CONFIG_ERRATA_SIFIVE
 #define	ERRATA_SIFIVE_CIP_453 0
 #define	ERRATA_SIFIVE_CIP_1200 1
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 6b75788c18e6..b0345992a35e 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -45,6 +45,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
 
 	cpu_mfr_info->feature_probe_func = NULL;
 	switch (cpu_mfr_info->vendor_id) {
+#ifdef CONFIG_ERRATA_ANDES
+	case ANDESTECH_VENDOR_ID:
+		cpu_mfr_info->patch_func = andes_errata_patch_func;
+		break;
+#endif
 #ifdef CONFIG_ERRATA_SIFIVE
 	case SIFIVE_VENDOR_ID:
 		cpu_mfr_info->patch_func = sifive_errata_patch_func;
-- 
2.41.0


From 4e567219d4cdfec4344b0489aaecc17f30824405 Mon Sep 17 00:00:00 2001
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 2 Jul 2023 21:34:26 +0100
Subject: [PATCH 25/72] riscv: mm: dma-noncoherent: nonstandard cache
 operations support

Introduce support for nonstandard noncoherent systems in the RISC-V
architecture. It enables function pointer support to handle cache
management in such systems.

This patch adds a new configuration option called
"RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that
depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer
support for cache management in nonstandard noncoherent systems.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230702203429.237615-4-prabhakar.mahadev-lad.rj@bp.renesas.com
---
 arch/riscv/Kconfig                       |  7 ++++
 arch/riscv/include/asm/dma-noncoherent.h | 28 +++++++++++++++
 arch/riscv/mm/dma-noncoherent.c          | 43 ++++++++++++++++++++++++
 arch/riscv/mm/pmem.c                     | 13 +++++++
 4 files changed, 91 insertions(+)
 create mode 100644 arch/riscv/include/asm/dma-noncoherent.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4c07b9189c86..3c2087974ce0 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -269,6 +269,13 @@ config RISCV_DMA_NONCOHERENT
 	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
 	select DMA_DIRECT_REMAP
 
+config RISCV_NONSTANDARD_CACHE_OPS
+	bool
+	depends on RISCV_DMA_NONCOHERENT
+	help
+	  This enables function pointer support for non-standard noncoherent
+	  systems to handle cache management.
+
 config AS_HAS_INSN
 	def_bool $(as-instr,.insn r 51$(comma) 0$(comma) 0$(comma) t0$(comma) t0$(comma) zero)
 
diff --git a/arch/riscv/include/asm/dma-noncoherent.h b/arch/riscv/include/asm/dma-noncoherent.h
new file mode 100644
index 000000000000..969cf1f1363a
--- /dev/null
+++ b/arch/riscv/include/asm/dma-noncoherent.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#ifndef __ASM_DMA_NONCOHERENT_H
+#define __ASM_DMA_NONCOHERENT_H
+
+#include <linux/dma-direct.h>
+
+/*
+ * struct riscv_cache_ops - Structure for CMO function pointers
+ *
+ * @wback: Function pointer for cache writeback
+ * @inv: Function pointer for invalidating cache
+ * @wback_inv: Function pointer for flushing the cache (writeback + invalidating)
+ */
+struct riscv_cache_ops {
+	void (*wback)(phys_addr_t paddr, unsigned long size);
+	void (*inv)(phys_addr_t paddr, unsigned long size);
+	void (*wback_inv)(phys_addr_t paddr, unsigned long size);
+};
+
+extern struct riscv_cache_ops noncoherent_cache_ops;
+
+void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops);
+
+#endif	/* __ASM_DMA_NONCOHERENT_H */
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index a72f152b7dbe..85eb58344a1e 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -9,13 +9,26 @@
 #include <linux/dma-map-ops.h>
 #include <linux/mm.h>
 #include <asm/cacheflush.h>
+#include <asm/dma-noncoherent.h>
 
 static bool noncoherent_supported __ro_after_init;
 
+struct riscv_cache_ops noncoherent_cache_ops __ro_after_init = {
+	.wback = NULL,
+	.inv = NULL,
+	.wback_inv = NULL,
+};
+
 static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size)
 {
 	void *vaddr = phys_to_virt(paddr);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+	if (unlikely(noncoherent_cache_ops.wback)) {
+		noncoherent_cache_ops.wback(paddr, size);
+		return;
+	}
+#endif
 	ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
 }
 
@@ -23,6 +36,13 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size)
 {
 	void *vaddr = phys_to_virt(paddr);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+	if (unlikely(noncoherent_cache_ops.inv)) {
+		noncoherent_cache_ops.inv(paddr, size);
+		return;
+	}
+#endif
+
 	ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
 }
 
@@ -30,6 +50,13 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size)
 {
 	void *vaddr = phys_to_virt(paddr);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+	if (unlikely(noncoherent_cache_ops.wback_inv)) {
+		noncoherent_cache_ops.wback_inv(paddr, size);
+		return;
+	}
+#endif
+
 	ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size);
 }
 
@@ -50,6 +77,13 @@ void arch_dma_prep_coherent(struct page *page, size_t size)
 {
 	void *flush_addr = page_address(page);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+	if (unlikely(noncoherent_cache_ops.wback_inv)) {
+		noncoherent_cache_ops.wback_inv(page_to_phys(page), size);
+		return;
+	}
+#endif
+
 	ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size);
 }
 
@@ -75,3 +109,12 @@ void riscv_noncoherent_supported(void)
 	     "Non-coherent DMA support enabled without a block size\n");
 	noncoherent_supported = true;
 }
+
+void riscv_noncoherent_register_cache_ops(const struct riscv_cache_ops *ops)
+{
+	if (!ops)
+		return;
+
+	noncoherent_cache_ops = *ops;
+}
+EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops);
diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c
index 089df92ae876..c5fc5ec96f6d 100644
--- a/arch/riscv/mm/pmem.c
+++ b/arch/riscv/mm/pmem.c
@@ -7,15 +7,28 @@
 #include <linux/libnvdimm.h>
 
 #include <asm/cacheflush.h>
+#include <asm/dma-noncoherent.h>
 
 void arch_wb_cache_pmem(void *addr, size_t size)
 {
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+	if (unlikely(noncoherent_cache_ops.wback)) {
+		noncoherent_cache_ops.wback(virt_to_phys(addr), size);
+		return;
+	}
+#endif
 	ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size);
 }
 EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);
 
 void arch_invalidate_pmem(void *addr, size_t size)
 {
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+	if (unlikely(noncoherent_cache_ops.inv)) {
+		noncoherent_cache_ops.inv(virt_to_phys(addr), size);
+		return;
+	}
+#endif
 	ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size);
 }
 EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
-- 
2.41.0


From 78cecd49513e06b5c47daaa817a7bbf48bd377fa Mon Sep 17 00:00:00 2001
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 2 Jul 2023 21:34:27 +0100
Subject: [PATCH 26/72] dt-bindings: cache: andestech,ax45mp-cache: Add DT
 binding documentation for L2 cache controller

Add DT binding documentation for L2 cache controller found on RZ/Five SoC.

The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. The AX45MP core has an L2 cache controller, this patch
describes the L2 cache block.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230702203429.237615-5-prabhakar.mahadev-lad.rj@bp.renesas.com
---
 .../cache/andestech,ax45mp-cache.yaml         | 81 +++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
new file mode 100644
index 000000000000..9ab5f0c435d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2023 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Andestech AX45MP L2 Cache Controller
+
+maintainers:
+  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+description:
+  A level-2 cache (L2C) is used to improve the system performance by providing
+  a large amount of cache line entries and reasonable access delays. The L2C
+  is shared between cores, and a non-inclusive non-exclusive policy is used.
+
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - andestech,ax45mp-cache
+
+  required:
+    - compatible
+
+properties:
+  compatible:
+    items:
+      - const: andestech,ax45mp-cache
+      - const: cache
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  cache-line-size:
+    const: 64
+
+  cache-level:
+    const: 2
+
+  cache-sets:
+    const: 1024
+
+  cache-size:
+    enum: [131072, 262144, 524288, 1048576, 2097152]
+
+  cache-unified: true
+
+  next-level-cache: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - cache-line-size
+  - cache-level
+  - cache-sets
+  - cache-size
+  - cache-unified
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    cache-controller@2010000 {
+        compatible = "andestech,ax45mp-cache", "cache";
+        reg = <0x13400000 0x100000>;
+        interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
+        cache-line-size = <64>;
+        cache-level = <2>;
+        cache-sets = <1024>;
+        cache-size = <262144>;
+        cache-unified;
+    };
-- 
2.41.0


From 747e6de2bc73bbe481a9cfe99b20f49033b9345a Mon Sep 17 00:00:00 2001
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 2 Jul 2023 21:34:28 +0100
Subject: [PATCH 27/72] cache: Add L2 cache management for Andes AX45MP RISC-V
 core

I/O Coherence Port (IOCP) provides an AXI interface for connecting
external non-caching masters, such as DMA controllers. The accesses
from IOCP are coherent with D-Caches and L2 Cache.

IOCP is a specification option and is disabled on the Renesas RZ/Five
SoC due to this reason IP blocks using DMA will fail.

The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
block that allows dynamic adjustment of memory attributes in the runtime.
It contains a configurable amount of PMA entries implemented as CSR
registers to control the attributes of memory locations in interest.
Below are the memory attributes supported:
* Device, Non-bufferable
* Device, bufferable
* Memory, Non-cacheable, Non-bufferable
* Memory, Non-cacheable, Bufferable
* Memory, Write-back, No-allocate
* Memory, Write-back, Read-allocate
* Memory, Write-back, Write-allocate
* Memory, Write-back, Read and Write-allocate

More info about PMA (section 10.3):
Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf

As a workaround for SoCs with IOCP disabled CMO needs to be handled by
software. Firstly OpenSBI configures the memory region as
"Memory, Non-cacheable, Bufferable" and passes this region as a global
shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
allocations happen from this region and synchronization callbacks are
implemented to synchronize when doing DMA transactions.

Example PMA region passes as a DT node from OpenSBI:
    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;

        pma_resv0@58000000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0x58000000 0x0 0x08000000>;
            no-map;
            linux,dma-default;
        };
    };

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230702203429.237615-6-prabhakar.mahadev-lad.rj@bp.renesas.com
---
 MAINTAINERS                  |   7 ++
 drivers/Kconfig              |   2 +
 drivers/Makefile             |   1 +
 drivers/cache/Kconfig        |  11 ++
 drivers/cache/Makefile       |   3 +
 drivers/cache/ax45mp_cache.c | 213 +++++++++++++++++++++++++++++++++++
 6 files changed, 237 insertions(+)
 create mode 100644 drivers/cache/Kconfig
 create mode 100644 drivers/cache/Makefile
 create mode 100644 drivers/cache/ax45mp_cache.c

diff --git a/MAINTAINERS b/MAINTAINERS
index d516295978a4..0a574b497a1b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20254,6 +20254,13 @@ S:	Supported
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
 F:	drivers/staging/
 
+STANDALONE CACHE CONTROLLER DRIVERS
+M:	Conor Dooley <conor@kernel.org>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
+F:	drivers/cache
+
 STARFIRE/DURALAN NETWORK DRIVER
 M:	Ion Badulescu <ionut@badula.org>
 S:	Odd Fixes
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 514ae6b24cb2..2ae1b6707c2c 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -15,6 +15,8 @@ source "drivers/base/Kconfig"
 
 source "drivers/bus/Kconfig"
 
+source "drivers/cache/Kconfig"
+
 source "drivers/connector/Kconfig"
 
 source "drivers/firmware/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 7241d80a7b29..23eb201fe18a 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -11,6 +11,7 @@ ifdef building_out_of_srctree
 MAKEFLAGS += --include-dir=$(srctree)
 endif
 
+obj-y				+= cache/
 obj-y				+= irqchip/
 obj-y				+= bus/
 
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
new file mode 100644
index 000000000000..a57677f908f3
--- /dev/null
+++ b/drivers/cache/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
+menu "Cache Drivers"
+
+config AX45MP_L2_CACHE
+	bool "Andes Technology AX45MP L2 Cache controller"
+	depends on RISCV_DMA_NONCOHERENT
+	select RISCV_NONSTANDARD_CACHE_OPS
+	help
+	  Support for the L2 cache controller on Andes Technology AX45MP platforms.
+
+endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
new file mode 100644
index 000000000000..2012e7fb978d
--- /dev/null
+++ b/drivers/cache/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
diff --git a/drivers/cache/ax45mp_cache.c b/drivers/cache/ax45mp_cache.c
new file mode 100644
index 000000000000..863bf0bfef98
--- /dev/null
+++ b/drivers/cache/ax45mp_cache.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * non-coherent cache functions for Andes AX45MP
+ *
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include <linux/cacheflush.h>
+#include <linux/cacheinfo.h>
+#include <linux/dma-direction.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+#include <asm/dma-noncoherent.h>
+
+/* L2 cache registers */
+#define AX45MP_L2C_REG_CTL_OFFSET		0x8
+
+#define AX45MP_L2C_REG_C0_CMD_OFFSET		0x40
+#define AX45MP_L2C_REG_C0_ACC_OFFSET		0x48
+#define AX45MP_L2C_REG_STATUS_OFFSET		0x80
+
+/* D-cache operation */
+#define AX45MP_CCTL_L1D_VA_INVAL		0 /* Invalidate an L1 cache entry */
+#define AX45MP_CCTL_L1D_VA_WB			1 /* Write-back an L1 cache entry */
+
+/* L2 CCTL status */
+#define AX45MP_CCTL_L2_STATUS_IDLE		0
+
+/* L2 CCTL status cores mask */
+#define AX45MP_CCTL_L2_STATUS_C0_MASK		0xf
+
+/* L2 cache operation */
+#define AX45MP_CCTL_L2_PA_INVAL			0x8 /* Invalidate an L2 cache entry */
+#define AX45MP_CCTL_L2_PA_WB			0x9 /* Write-back an L2 cache entry */
+
+#define AX45MP_L2C_REG_PER_CORE_OFFSET		0x10
+#define AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET	4
+
+#define AX45MP_L2C_REG_CN_CMD_OFFSET(n)	\
+	(AX45MP_L2C_REG_C0_CMD_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
+#define AX45MP_L2C_REG_CN_ACC_OFFSET(n)	\
+	(AX45MP_L2C_REG_C0_ACC_OFFSET + ((n) * AX45MP_L2C_REG_PER_CORE_OFFSET))
+#define AX45MP_CCTL_L2_STATUS_CN_MASK(n)	\
+	(AX45MP_CCTL_L2_STATUS_C0_MASK << ((n) * AX45MP_CCTL_L2_STATUS_PER_CORE_OFFSET))
+
+#define AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM	0x80b
+#define AX45MP_CCTL_REG_UCCTLCOMMAND_NUM	0x80c
+
+#define AX45MP_CACHE_LINE_SIZE			64
+
+struct ax45mp_priv {
+	void __iomem *l2c_base;
+	u32 ax45mp_cache_line_size;
+};
+
+static struct ax45mp_priv ax45mp_priv;
+
+/* L2 Cache operations */
+static inline uint32_t ax45mp_cpu_l2c_get_cctl_status(void)
+{
+	return readl(ax45mp_priv.l2c_base + AX45MP_L2C_REG_STATUS_OFFSET);
+}
+
+static void ax45mp_cpu_cache_operation(unsigned long start, unsigned long end,
+				       unsigned int l1_op, unsigned int l2_op)
+{
+	unsigned long line_size = ax45mp_priv.ax45mp_cache_line_size;
+	void __iomem *base = ax45mp_priv.l2c_base;
+	int mhartid = smp_processor_id();
+	unsigned long pa;
+
+	while (end > start) {
+		csr_write(AX45MP_CCTL_REG_UCCTLBEGINADDR_NUM, start);
+		csr_write(AX45MP_CCTL_REG_UCCTLCOMMAND_NUM, l1_op);
+
+		pa = virt_to_phys((void *)start);
+		writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid));
+		writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid));
+		while ((ax45mp_cpu_l2c_get_cctl_status() &
+			AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) !=
+			AX45MP_CCTL_L2_STATUS_IDLE)
+			;
+
+		start += line_size;
+	}
+}
+
+/* Write-back L1 and L2 cache entry */
+static inline void ax45mp_cpu_dcache_wb_range(unsigned long start, unsigned long end)
+{
+	ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_WB,
+				   AX45MP_CCTL_L2_PA_WB);
+}
+
+/* Invalidate the L1 and L2 cache entry */
+static inline void ax45mp_cpu_dcache_inval_range(unsigned long start, unsigned long end)
+{
+	ax45mp_cpu_cache_operation(start, end, AX45MP_CCTL_L1D_VA_INVAL,
+				   AX45MP_CCTL_L2_PA_INVAL);
+}
+
+static void ax45mp_dma_cache_inv(phys_addr_t paddr, unsigned long size)
+{
+	unsigned long start = (unsigned long)phys_to_virt(paddr);
+	unsigned long end = start + size;
+	unsigned long line_size;
+	unsigned long flags;
+
+	if (unlikely(start == end))
+		return;
+
+	line_size = ax45mp_priv.ax45mp_cache_line_size;
+
+	start = start & (~(line_size - 1));
+	end = ((end + line_size - 1) & (~(line_size - 1)));
+
+	local_irq_save(flags);
+
+	ax45mp_cpu_dcache_inval_range(start, end);
+
+	local_irq_restore(flags);
+}
+
+static void ax45mp_dma_cache_wback(phys_addr_t paddr, unsigned long size)
+{
+	unsigned long start = (unsigned long)phys_to_virt(paddr);
+	unsigned long end = start + size;
+	unsigned long line_size;
+	unsigned long flags;
+
+	line_size = ax45mp_priv.ax45mp_cache_line_size;
+	start = start & (~(line_size - 1));
+	local_irq_save(flags);
+	ax45mp_cpu_dcache_wb_range(start, end);
+	local_irq_restore(flags);
+}
+
+static void ax45mp_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
+{
+	ax45mp_dma_cache_wback(paddr, size);
+	ax45mp_dma_cache_inv(paddr, size);
+}
+
+static int ax45mp_get_l2_line_size(struct device_node *np)
+{
+	int ret;
+
+	ret = of_property_read_u32(np, "cache-line-size", &ax45mp_priv.ax45mp_cache_line_size);
+	if (ret) {
+		pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n");
+		return ret;
+	}
+
+	if (ax45mp_priv.ax45mp_cache_line_size != AX45MP_CACHE_LINE_SIZE) {
+		pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n",
+		       ax45mp_priv.ax45mp_cache_line_size);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct riscv_cache_ops ax45mp_cmo_ops = {
+	.wback = &ax45mp_dma_cache_wback,
+	.inv = &ax45mp_dma_cache_inv,
+	.wback_inv = &ax45mp_dma_cache_wback_inv,
+};
+
+static const struct of_device_id ax45mp_cache_ids[] = {
+	{ .compatible = "andestech,ax45mp-cache" },
+	{ /* sentinel */ }
+};
+
+static int __init ax45mp_cache_init(void)
+{
+	struct device_node *np;
+	struct resource res;
+	int ret;
+
+	np = of_find_matching_node(NULL, ax45mp_cache_ids);
+	if (!of_device_is_available(np))
+		return -ENODEV;
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret)
+		return ret;
+
+	/*
+	 * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size
+	 * will be 0 for sure, so we can definitely rely on it. If
+	 * riscv_cbom_block_size = 0 we don't need to handle CMO using SW any
+	 * more so we just return success here and only if its being set we
+	 * continue further in the probe path.
+	 */
+	if (!riscv_cbom_block_size)
+		return 0;
+
+	ax45mp_priv.l2c_base = ioremap(res.start, resource_size(&res));
+	if (!ax45mp_priv.l2c_base)
+		return -ENOMEM;
+
+	ret = ax45mp_get_l2_line_size(np);
+	if (ret) {
+		iounmap(ax45mp_priv.l2c_base);
+		return ret;
+	}
+
+	riscv_noncoherent_register_cache_ops(&ax45mp_cmo_ops);
+
+	return 0;
+}
+early_initcall(ax45mp_cache_init);
-- 
2.41.0


From f22d0a065267e8328882dac88cfc8bbde3bf9d27 Mon Sep 17 00:00:00 2001
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Sun, 2 Jul 2023 21:34:29 +0100
Subject: [PATCH 28/72] soc: renesas: Kconfig: Select the required configs for
 RZ/Five SoC

Explicitly select the required Cache management and Errata configs
required for the RZ/Five SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Link: https://lore.kernel.org/r/20230702203429.237615-7-prabhakar.mahadev-lad.rj@bp.renesas.com
---
 drivers/soc/renesas/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index de31589ed054..67604f24973e 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -334,6 +334,10 @@ if RISCV
 config ARCH_R9A07G043
 	bool "RISC-V Platform support for RZ/Five"
 	select ARCH_RZG2L
+	select AX45MP_L2_CACHE
+	select DMA_GLOBAL_POOL
+	select ERRATA_ANDES
+	select ERRATA_ANDES_CMO
 	help
 	  This enables support for the Renesas RZ/Five SoC.
 
-- 
2.41.0


From a77fe6b248891f0c2f6a501096d1e561f66df639 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Tue, 20 Jun 2023 15:23:43 +0200
Subject: [PATCH 29/72] dt-bindings: cache: sifive,ccache0: Support the
 StarFive JH7100 SoC

This cache controller is also used on the StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 8a6a78e1a7ab..7e8cebe21584 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -38,7 +38,9 @@ properties:
               - sifive,fu740-c000-ccache
           - const: cache
       - items:
-          - const: starfive,jh7110-ccache
+          - enum:
+              - starfive,jh7100-ccache
+              - starfive,jh7110-ccache
           - const: sifive,ccache0
           - const: cache
       - items:
@@ -88,6 +90,7 @@ allOf:
           contains:
             enum:
               - sifive,fu740-c000-ccache
+              - starfive,jh7100-ccache
               - starfive,jh7110-ccache
               - microchip,mpfs-ccache
 
@@ -111,6 +114,7 @@ allOf:
           contains:
             enum:
               - sifive,fu740-c000-ccache
+              - starfive,jh7100-ccache
               - starfive,jh7110-ccache
 
     then:
-- 
2.41.0


From 99c80741275eb66042174e478979a4c41bb2ab63 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Wed, 6 Apr 2022 00:38:05 +0200
Subject: [PATCH 30/72] soc: sifive: ccache: Add StarFive JH7100 support

This adds support for the StarFive JH7100 SoC which also feature this
SiFive cache controller.

Unfortunately the interrupt for uncorrected data is broken on the JH7100
and fires continuously, so add a quirk to not register a handler for it.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/soc/sifive/Kconfig         |  1 +
 drivers/soc/sifive/sifive_ccache.c | 11 ++++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index e86870be34c9..867cf16273a4 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -4,6 +4,7 @@ if SOC_SIFIVE || SOC_STARFIVE
 
 config SIFIVE_CCACHE
 	bool "Sifive Composable Cache controller"
+	default SOC_STARFIVE
 	help
 	  Support for the composable cache controller on SiFive platforms.
 
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 3684f5b40a80..676468c35859 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -106,6 +106,7 @@ static void ccache_config_read(void)
 static const struct of_device_id sifive_ccache_ids[] = {
 	{ .compatible = "sifive,fu540-c000-ccache" },
 	{ .compatible = "sifive,fu740-c000-ccache" },
+	{ .compatible = "starfive,jh7100-ccache", .data = (void *)BIT(DATA_UNCORR) },
 	{ .compatible = "sifive,ccache0" },
 	{ /* end of table */ }
 };
@@ -210,11 +211,15 @@ static int __init sifive_ccache_init(void)
 	struct device_node *np;
 	struct resource res;
 	int i, rc, intr_num;
+	const struct of_device_id *match;
+	unsigned long broken_irqs;
 
-	np = of_find_matching_node(NULL, sifive_ccache_ids);
+	np = of_find_matching_node_and_match(NULL, sifive_ccache_ids, &match);
 	if (!np)
 		return -ENODEV;
 
+	broken_irqs = (uintptr_t)match->data;
+
 	if (of_address_to_resource(np, 0, &res)) {
 		rc = -ENODEV;
 		goto err_node_put;
@@ -240,6 +245,10 @@ static int __init sifive_ccache_init(void)
 
 	for (i = 0; i < intr_num; i++) {
 		g_irq[i] = irq_of_parse_and_map(np, i);
+
+		if (broken_irqs & BIT(i))
+			continue;
+
 		rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc",
 				 NULL);
 		if (rc) {
-- 
2.41.0


From 717b35803246e6f4cadcde923571dec1ca7273e1 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Tue, 20 Jun 2023 15:26:12 +0200
Subject: [PATCH 31/72] dt-bindings: cache: sifive,ccache0: Add
 sifive,cache-ops property

This cache controller also supports flushing cache lines by writing
their address to a register. This can be used for cache management on
SoCs with non-coherent DMAs that predate the RISC-V Zicbom extension
such as the StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 7e8cebe21584..fb7eca4a49f2 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -81,6 +81,11 @@ properties:
       The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
       The reserved memory node should be defined as per the bindings in reserved-memory.txt.
 
+  sifive,cache-ops:
+    type: boolean
+    description: |
+      Use the controllers cache flushing register for cache management operations.
+
 allOf:
   - $ref: /schemas/cache-controller.yaml#
 
-- 
2.41.0


From 7aae5aaeec179c22d4430e05e36fbfa599ac4a1a Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Sat, 12 Jun 2021 16:48:31 -0700
Subject: [PATCH 32/72] soc: sifive: ccache: Support cache management
 operations

This cache controller also supports flushing cache lines by writing
their address to a register. This can be used for cache management on
SoCs with non-coherent DMAs that predate the RISC-V Zicbom extension
such as the StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/soc/sifive/sifive_ccache.c | 45 +++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 676468c35859..0c609fc1334a 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -8,13 +8,16 @@
 
 #define pr_fmt(fmt) "CCACHE: " fmt
 
+#include <linux/align.h>
 #include <linux/debugfs.h>
 #include <linux/interrupt.h>
 #include <linux/of_irq.h>
 #include <linux/of_address.h>
 #include <linux/device.h>
 #include <linux/bitfield.h>
+#include <asm/cacheflush.h>
 #include <asm/cacheinfo.h>
+#include <asm/dma-noncoherent.h>
 #include <soc/sifive/sifive_ccache.h>
 
 #define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
@@ -39,10 +42,14 @@
 #define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16)
 #define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24)
 
+#define SIFIVE_CCACHE_FLUSH64 0x200
+#define SIFIVE_CCACHE_FLUSH32 0x240
+
 #define SIFIVE_CCACHE_WAYENABLE 0x08
 #define SIFIVE_CCACHE_ECCINJECTERR 0x40
 
 #define SIFIVE_CCACHE_MAX_ECCINTR 4
+#define SIFIVE_CCACHE_LINE_SIZE 64
 
 static void __iomem *ccache_base;
 static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
@@ -125,6 +132,34 @@ int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
 }
 EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+static void ccache_flush_range(phys_addr_t start, unsigned long len)
+{
+	phys_addr_t end = start + len;
+	phys_addr_t line;
+
+	if (!len)
+		return;
+
+	mb();
+	for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;
+			line += SIFIVE_CCACHE_LINE_SIZE) {
+#ifdef CONFIG_32BIT
+		writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);
+#else
+		writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);
+#endif
+		mb();
+	}
+}
+
+static const struct __initdata riscv_cache_ops ccache_mgmt_ops = {
+	.wback = &ccache_flush_range,
+	.inv = &ccache_flush_range,
+	.wback_inv = &ccache_flush_range,
+};
+#endif /* CONFIG_RISCV_NONSTANDARD_CACHE_OPS */
+
 static int ccache_largest_wayenabled(void)
 {
 	return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
@@ -258,6 +293,14 @@ static int __init sifive_ccache_init(void)
 	}
 	of_node_put(np);
 
+#ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS
+	if (of_property_read_bool(np, "sifive,cache-ops")) {
+		riscv_cbom_block_size = SIFIVE_CCACHE_LINE_SIZE;
+		riscv_noncoherent_supported();
+		riscv_noncoherent_register_cache_ops(&ccache_mgmt_ops);
+	}
+#endif
+
 	ccache_config_read();
 
 	ccache_cache_ops.get_priv_group = ccache_get_priv_group;
@@ -278,4 +321,4 @@ static int __init sifive_ccache_init(void)
 	return rc;
 }
 
-device_initcall(sifive_ccache_init);
+arch_initcall(sifive_ccache_init);
-- 
2.41.0


From ddd72e49bd2933d5479be2ee1c82bbe266f16f36 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sun, 23 Jul 2023 18:56:46 +0200
Subject: [PATCH 33/72] riscv: errata: Add StarFive JH7100 errata

This not really an errata, but since the JH7100 was made before
the standard Zicbom extension it needs the DMA_GLOBAL_POOL and
RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 arch/riscv/Kconfig.errata | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 92c779764b27..28ed844ad282 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -53,6 +53,22 @@ config ERRATA_SIFIVE_CIP_1200
 
 	  If you don't know what to do here, say "Y".
 
+config ERRATA_STARFIVE_JH7100
+	bool "StarFive JH7100 support"
+	depends on ARCH_STARFIVE
+	select DMA_GLOBAL_POOL
+	select RISCV_NONSTANDARD_CACHE_OPS
+	select SIFIVE_CCACHE
+	default n
+	help
+	  The StarFive JH7100 was a test chip for the JH7110 and has
+	  caches that are non-coherent with respect to peripheral DMAs.
+	  It was designed before the Zicbom extension so needs non-standard
+	  cache operations through the SiFive cache controller.
+
+	  Say "Y" if you want to support the BeagleV Starlight and/or
+	  StarFive VisionFive V1 boards.
+
 config ERRATA_THEAD
 	bool "T-HEAD errata"
 	depends on RISCV_ALTERNATIVE
-- 
2.41.0


From c902a23d9059f782581d91cc4ac8211d5897c26e Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Wed, 31 Aug 2022 22:54:07 +0200
Subject: [PATCH 34/72] riscv: dts: starfive: Mark the JH7100 as having
 non-coherent DMAs

The StarFive JH7100 SoC has non-coherent device DMAs, so mark the
soc bus as such.

Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 35ab54fb235f..1fe7a95caf55 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -136,6 +136,7 @@ gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
+		dma-noncoherent;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
-- 
2.41.0


From 242a4917e813f8cac49b4609caaf70072537fb91 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sun, 18 Jun 2023 19:45:52 +0200
Subject: [PATCH 35/72] riscv: dts: starfive: Add JH7100 cache controller

The StarFive JH7100 SoC also features the SiFive L2 cache controller.
This SoC has non-coherent DMAs, but predate the RISC-V Zicbom extension,
so we need the sifive,cache-ops property to use the cache controller for
cache flushing operations instead.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 1fe7a95caf55..f4979723b8e8 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -32,6 +32,7 @@ U74_0: cpu@0 {
 			i-tlb-sets = <1>;
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
 
@@ -57,6 +58,7 @@ U74_1: cpu@1 {
 			i-tlb-sets = <1>;
 			i-tlb-size = <32>;
 			mmu-type = "riscv,sv39";
+			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc";
 			tlb-split;
 
@@ -148,6 +150,18 @@ clint: clint@2000000 {
 					       &cpu1_intc 3 &cpu1_intc 7>;
 		};
 
+		ccache: cache-controller@2010000 {
+			compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
+			reg = <0x0 0x2010000 0x0 0x1000>;
+			interrupts = <128>, <130>, <131>, <129>;
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <2097152>;
+			cache-unified;
+			sifive,cache-ops;
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-- 
2.41.0


From d42adb94cafdd46865340e83fccc028430e6bb0c Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Mon, 19 Jun 2023 00:24:56 +0200
Subject: [PATCH 36/72] riscv: dts: starfive: Add pool for coherent DMA memory
 on JH7100 boards

The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers
expect to be able to allocate coherent memory for DMA descriptors and
such. However on the JH7100 DDR memory appears twice in the physical
memory map, once cached and once uncached:

  0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached
  0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached

To use this uncached region we create a global DMA memory pool there and
reserve the corresponding area in the cached region.

However the uncached region is fully above the 32bit address limit, so add
a dma-ranges map so the DMA address used for peripherals is still in the
regular cached region below the limit.

Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 .../boot/dts/starfive/jh7100-common.dtsi      | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index b93ce351a90f..504c73f01f14 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -39,6 +39,30 @@ led-ack {
 			label = "ack";
 		};
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		dma-reserved {
+			reg = <0x0 0xfa000000 0x0 0x1000000>;
+			no-map;
+		};
+
+		linux,dma {
+			compatible = "shared-dma-pool";
+			reg = <0x10 0x7a000000 0x0 0x1000000>;
+			no-map;
+			linux,dma-default;
+		};
+	};
+
+	soc {
+		dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>,
+			     <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
+			     <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
+	};
 };
 
 &gpio {
-- 
2.41.0


From 972c2dac1034d884a4b4be41d28b061de0d2b32a Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: Thu, 25 Nov 2021 14:21:18 +0100
Subject: [PATCH 37/72] riscv: dts: starfive: Group tuples in interrupt
 properties

To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.

Fix this by grouping the tuples of "interrupts-extended" properties
using angle brackets.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index f4979723b8e8..c6365d2aed5e 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -146,8 +146,8 @@ soc {
 		clint: clint@2000000 {
 			compatible = "starfive,jh7100-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
-			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
-					       &cpu1_intc 3 &cpu1_intc 7>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+					      <&cpu1_intc 3>, <&cpu1_intc 7>;
 		};
 
 		ccache: cache-controller@2010000 {
@@ -165,8 +165,8 @@ ccache: cache-controller@2010000 {
 		plic: interrupt-controller@c000000 {
 			compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-			interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
-					       &cpu1_intc 11 &cpu1_intc 9>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+					      <&cpu1_intc 11>, <&cpu1_intc 9>;
 			interrupt-controller;
 			#address-cells = <0>;
 			#interrupt-cells = <1>;
-- 
2.41.0


From 7a70df7cf05f00e43f150df1207ae839d5c796df Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sun, 18 Jun 2023 19:54:56 +0200
Subject: [PATCH 38/72] riscv: dts: starfive: Add JH7100 MMC nodes

Add device tree nodes for the MMC controllers on the StarFive JH7100
SoC and pinctrl settings for the boards using it.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 .../boot/dts/starfive/jh7100-common.dtsi      | 81 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7100.dtsi      | 26 ++++++
 2 files changed, 107 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index 504c73f01f14..2390ddbf4d3e 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -108,6 +108,78 @@ GPO_I2C2_PAD_SDA_OEN,
 		};
 	};
 
+	sdio0_pins: sdio0-0 {
+		clk-pins {
+			pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
+				  GPO_ENABLE, GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+		sdio-pins {
+			pinmux = <GPIOMUX(55, GPO_LOW, GPO_DISABLE,
+				  GPI_SDIO0_PAD_CARD_DETECT_N)>,
+				 <GPIOMUX(53,
+				  GPO_SDIO0_PAD_CCMD_OUT,
+				  GPO_SDIO0_PAD_CCMD_OEN,
+				  GPI_SDIO0_PAD_CCMD_IN)>,
+				 <GPIOMUX(49,
+				  GPO_SDIO0_PAD_CDATA_OUT_BIT0,
+				  GPO_SDIO0_PAD_CDATA_OEN_BIT0,
+				  GPI_SDIO0_PAD_CDATA_IN_BIT0)>,
+				 <GPIOMUX(50,
+				  GPO_SDIO0_PAD_CDATA_OUT_BIT1,
+				  GPO_SDIO0_PAD_CDATA_OEN_BIT1,
+				  GPI_SDIO0_PAD_CDATA_IN_BIT1)>,
+				 <GPIOMUX(51,
+				  GPO_SDIO0_PAD_CDATA_OUT_BIT2,
+				  GPO_SDIO0_PAD_CDATA_OEN_BIT2,
+				  GPI_SDIO0_PAD_CDATA_IN_BIT2)>,
+				 <GPIOMUX(52,
+				  GPO_SDIO0_PAD_CDATA_OUT_BIT3,
+				  GPO_SDIO0_PAD_CDATA_OEN_BIT3,
+				  GPI_SDIO0_PAD_CDATA_IN_BIT3)>;
+			bias-pull-up;
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	sdio1_pins: sdio1-0 {
+		clk-pins {
+			pinmux = <GPIOMUX(33, GPO_SDIO1_PAD_CCLK_OUT,
+				  GPO_ENABLE, GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+		sdio-pins {
+			pinmux = <GPIOMUX(29,
+				  GPO_SDIO1_PAD_CCMD_OUT,
+				  GPO_SDIO1_PAD_CCMD_OEN,
+				  GPI_SDIO1_PAD_CCMD_IN)>,
+				 <GPIOMUX(36,
+				  GPO_SDIO1_PAD_CDATA_OUT_BIT0,
+				  GPO_SDIO1_PAD_CDATA_OEN_BIT0,
+				  GPI_SDIO1_PAD_CDATA_IN_BIT0)>,
+				 <GPIOMUX(30,
+				  GPO_SDIO1_PAD_CDATA_OUT_BIT1,
+				  GPO_SDIO1_PAD_CDATA_OEN_BIT1,
+				  GPI_SDIO1_PAD_CDATA_IN_BIT1)>,
+				 <GPIOMUX(34,
+				  GPO_SDIO1_PAD_CDATA_OUT_BIT2,
+				  GPO_SDIO1_PAD_CDATA_OEN_BIT2,
+				  GPI_SDIO1_PAD_CDATA_IN_BIT2)>,
+				 <GPIOMUX(31,
+				  GPO_SDIO1_PAD_CDATA_OUT_BIT3,
+				  GPO_SDIO1_PAD_CDATA_OEN_BIT3,
+				  GPI_SDIO1_PAD_CDATA_IN_BIT3)>;
+			bias-pull-up;
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
 	uart3_pins: uart3-0 {
 		rx-pins {
 			pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
@@ -178,6 +250,15 @@ &osc_aud {
 	clock-frequency = <27000000>;
 };
 
+&sdio0 {
+	broken-cd;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_pins>;
+	status = "okay";
+};
+
 &uart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart3_pins>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index c6365d2aed5e..3576499e4292 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -173,6 +173,32 @@ plic: interrupt-controller@c000000 {
 			riscv,ndev = <133>;
 		};
 
+		sdio0: mmc@10000000 {
+			compatible = "snps,dw-mshc";
+			reg = <0x0 0x10000000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
+				 <&clkgen JH7100_CLK_SDIO0_CCLKINT_INV>;
+			clock-names = "biu", "ciu";
+			interrupts = <4>;
+			data-addr = <0>;
+			fifo-depth = <32>;
+			fifo-watermark-aligned;
+			status = "disabled";
+		};
+
+		sdio1: mmc@10010000 {
+			compatible = "snps,dw-mshc";
+			reg = <0x0 0x10010000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
+				 <&clkgen JH7100_CLK_SDIO1_CCLKINT_INV>;
+			clock-names = "biu", "ciu";
+			interrupts = <5>;
+			data-addr = <0>;
+			fifo-depth = <32>;
+			fifo-watermark-aligned;
+			status = "disabled";
+		};
+
 		clkgen: clock-controller@11800000 {
 			compatible = "starfive,jh7100-clkgen";
 			reg = <0x0 0x11800000 0x0 0x10000>;
-- 
2.41.0


From 1580177a43b10de0dda5e52380476ebd86c2a03c Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sat, 25 Mar 2023 22:57:06 +0100
Subject: [PATCH 39/72] clk: starfive: Add flags argument to JH71X0__MUX macro

This flag is needed to add the CLK_SET_RATE_PARENT flag on the gmac_tx
clock on the JH7100, which in turn is needed by the dwmac-starfive
driver to set the clock properly for 1000, 100 and 10 Mbps links.

This change was mostly made using coccinelle:

@ match @
expression idx, name, nparents;
@@
 JH71X0__MUX(
-idx, name, nparents,
+idx, name, 0, nparents,
 ...)

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 .../clk/starfive/clk-starfive-jh7100-audio.c  |  2 +-
 drivers/clk/starfive/clk-starfive-jh7100.c    | 32 +++++++++----------
 .../clk/starfive/clk-starfive-jh7110-aon.c    |  6 ++--
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 26 +++++++--------
 drivers/clk/starfive/clk-starfive-jh71x0.h    |  4 +--
 5 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index 02aefb7264f8..7141ed244782 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -80,7 +80,7 @@ static const struct jh71x0_clk_data jh7100_audclk_data[] = {
 	JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
 	JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
 	JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
-	JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
+	JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 0, 2,
 		    JH7100_AUDCLK_VAD_INTMEM,
 		    JH7100_AUDCLK_AUDIO_12288),
 };
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 69cc11ea7e33..d3b260c01d5c 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -24,48 +24,48 @@
 #define JH7100_CLK_GMAC_GR_MII_RX	(JH7100_CLK_END + 3)
 
 static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
-	JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
+	JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 0, 4,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_PLL0_OUT,
 		    JH7100_CLK_PLL1_OUT,
 		    JH7100_CLK_PLL2_OUT),
-	JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
+	JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 0, 3,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_PLL1_OUT,
 		    JH7100_CLK_PLL2_OUT),
-	JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
+	JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 0, 4,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_PLL0_OUT,
 		    JH7100_CLK_PLL1_OUT,
 		    JH7100_CLK_PLL2_OUT),
-	JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
+	JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 0, 3,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_PLL0_OUT,
 		    JH7100_CLK_PLL2_OUT),
-	JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
+	JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 0, 2,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_PLL0_OUT),
-	JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
+	JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 0, 2,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_PLL2_OUT),
-	JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
+	JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 0, 3,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_PLL1_OUT,
 		    JH7100_CLK_PLL2_OUT),
-	JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
+	JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 0, 3,
 		    JH7100_CLK_OSC_AUD,
 		    JH7100_CLK_PLL0_OUT,
 		    JH7100_CLK_PLL2_OUT),
 	JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
-	JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
+	JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 0, 3,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_PLL1_OUT,
 		    JH7100_CLK_PLL2_OUT),
-	JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
+	JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 0, 3,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_PLL0_OUT,
 		    JH7100_CLK_PLL1_OUT),
-	JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
+	JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 0, 3,
 		    JH7100_CLK_OSC_AUD,
 		    JH7100_CLK_PLL0_OUT,
 		    JH7100_CLK_PLL2_OUT),
@@ -76,7 +76,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
 	JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
 	JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
 	JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
-	JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
+	JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 0, 2,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_OSC_AUD),
 	JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
@@ -142,7 +142,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
 	JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
 	JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
 	JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
-	JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
+	JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 0, 2,
 		    JH7100_CLK_CPU_AXI,
 		    JH7100_CLK_NNEBUS_SRC1),
 	JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
@@ -166,7 +166,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
 	JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
 	JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
 		    JH7100_CLK_USBPHY_ROOTDIV),
-	JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
+	JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 0, 2,
 		    JH7100_CLK_OSC_SYS,
 		    JH7100_CLK_USBPHY_PLLDIV25M),
 	JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
@@ -200,12 +200,12 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
 	JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
 	JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
 	JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
-	JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
+	JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 0, 3,
 		    JH7100_CLK_GMAC_GTX,
 		    JH7100_CLK_GMAC_TX_INV,
 		    JH7100_CLK_GMAC_RMII_TX),
 	JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
-	JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
+	JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 0, 2,
 		    JH7100_CLK_GMAC_GR_MII_RX,
 		    JH7100_CLK_GMAC_RMII_RX),
 	JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
index 62954eb7b50a..418efdad719b 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
@@ -26,7 +26,7 @@
 static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
 	/* source */
 	JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
-	JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
+	JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 0, 2,
 		    JH7110_AONCLK_OSC_DIV4,
 		    JH7110_AONCLK_OSC),
 	/* gmac0 */
@@ -39,7 +39,7 @@ static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
 		    JH7110_AONCLK_GMAC0_GTXCLK,
 		    JH7110_AONCLK_GMAC0_RMII_RTX),
 	JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
-	JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
+	JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 0, 2,
 		    JH7110_AONCLK_GMAC0_RGMII_RXIN,
 		    JH7110_AONCLK_GMAC0_RMII_RTX),
 	JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
@@ -48,7 +48,7 @@ static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
 	/* rtc */
 	JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
 	JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
-	JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
+	JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 0, 2,
 		    JH7110_AONCLK_RTC_OSC,
 		    JH7110_AONCLK_RTC_INTERNAL),
 	JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index e6031345ef05..a3462491ee06 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -35,18 +35,18 @@
 
 static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
 	/* root */
-	JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
+	JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 0, 2,
 		    JH7110_SYSCLK_OSC,
 		    JH7110_SYSCLK_PLL0_OUT),
 	JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
 	JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
-	JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
+	JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 0, 2,
 		    JH7110_SYSCLK_PLL2_OUT,
 		    JH7110_SYSCLK_PLL1_OUT),
 	JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
 		    JH7110_SYSCLK_PLL0_OUT,
 		    JH7110_SYSCLK_PLL2_OUT),
-	JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
+	JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 0, 2,
 		    JH7110_SYSCLK_OSC,
 		    JH7110_SYSCLK_PLL2_OUT),
 	JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
@@ -61,7 +61,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
 	JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
 	JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
 	JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
-	JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
+	JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 0, 2,
 		    JH7110_SYSCLK_MCLK_INNER,
 		    JH7110_SYSCLK_MCLK_EXT),
 	JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
@@ -95,7 +95,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
 	JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
 	JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
 	JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
-	JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
+	JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 0, 4,
 		    JH7110_SYSCLK_OSC_DIV2,
 		    JH7110_SYSCLK_PLL1_DIV2,
 		    JH7110_SYSCLK_PLL1_DIV4,
@@ -185,7 +185,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
 	JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
 		    JH7110_SYSCLK_GMAC1_RMII_REFIN),
 	JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
-	JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
+	JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 0, 2,
 		    JH7110_SYSCLK_GMAC1_RGMII_RXIN,
 		    JH7110_SYSCLK_GMAC1_RMII_RTX),
 	JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
@@ -269,11 +269,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
 	JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
 		    JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
 		    JH7110_SYSCLK_I2STX0_BCLK_MST),
-	JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk",	2,
+	JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 0, 2,
 		    JH7110_SYSCLK_I2STX0_BCLK_MST,
 		    JH7110_SYSCLK_I2STX_BCLK_EXT),
 	JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
-	JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
+	JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 0, 2,
 		    JH7110_SYSCLK_I2STX0_LRCK_MST,
 		    JH7110_SYSCLK_I2STX_LRCK_EXT),
 	/* i2stx1 */
@@ -284,11 +284,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
 	JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
 		    JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
 		    JH7110_SYSCLK_I2STX1_BCLK_MST),
-	JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
+	JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 0, 2,
 		    JH7110_SYSCLK_I2STX1_BCLK_MST,
 		    JH7110_SYSCLK_I2STX_BCLK_EXT),
 	JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
-	JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
+	JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 0, 2,
 		    JH7110_SYSCLK_I2STX1_LRCK_MST,
 		    JH7110_SYSCLK_I2STX_LRCK_EXT),
 	/* i2srx */
@@ -299,11 +299,11 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
 	JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
 		    JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
 		    JH7110_SYSCLK_I2SRX_BCLK_MST),
-	JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
+	JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 0, 2,
 		    JH7110_SYSCLK_I2SRX_BCLK_MST,
 		    JH7110_SYSCLK_I2SRX_BCLK_EXT),
 	JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
-	JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
+	JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 0, 2,
 		    JH7110_SYSCLK_I2SRX_LRCK_MST,
 		    JH7110_SYSCLK_I2SRX_LRCK_EXT),
 	/* pdm */
@@ -313,7 +313,7 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
 	JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
 	JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
 	JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
-	JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
+	JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 0, 2,
 		    JH7110_SYSCLK_TDM_INTERNAL,
 		    JH7110_SYSCLK_TDM_EXT),
 	JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
index 34bb11c72eb7..23e052fc1549 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
@@ -61,10 +61,10 @@ struct jh71x0_clk_data {
 	.parents = { [0] = _parent },						\
 }
 
-#define JH71X0__MUX(_idx, _name, _nparents, ...)				\
+#define JH71X0__MUX(_idx, _name, _flags, _nparents, ...)			\
 [_idx] = {									\
 	.name = _name,								\
-	.flags = 0,								\
+	.flags = _flags,							\
 	.max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT,			\
 	.parents = { __VA_ARGS__ },						\
 }
-- 
2.41.0


From 5cd800da48ca82a7718390375438cf5af26f044a Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sat, 25 Mar 2023 23:04:31 +0100
Subject: [PATCH 40/72] clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to
 gmac_tx

This is needed by the dwmac-starfive ethernet driver to set the clock
for 1000, 100 and 10 Mbps links properly.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 drivers/clk/starfive/clk-starfive-jh7100.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index d3b260c01d5c..03f6f26a15d8 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -200,7 +200,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
 	JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
 	JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
 	JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
-	JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 0, 3,
+	JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 3,
 		    JH7100_CLK_GMAC_GTX,
 		    JH7100_CLK_GMAC_TX_INV,
 		    JH7100_CLK_GMAC_RMII_TX),
-- 
2.41.0


From 40f81618fa1593f7e65b2aeb421bfa5c78c20e42 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Wed, 29 Sep 2021 20:50:22 +0200
Subject: [PATCH 41/72] net: stmmac: dwmac-starfive: Add JH7100 support

This adds support for setting the phy interface and delay chains on the
StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 .../net/ethernet/stmicro/stmmac/dwmac-starfive.c    | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
index d3a39d2fb3a9..2ea1c9477821 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
@@ -17,6 +17,10 @@
 #define STARFIVE_DWMAC_PHY_INFT_RMII	0x4
 #define STARFIVE_DWMAC_PHY_INFT_FIELD	0x7U
 
+#define JH7100_SYSMAIN_REGISTER28 0x70
+/* The value below is not a typo, just really bad naming by StarFive ¯\_(ツ)_/¯ */
+#define JH7100_SYSMAIN_REGISTER49 0xc8
+
 struct starfive_dwmac {
 	struct device *dev;
 	struct clk *clk_tx;
@@ -56,6 +60,7 @@ static int starfive_dwmac_set_mode(struct plat_stmmacenet_data *plat_dat)
 	struct regmap *regmap;
 	unsigned int args[2];
 	unsigned int mode;
+	u32 gtxclk_dlychain;
 	int err;
 
 	switch (plat_dat->interface) {
@@ -65,6 +70,7 @@ static int starfive_dwmac_set_mode(struct plat_stmmacenet_data *plat_dat)
 
 	case PHY_INTERFACE_MODE_RGMII:
 	case PHY_INTERFACE_MODE_RGMII_ID:
+	case PHY_INTERFACE_MODE_RGMII_TXID:
 		mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
 		break;
 
@@ -87,6 +93,12 @@ static int starfive_dwmac_set_mode(struct plat_stmmacenet_data *plat_dat)
 	if (err)
 		return dev_err_probe(dwmac->dev, err, "error setting phy mode\n");
 
+	if (!of_property_read_u32(dwmac->dev->of_node, "starfive,gtxclk-dlychain", &gtxclk_dlychain)) {
+		err = regmap_write(regmap, JH7100_SYSMAIN_REGISTER49, gtxclk_dlychain);
+		if (err)
+			return dev_err_probe(dwmac->dev, err, "error selecting gtxclk delay chain\n");
+	}
+
 	return 0;
 }
 
@@ -149,6 +161,7 @@ static int starfive_dwmac_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id starfive_dwmac_match[] = {
+	{ .compatible = "starfive,jh7100-dwmac"	},
 	{ .compatible = "starfive,jh7110-dwmac"	},
 	{ /* sentinel */ }
 };
-- 
2.41.0


From 29463fd1d5a841907c7771bce5393fe2b85cd416 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sun, 18 Jun 2023 19:58:14 +0200
Subject: [PATCH 42/72] riscv: dts: starfive: Add JH7100 sysmain node

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 3576499e4292..98cff0ab8f11 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -213,6 +213,11 @@ rstgen: reset-controller@11840000 {
 			#reset-cells = <1>;
 		};
 
+		sysmain: syscon@11850000 {
+			compatible = "starfive,jh7100-sysmain", "syscon";
+			reg = <0x0 0x11850000 0x0 0x10000>;
+		};
+
 		i2c0: i2c@118b0000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x0 0x118b0000 0x0 0x10000>;
-- 
2.41.0


From 77fda858b183cfab8589eaeb14ab1fccf3b14b1d Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Tue, 20 Jun 2023 20:38:23 +0200
Subject: [PATCH 43/72] dt-bindings: net: Add StarFive JH7100 dwmac support

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 .../devicetree/bindings/net/snps,dwmac.yaml          |  1 +
 .../bindings/net/starfive,jh7110-dwmac.yaml          | 12 ++++++++----
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index ddf9522a5dc2..0d7114a4fa26 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -95,6 +95,7 @@ properties:
         - snps,dwmac-5.20
         - snps,dwxgmac
         - snps,dwxgmac-2.10
+        - starfive,jh7100-dwmac
         - starfive,jh7110-dwmac
 
   reg:
diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
index 5e7cfbbebce6..abf68df44970 100644
--- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
@@ -22,10 +22,14 @@ select:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - starfive,jh7110-dwmac
-      - const: snps,dwmac-5.20
+    oneOf:
+      - items:
+          - const: starfive,jh7100-dwmac
+          - const: snps,dwmac
+      - items:
+          - enum:
+              - starfive,jh7110-dwmac
+          - const: snps,dwmac-5.20
 
   reg:
     maxItems: 1
-- 
2.41.0


From 13978a3c3c615f8e9eb043c3a22e63905b75cef4 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sun, 18 Jun 2023 20:02:57 +0200
Subject: [PATCH 44/72] riscv: dts: starfive: Add JH7100 ethernet nodes

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 .../dts/starfive/jh7100-beaglev-starlight.dts | 10 +++
 .../boot/dts/starfive/jh7100-common.dtsi      | 86 +++++++++++++++++++
 .../jh7100-starfive-visionfive-v1.dts         |  6 ++
 arch/riscv/boot/dts/starfive/jh7100.dtsi      | 33 +++++++
 4 files changed, 135 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
index 7cda3a89020a..22dfeddeee17 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
@@ -11,3 +11,13 @@ / {
 	model = "BeagleV Starlight Beta";
 	compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
 };
+
+&gmac {
+	snps,reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
+};
+
+&mdio {
+	phy: ethernet-phy@7 {
+		reg = <7>;
+	};
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index 2390ddbf4d3e..c3b3f5945036 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -65,7 +65,93 @@ soc {
 	};
 };
 
+&gmac {
+	starfive,gtxclk-dlychain = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac_pins>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&phy>;
+	status = "okay";
+
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+	};
+};
+
 &gpio {
+	gmac_pins: gmac-0 {
+		gtxclk-pins {
+			pins = <PAD_FUNC_SHARE(115)>;
+			bias-pull-up;
+			drive-strength = <35>;
+			input-enable;
+			input-schmitt-enable;
+			slew-rate = <0>;
+		};
+		miitxclk-pins {
+			pins = <PAD_FUNC_SHARE(116)>;
+			bias-pull-up;
+			drive-strength = <14>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+		tx-pins {
+			pins = <PAD_FUNC_SHARE(117)>,
+			       <PAD_FUNC_SHARE(119)>,
+			       <PAD_FUNC_SHARE(120)>,
+			       <PAD_FUNC_SHARE(121)>,
+			       <PAD_FUNC_SHARE(122)>,
+			       <PAD_FUNC_SHARE(123)>,
+			       <PAD_FUNC_SHARE(124)>,
+			       <PAD_FUNC_SHARE(125)>,
+			       <PAD_FUNC_SHARE(126)>;
+			bias-pull-up;
+			drive-strength = <35>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+		rxclk-pins {
+			pins = <PAD_FUNC_SHARE(127)>;
+			bias-pull-up;
+			drive-strength = <14>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <6>;
+		};
+		rxer-pins {
+			pins = <PAD_FUNC_SHARE(129)>;
+			bias-pull-up;
+			drive-strength = <14>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+		rx-pins {
+			pins = <PAD_FUNC_SHARE(128)>,
+			       <PAD_FUNC_SHARE(130)>,
+			       <PAD_FUNC_SHARE(131)>,
+			       <PAD_FUNC_SHARE(132)>,
+			       <PAD_FUNC_SHARE(133)>,
+			       <PAD_FUNC_SHARE(134)>,
+			       <PAD_FUNC_SHARE(135)>,
+			       <PAD_FUNC_SHARE(136)>,
+			       <PAD_FUNC_SHARE(137)>,
+			       <PAD_FUNC_SHARE(138)>,
+			       <PAD_FUNC_SHARE(139)>,
+			       <PAD_FUNC_SHARE(140)>,
+			       <PAD_FUNC_SHARE(141)>;
+			bias-pull-up;
+			drive-strength = <14>;
+			input-enable;
+			input-schmitt-enable;
+			slew-rate = <0>;
+		};
+	};
+
 	i2c0_pins: i2c0-0 {
 		i2c-pins {
 			pinmux = <GPIOMUX(62, GPO_LOW,
diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
index e82af72f1aaf..f9744938f0ce 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
+++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
@@ -18,3 +18,9 @@ gpio-restart {
 		priority = <224>;
 	};
 };
+
+&mdio {
+	phy: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 98cff0ab8f11..6f54c8ba51f0 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -135,6 +135,13 @@ gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
 		clock-frequency = <0>;
 	};
 
+	/* gmac device configuration */
+	stmmac_axi_setup: stmmac-axi-config {
+		snps,wr_osr_lmt = <16>;
+		snps,rd_osr_lmt = <16>;
+		snps,blen = <256 128 64 32 0 0 0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
@@ -199,6 +206,32 @@ sdio1: mmc@10010000 {
 			status = "disabled";
 		};
 
+		gmac: ethernet@10020000 {
+			compatible = "starfive,jh7100-dwmac", "snps,dwmac";
+			reg = <0x0 0x10020000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_GMAC_ROOT_DIV>,
+				 <&clkgen JH7100_CLK_GMAC_AHB>,
+				 <&clkgen JH7100_CLK_GMAC_PTP_REF>,
+				 <&clkgen JH7100_CLK_GMAC_TX_INV>,
+				 <&clkgen JH7100_CLK_GMAC_GTX>;
+			clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
+			resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
+			reset-names = "stmmaceth";
+			interrupts = <6>, <7>;
+			interrupt-names = "macirq", "eth_wake_irq";
+			max-frame-size = <9000>;
+			snps,multicast-filter-bins = <0>;
+			snps,perfect-filter-entries = <128>;
+			starfive,syscon = <&sysmain 0x70 0>;
+			rx-fifo-depth = <32768>;
+			tx-fifo-depth = <16384>;
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,fixed-burst;
+			snps,force_thresh_dma_mode;
+			snps,no-pbl-x8;
+			status = "disabled";
+		};
+
 		clkgen: clock-controller@11800000 {
 			compatible = "starfive,jh7100-clkgen";
 			reg = <0x0 0x11800000 0x0 0x10000>;
-- 
2.41.0


From 665510896d6fffb16ccac73425ad51d2b95e7acb Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Sat, 20 Nov 2021 17:13:22 +0100
Subject: [PATCH 45/72] riscv: dts: starfive: Add StarFive JH7100 audio clock
 node

Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 6f54c8ba51f0..b55cf2d00ee8 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -232,6 +232,16 @@ gmac: ethernet@10020000 {
 			status = "disabled";
 		};
 
+		audclk: clock-controller@10480000 {
+			compatible = "starfive,jh7100-audclk";
+			reg = <0x0 0x10480000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
+				 <&clkgen JH7100_CLK_AUDIO_12288>,
+				 <&clkgen JH7100_CLK_DOM7AHB_BUS>;
+			clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
+			#clock-cells = <1>;
+		};
+
 		clkgen: clock-controller@11800000 {
 			compatible = "starfive,jh7100-clkgen";
 			reg = <0x0 0x11800000 0x0 0x10000>;
-- 
2.41.0


From fdb35253abd2ba2866169c0d3770f47251a4b8ef Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Sat, 20 Nov 2021 19:29:25 +0100
Subject: [PATCH 46/72] dt-bindings: reset: Add StarFive JH7100 audio reset
 definitions

Add all resets for the StarFive JH7100 audio reset controller.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 .../dt-bindings/reset/starfive-jh7100-audio.h | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 include/dt-bindings/reset/starfive-jh7100-audio.h

diff --git a/include/dt-bindings/reset/starfive-jh7100-audio.h b/include/dt-bindings/reset/starfive-jh7100-audio.h
new file mode 100644
index 000000000000..30e3d4cf067a
--- /dev/null
+++ b/include/dt-bindings/reset/starfive-jh7100-audio.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2021 Emil Renner Berthing
+ */
+
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__
+
+#define JH7100_AUDRSTN_APB_BUS		0
+#define JH7100_AUDRSTN_I2SADC_APB	1
+#define JH7100_AUDRSTN_I2SADC_SRST	2
+#define JH7100_AUDRSTN_PDM_APB		3
+#define JH7100_AUDRSTN_I2SVAD_APB	4
+#define JH7100_AUDRSTN_I2SVAD_SRST	5
+#define JH7100_AUDRSTN_SPDIF_APB	6
+#define JH7100_AUDRSTN_PWMDAC_APB	7
+#define JH7100_AUDRSTN_I2SDAC_APB	8
+#define JH7100_AUDRSTN_I2SDAC_SRST	9
+#define JH7100_AUDRSTN_I2S1_APB		10
+#define JH7100_AUDRSTN_I2S1_SRST	11
+#define JH7100_AUDRSTN_I2SDAC16K_APB	12
+#define JH7100_AUDRSTN_I2SDAC16K_SRST	13
+#define JH7100_AUDRSTN_DMA1P_AHB	14
+#define JH7100_AUDRSTN_USB_APB		15
+#define JH7100_AUDRST_USB_AXI		16
+#define JH7100_AUDRST_USB_PWRUP_RST_N	17
+#define JH7100_AUDRST_USB_PONRST	18
+
+#define JH7100_AUDRSTN_END		19
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_AUDIO_H__ */
-- 
2.41.0


From 3856e81da937ed24e5c8d1e39cce65140df85263 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Tue, 7 Dec 2021 21:48:51 +0100
Subject: [PATCH 47/72] dt-bindings: reset: Add starfive,jh7100-audrst bindings

Add bindings for the audio reset controller on the StarFive JH7100
RISC-V SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 .../reset/starfive,jh7100-audrst.yaml         | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/starfive,jh7100-audrst.yaml

diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7100-audrst.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7100-audrst.yaml
new file mode 100644
index 000000000000..6ed85cc84c95
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/starfive,jh7100-audrst.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/starfive,jh7100-audrst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7100 SoC Audio Reset Controller Device Tree Bindings
+
+maintainers:
+  - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+  compatible:
+    enum:
+      - starfive,jh7100-audrst
+
+  reg:
+    maxItems: 1
+
+  "#reset-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    reset-controller@10490000 {
+        compatible = "starfive,jh7100-audrst";
+        reg = <0x10490000 0x10000>;
+        #reset-cells = <1>;
+    };
+
+...
-- 
2.41.0


From d9158e0c9c8ae2dda4b71a79aa48e76004eae9a0 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Sat, 20 Nov 2021 19:30:49 +0100
Subject: [PATCH 48/72] reset: starfive: Add JH7100 audio reset driver

The audio resets are almost identical to the system resets, there are
just fewer of them. So factor out and export a generic probe function,
so most of the reset controller implementation can be shared.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 MAINTAINERS                                   |  2 +-
 drivers/reset/starfive/Kconfig                |  7 ++
 drivers/reset/starfive/Makefile               |  2 +
 .../starfive/reset-starfive-jh7100-audio.c    | 66 +++++++++++++++++++
 .../reset/starfive/reset-starfive-jh7100.h    | 16 +++++
 5 files changed, 92 insertions(+), 1 deletion(-)
 create mode 100644 drivers/reset/starfive/reset-starfive-jh7100-audio.c
 create mode 100644 drivers/reset/starfive/reset-starfive-jh7100.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 0a574b497a1b..0fdabb609c86 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20319,7 +20319,7 @@ STARFIVE JH71X0 RESET CONTROLLER DRIVERS
 M:	Emil Renner Berthing <kernel@esmil.dk>
 M:	Hal Feng <hal.feng@starfivetech.com>
 S:	Maintained
-F:	Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
+F:	Documentation/devicetree/bindings/reset/starfive,jh7100-*.yaml
 F:	drivers/reset/starfive/reset-starfive-jh71*
 F:	include/dt-bindings/reset/starfive?jh71*.h
 
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index d832339f61bc..e125c877875b 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -11,6 +11,13 @@ config RESET_STARFIVE_JH7100
 	help
 	  This enables the reset controller driver for the StarFive JH7100 SoC.
 
+config RESET_STARFIVE_JH7100_AUDIO
+	tristate "StarFive JH7100 Audio Reset Driver"
+	depends on RESET_STARFIVE_JH7100
+	default m if SOC_STARFIVE
+	help
+	  This enables the audio reset driver for the StarFive JH7100 SoC.
+
 config RESET_STARFIVE_JH7110
 	bool "StarFive JH7110 Reset Driver"
 	depends on CLK_STARFIVE_JH7110_SYS
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 7a44b66fb9d5..ed8683748d31 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -2,4 +2,6 @@
 obj-$(CONFIG_RESET_STARFIVE_JH71X0)		+= reset-starfive-jh71x0.o
 
 obj-$(CONFIG_RESET_STARFIVE_JH7100)		+= reset-starfive-jh7100.o
+obj-$(CONFIG_RESET_STARFIVE_JH7100_AUDIO)	+= reset-starfive-jh7100-audio.o
+
 obj-$(CONFIG_RESET_STARFIVE_JH7110)		+= reset-starfive-jh7110.o
diff --git a/drivers/reset/starfive/reset-starfive-jh7100-audio.c b/drivers/reset/starfive/reset-starfive-jh7100-audio.c
new file mode 100644
index 000000000000..44ffef634fed
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jh7100-audio.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Audio reset driver for the StarFive JH7100 SoC
+ *
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "reset-starfive-jh71x0.h"
+
+#include <dt-bindings/reset/starfive-jh7100-audio.h>
+
+/* register offsets */
+#define JH7100_AUDRST_ASSERT0	0x00
+#define JH7100_AUDRST_STATUS0	0x04
+
+/*
+ * Writing a 1 to the n'th bit of the ASSERT register asserts
+ * line n, and writing a 0 deasserts the same line.
+ * Most reset lines have their status inverted so a 0 bit in the STATUS
+ * register means the line is asserted and a 1 means it's deasserted. A few
+ * lines don't though, so store the expected value of the status registers when
+ * all lines are asserted.
+ */
+static const u32 jh7100_audrst_asserted[1] = {
+	BIT(JH7100_AUDRST_USB_AXI) |
+	BIT(JH7100_AUDRST_USB_PWRUP_RST_N) |
+	BIT(JH7100_AUDRST_USB_PONRST)
+};
+
+static int jh7100_audrst_probe(struct platform_device *pdev)
+{
+	void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
+
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
+					      base + JH7100_AUDRST_ASSERT0,
+					      base + JH7100_AUDRST_STATUS0,
+					      jh7100_audrst_asserted,
+					      JH7100_AUDRSTN_END,
+					      THIS_MODULE);
+}
+
+static const struct of_device_id jh7100_audrst_dt_ids[] = {
+	{ .compatible = "starfive,jh7100-audrst" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7100_audrst_dt_ids);
+
+static struct platform_driver jh7100_audrst_driver = {
+	.probe = jh7100_audrst_probe,
+	.driver = {
+		.name = "jh7100-reset-audio",
+		.of_match_table = jh7100_audrst_dt_ids,
+	},
+};
+module_platform_driver(jh7100_audrst_driver);
+
+MODULE_AUTHOR("Emil Renner Berthing");
+MODULE_DESCRIPTION("StarFive JH7100 audio reset driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/reset/starfive/reset-starfive-jh7100.h b/drivers/reset/starfive/reset-starfive-jh7100.h
new file mode 100644
index 000000000000..ee8f3e3b1644
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jh7100.h
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#ifndef _RESET_STARFIVE_JH7100_H_
+#define _RESET_STARFIVE_JH7100_H_
+
+#include <linux/platform_device.h>
+
+int reset_starfive_jh7100_generic_probe(struct platform_device *pdev,
+					const u32 *asserted,
+					unsigned int status_offset,
+					unsigned int nr_resets);
+
+#endif
-- 
2.41.0


From 1e9173690f61dece3fec1d0918f7b45b280a2f0a Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Sat, 20 Nov 2021 21:33:08 +0100
Subject: [PATCH 49/72] riscv: dts: starfive: Add StarFive JH7100 audio reset
 node

Add device tree node for the audio resets on the StarFive JH7100 RISC-V
SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index b55cf2d00ee8..c59c7be3800a 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -242,6 +242,12 @@ audclk: clock-controller@10480000 {
 			#clock-cells = <1>;
 		};
 
+		audrst: reset-controller@10490000 {
+			compatible = "starfive,jh7100-audrst";
+			reg = <0x0 0x10490000 0x0 0x10000>;
+			#reset-cells = <1>;
+		};
+
 		clkgen: clock-controller@11800000 {
 			compatible = "starfive,jh7100-clkgen";
 			reg = <0x0 0x11800000 0x0 0x10000>;
-- 
2.41.0


From df6598883cab77152dbde95291c7932159f829df Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Sun, 3 Jul 2022 21:01:11 +0200
Subject: [PATCH 50/72] power: reset: tps65086: Allow building as a module

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/power/reset/Kconfig            | 2 +-
 drivers/power/reset/tps65086-restart.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index fff07b2bd77b..3271c49fe223 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -213,7 +213,7 @@ config POWER_RESET_ST
 	  Reset support for STMicroelectronics boards.
 
 config POWER_RESET_TPS65086
-	bool "TPS65086 restart driver"
+	tristate "TPS65086 restart driver"
 	depends on MFD_TPS65086
 	help
 	  This driver adds support for resetting the TPS65086 PMIC on restart.
diff --git a/drivers/power/reset/tps65086-restart.c b/drivers/power/reset/tps65086-restart.c
index 5ec819eac7da..78b89f745a3d 100644
--- a/drivers/power/reset/tps65086-restart.c
+++ b/drivers/power/reset/tps65086-restart.c
@@ -95,3 +95,4 @@ module_platform_driver(tps65086_restart_driver);
 
 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
 MODULE_DESCRIPTION("TPS65086 restart driver");
+MODULE_LICENSE("GPL v2");
-- 
2.41.0


From 1a9e4d0f6462447fe21e3b1a083ab8f3e616898f Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sat, 22 Jul 2023 15:59:02 +0200
Subject: [PATCH 51/72] usb: cdns3: starfive: Simplify mode init

The syscon regmap and offset to the USB mode register is only used at
probe time, so there is no need to store it in the device data. Just get
the regmap pointer in the cdns_mode_init() function where it is needed.
Also this function never uses the platform device, so just pass the
device pointer directly.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 drivers/usb/cdns3/cdns3-starfive.c | 51 ++++++++++++------------------
 1 file changed, 21 insertions(+), 30 deletions(-)

diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
index fc1f003b145d..e82e806af88a 100644
--- a/drivers/usb/cdns3/cdns3-starfive.c
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -34,46 +34,45 @@
 
 struct cdns_starfive {
 	struct device *dev;
-	struct regmap *stg_syscon;
 	struct reset_control *resets;
 	struct clk_bulk_data *clks;
 	int num_clks;
-	u32 stg_usb_mode;
 };
 
-static void cdns_mode_init(struct platform_device *pdev,
-			   struct cdns_starfive *data)
+static int cdns_mode_init(struct device *dev, struct cdns_starfive *data)
 {
+	struct regmap *syscon;
+	unsigned int usb_mode;
 	enum usb_dr_mode mode;
 
-	regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+	syscon = syscon_regmap_lookup_by_phandle_args(dev->of_node,
+						      "starfive,stg-syscon", 1, &usb_mode);
+	if (IS_ERR(syscon))
+		return dev_err_probe(dev, PTR_ERR(syscon),
+				     "Failed to parse starfive,stg-syscon\n");
+
+	regmap_update_bits(syscon, usb_mode,
 			   USB_MISC_CFG_MASK,
 			   USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
 
 	/* dr mode setting */
-	mode = usb_get_dr_mode(&pdev->dev);
+	mode = usb_get_dr_mode(dev);
 
 	switch (mode) {
 	case USB_DR_MODE_HOST:
-		regmap_update_bits(data->stg_syscon,
-				   data->stg_usb_mode,
-				   USB_STRAP_MASK,
-				   USB_STRAP_HOST);
-		regmap_update_bits(data->stg_syscon,
-				   data->stg_usb_mode,
-				   USB_SUSPENDM_MASK,
-				   USB_SUSPENDM_HOST);
+		regmap_update_bits(syscon, usb_mode, USB_STRAP_MASK, USB_STRAP_HOST);
+		regmap_update_bits(syscon, usb_mode, USB_SUSPENDM_MASK, USB_SUSPENDM_HOST);
 		break;
 
 	case USB_DR_MODE_PERIPHERAL:
-		regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
-				   USB_STRAP_MASK, USB_STRAP_DEVICE);
-		regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
-				   USB_SUSPENDM_MASK, 0);
+		regmap_update_bits(syscon, usb_mode, USB_STRAP_MASK, USB_STRAP_DEVICE);
+		regmap_update_bits(syscon, usb_mode, USB_SUSPENDM_MASK, 0);
 		break;
 	default:
 		break;
 	}
+
+	return 0;
 }
 
 static int cdns_clk_rst_init(struct cdns_starfive *data)
@@ -108,7 +107,6 @@ static int cdns_starfive_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct cdns_starfive *data;
-	unsigned int args;
 	int ret;
 
 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
@@ -117,16 +115,6 @@ static int cdns_starfive_probe(struct platform_device *pdev)
 
 	data->dev = dev;
 
-	data->stg_syscon =
-		syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
-						     "starfive,stg-syscon", 1, &args);
-
-	if (IS_ERR(data->stg_syscon))
-		return dev_err_probe(dev, PTR_ERR(data->stg_syscon),
-				     "Failed to parse starfive,stg-syscon\n");
-
-	data->stg_usb_mode = args;
-
 	data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
 	if (data->num_clks < 0)
 		return dev_err_probe(data->dev, -ENODEV,
@@ -137,7 +125,10 @@ static int cdns_starfive_probe(struct platform_device *pdev)
 		return dev_err_probe(data->dev, PTR_ERR(data->resets),
 				     "Failed to get resets");
 
-	cdns_mode_init(pdev, data);
+	ret = cdns_mode_init(dev, data);
+	if (ret)
+		return ret;
+
 	ret = cdns_clk_rst_init(data);
 	if (ret)
 		return ret;
-- 
2.41.0


From 7d6ec15582bedae35bea03475141510c816c8332 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sat, 22 Jul 2023 16:18:24 +0200
Subject: [PATCH 52/72] usb: cdns3: starfive: Don't store device backpointer

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 drivers/usb/cdns3/cdns3-starfive.c | 36 +++++++++++++-----------------
 1 file changed, 15 insertions(+), 21 deletions(-)

diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
index e82e806af88a..70e44cc7a5a6 100644
--- a/drivers/usb/cdns3/cdns3-starfive.c
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -33,7 +33,6 @@
 #define USB_REFCLK_MODE			BIT(23)
 
 struct cdns_starfive {
-	struct device *dev;
 	struct reset_control *resets;
 	struct clk_bulk_data *clks;
 	int num_clks;
@@ -49,7 +48,7 @@ static int cdns_mode_init(struct device *dev, struct cdns_starfive *data)
 						      "starfive,stg-syscon", 1, &usb_mode);
 	if (IS_ERR(syscon))
 		return dev_err_probe(dev, PTR_ERR(syscon),
-				     "Failed to parse starfive,stg-syscon\n");
+				     "failed to parse starfive,stg-syscon\n");
 
 	regmap_update_bits(syscon, usb_mode,
 			   USB_MISC_CFG_MASK,
@@ -75,18 +74,17 @@ static int cdns_mode_init(struct device *dev, struct cdns_starfive *data)
 	return 0;
 }
 
-static int cdns_clk_rst_init(struct cdns_starfive *data)
+static int cdns_clk_rst_init(struct device *dev, struct cdns_starfive *data)
 {
 	int ret;
 
 	ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
 	if (ret)
-		return dev_err_probe(data->dev, ret,
-				     "failed to enable clocks\n");
+		return dev_err_probe(dev, ret, "failed to enable clocks\n");
 
 	ret = reset_control_deassert(data->resets);
 	if (ret) {
-		dev_err(data->dev, "failed to reset clocks\n");
+		dev_err(dev, "failed to reset clocks\n");
 		goto err_clk_init;
 	}
 
@@ -97,7 +95,7 @@ static int cdns_clk_rst_init(struct cdns_starfive *data)
 	return ret;
 }
 
-static void cdns_clk_rst_deinit(struct cdns_starfive *data)
+static void cdns_clk_rst_deinit(struct device *dev, struct cdns_starfive *data)
 {
 	reset_control_assert(data->resets);
 	clk_bulk_disable_unprepare(data->num_clks, data->clks);
@@ -113,30 +111,26 @@ static int cdns_starfive_probe(struct platform_device *pdev)
 	if (!data)
 		return -ENOMEM;
 
-	data->dev = dev;
-
-	data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
+	data->num_clks = devm_clk_bulk_get_all(dev, &data->clks);
 	if (data->num_clks < 0)
-		return dev_err_probe(data->dev, -ENODEV,
-				     "Failed to get clocks\n");
+		return dev_err_probe(dev, -ENODEV, "failed to get clocks\n");
 
-	data->resets = devm_reset_control_array_get_exclusive(data->dev);
+	data->resets = devm_reset_control_array_get_exclusive(dev);
 	if (IS_ERR(data->resets))
-		return dev_err_probe(data->dev, PTR_ERR(data->resets),
-				     "Failed to get resets");
+		return dev_err_probe(dev, PTR_ERR(data->resets), "failed to get resets\n");
 
 	ret = cdns_mode_init(dev, data);
 	if (ret)
 		return ret;
 
-	ret = cdns_clk_rst_init(data);
+	ret = cdns_clk_rst_init(dev, data);
 	if (ret)
 		return ret;
 
 	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
 	if (ret) {
-		dev_err(dev, "Failed to create children\n");
-		cdns_clk_rst_deinit(data);
+		dev_err(dev, "failed to create children\n");
+		cdns_clk_rst_deinit(dev, data);
 		return ret;
 	}
 
@@ -167,7 +161,7 @@ static int cdns_starfive_remove(struct platform_device *pdev)
 
 	pm_runtime_disable(dev);
 	pm_runtime_put_noidle(dev);
-	cdns_clk_rst_deinit(data);
+	cdns_clk_rst_deinit(dev, data);
 	platform_set_drvdata(pdev, NULL);
 
 	return 0;
@@ -195,14 +189,14 @@ static int cdns_starfive_resume(struct device *dev)
 {
 	struct cdns_starfive *data = dev_get_drvdata(dev);
 
-	return cdns_clk_rst_init(data);
+	return cdns_clk_rst_init(dev, data);
 }
 
 static int cdns_starfive_suspend(struct device *dev)
 {
 	struct cdns_starfive *data = dev_get_drvdata(dev);
 
-	cdns_clk_rst_deinit(data);
+	cdns_clk_rst_deinit(dev, data);
 
 	return 0;
 }
-- 
2.41.0


From 2e48f02c5a39d951017657e4d60dfc19a51f109c Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sat, 22 Jul 2023 16:21:04 +0200
Subject: [PATCH 53/72] usb: cdns3: starfive: Add StarFive JH7100 support

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 drivers/usb/cdns3/cdns3-starfive.c | 46 ++++++++++++++++++------------
 1 file changed, 28 insertions(+), 18 deletions(-)

diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
index 70e44cc7a5a6..5039f2f4eb1e 100644
--- a/drivers/usb/cdns3/cdns3-starfive.c
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -20,17 +20,17 @@
 #include <linux/usb/otg.h>
 #include "core.h"
 
-#define USB_STRAP_HOST			BIT(17)
-#define USB_STRAP_DEVICE		BIT(18)
-#define USB_STRAP_MASK			GENMASK(18, 16)
+#define JH7110_STRAP_HOST		BIT(17)
+#define JH7110_STRAP_DEVICE		BIT(18)
+#define JH7110_STRAP_MASK		GENMASK(18, 16)
 
-#define USB_SUSPENDM_HOST		BIT(19)
-#define USB_SUSPENDM_MASK		BIT(19)
+#define JH7110_SUSPENDM_HOST		BIT(19)
+#define JH7110_SUSPENDM_MASK		BIT(19)
 
-#define USB_MISC_CFG_MASK		GENMASK(23, 20)
-#define USB_SUSPENDM_BYPS		BIT(20)
-#define USB_PLL_EN			BIT(22)
-#define USB_REFCLK_MODE			BIT(23)
+#define JH7110_MISC_CFG_MASK		GENMASK(23, 20)
+#define JH7110_SUSPENDM_BYPS		BIT(20)
+#define JH7110_PLL_EN			BIT(22)
+#define JH7110_REFCLK_MODE		BIT(23)
 
 struct cdns_starfive {
 	struct reset_control *resets;
@@ -38,7 +38,14 @@ struct cdns_starfive {
 	int num_clks;
 };
 
-static int cdns_mode_init(struct device *dev, struct cdns_starfive *data)
+typedef int (cdns_starfive_mode_init_t)(struct device *dev, struct cdns_starfive *data);
+
+static int cdns_jh7100_mode_init(struct device *dev, struct cdns_starfive *data)
+{
+	return 0;
+}
+
+static int cdns_jh7110_mode_init(struct device *dev, struct cdns_starfive *data)
 {
 	struct regmap *syscon;
 	unsigned int usb_mode;
@@ -51,21 +58,21 @@ static int cdns_mode_init(struct device *dev, struct cdns_starfive *data)
 				     "failed to parse starfive,stg-syscon\n");
 
 	regmap_update_bits(syscon, usb_mode,
-			   USB_MISC_CFG_MASK,
-			   USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
+			   JH7110_MISC_CFG_MASK,
+			   JH7110_SUSPENDM_BYPS | JH7110_PLL_EN | JH7110_REFCLK_MODE);
 
 	/* dr mode setting */
 	mode = usb_get_dr_mode(dev);
 
 	switch (mode) {
 	case USB_DR_MODE_HOST:
-		regmap_update_bits(syscon, usb_mode, USB_STRAP_MASK, USB_STRAP_HOST);
-		regmap_update_bits(syscon, usb_mode, USB_SUSPENDM_MASK, USB_SUSPENDM_HOST);
+		regmap_update_bits(syscon, usb_mode, JH7110_STRAP_MASK, JH7110_STRAP_HOST);
+		regmap_update_bits(syscon, usb_mode, JH7110_SUSPENDM_MASK, JH7110_SUSPENDM_HOST);
 		break;
 
 	case USB_DR_MODE_PERIPHERAL:
-		regmap_update_bits(syscon, usb_mode, USB_STRAP_MASK, USB_STRAP_DEVICE);
-		regmap_update_bits(syscon, usb_mode, USB_SUSPENDM_MASK, 0);
+		regmap_update_bits(syscon, usb_mode, JH7110_STRAP_MASK, JH7110_STRAP_DEVICE);
+		regmap_update_bits(syscon, usb_mode, JH7110_SUSPENDM_MASK, 0);
 		break;
 	default:
 		break;
@@ -105,6 +112,7 @@ static int cdns_starfive_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct cdns_starfive *data;
+	cdns_starfive_mode_init_t *mode_init;
 	int ret;
 
 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
@@ -119,7 +127,8 @@ static int cdns_starfive_probe(struct platform_device *pdev)
 	if (IS_ERR(data->resets))
 		return dev_err_probe(dev, PTR_ERR(data->resets), "failed to get resets\n");
 
-	ret = cdns_mode_init(dev, data);
+	mode_init = device_get_match_data(dev);
+	ret = mode_init(dev, data);
 	if (ret)
 		return ret;
 
@@ -210,7 +219,8 @@ static const struct dev_pm_ops cdns_starfive_pm_ops = {
 };
 
 static const struct of_device_id cdns_starfive_of_match[] = {
-	{ .compatible = "starfive,jh7110-usb", },
+	{ .compatible = "starfive,jh7100-usb", .data = cdns_jh7100_mode_init },
+	{ .compatible = "starfive,jh7110-usb", .data = cdns_jh7110_mode_init },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, cdns_starfive_of_match);
-- 
2.41.0


From 47a18d106805774e8c3a94ac4e978acb60b01f29 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sat, 22 Jul 2023 16:36:17 +0200
Subject: [PATCH 54/72] riscv: dts: starfive: Add JH7100 USB node

Add the device tree node for the USB 3.0 peripheral on the
StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 .../boot/dts/starfive/jh7100-common.dtsi      |  5 ++++
 arch/riscv/boot/dts/starfive/jh7100.dtsi      | 26 +++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index c3b3f5945036..6fc5a1bc9316 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -350,3 +350,8 @@ &uart3 {
 	pinctrl-0 = <&uart3_pins>;
 	status = "okay";
 };
+
+&usb3 {
+	dr_mode = "host";
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index c59c7be3800a..bfdaa5ac1a55 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -248,6 +248,32 @@ audrst: reset-controller@10490000 {
 			#reset-cells = <1>;
 		};
 
+		usb3: usb@104c0000 {
+			compatible = "starfive,jh7100-usb";
+			ranges = <0x0 0x0 0x104c0000 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&audclk JH7100_AUDCLK_USB_LPM>,
+			         <&audclk JH7100_AUDCLK_USB_STB>,
+			         <&clkgen JH7100_CLK_USB_AXI>,
+			         <&clkgen JH7100_CLK_USBNOC_AXI>;
+			clock-names = "lpm", "stb", "axi", "nocaxi";
+			resets = <&rstgen JH7100_RSTN_USB_AXI>,
+			         <&rstgen JH7100_RSTN_USBNOC_AXI>;
+			reset-names = "axi", "nocaxi";
+			status = "disabled";
+
+			usb_cdns3: usb@0 {
+				compatible = "cdns,usb3";
+				reg = <0x00000 0x10000>,
+				      <0x10000 0x10000>,
+				      <0x20000 0x10000>;
+				reg-names = "otg", "xhci", "dev";
+				interrupts = <44>, <52>, <43>;
+				interrupt-names = "host", "peripheral", "otg";
+			};
+		};
+
 		clkgen: clock-controller@11800000 {
 			compatible = "starfive,jh7100-clkgen";
 			reg = <0x0 0x11800000 0x0 0x10000>;
-- 
2.41.0


From a868ce336164a0651ba7cda51842577018b9afab Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Thu, 14 Oct 2021 20:35:43 +0200
Subject: [PATCH 55/72] clk: starfive: jh7100: Keep more clocks alive

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/clk/starfive/clk-starfive-jh7100.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 03f6f26a15d8..0342db24c27e 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -94,9 +94,9 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
 	JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
 	JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
 	JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
-	JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
-	JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
-	JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
+	JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", CLK_IGNORE_UNUSED, JH7100_CLK_DLA_BUS),
+	JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", CLK_IGNORE_UNUSED, JH7100_CLK_DLA_BUS),
+	JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", CLK_IGNORE_UNUSED, JH7100_CLK_APB1_BUS),
 	JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
 	JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
 	JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
@@ -163,8 +163,9 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
 	JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
 	JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
 	JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
-	JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
-	JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
+	JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", CLK_IGNORE_UNUSED, 8,
+		    JH7100_CLK_USBPHY_ROOTDIV),
+	JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", CLK_IGNORE_UNUSED, 32,
 		    JH7100_CLK_USBPHY_ROOTDIV),
 	JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 0, 2,
 		    JH7100_CLK_OSC_SYS,
@@ -183,11 +184,11 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
 	JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
 	JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
 	JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
-	JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
+	JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", CLK_IGNORE_UNUSED, 4, JH7100_CLK_VOUT_ROOT),
 	JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
 	JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
-	JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
-	JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
+	JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", CLK_IGNORE_UNUSED, JH7100_CLK_DISP_BUS),
+	JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", CLK_IGNORE_UNUSED, JH7100_CLK_DISP_BUS),
 	JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
 	JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
 	JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
@@ -223,7 +224,7 @@ static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
 	JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
 	JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
 	JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
-	JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
+	JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", CLK_IGNORE_UNUSED, JH7100_CLK_APB1_BUS),
 	JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
 	JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
 	JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
-- 
2.41.0


From bc94aa7cb88744cfc0dbc072b7aa4ab7adbbfc85 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Sat, 17 Jul 2021 21:50:38 +0200
Subject: [PATCH 56/72] pinctrl: starfive: Reset pinmux settings

Current u-boot doesn't seem to take into account that some GPIOs are
configured as inputs/outputs of certain peripherals on power-up. This
means it ends up configuring some GPIOs as inputs to more than one
peripheral which the documentation explicitly says is illegal. Similarly
it also ends up configuring more than one GPIO as output of the same
peripheral. While not explicitly mentioned by the documentation this
also seems like a bad idea.

The easiest way to remedy this mess is to just disconnect all GPIOs from
peripherals and have our pinmux configuration set everything up
properly. This, however, means that we'd disconnect the serial console
from its pins for a while, so add a device tree property to keep
certain GPIOs from being reset.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 .../pinctrl/starfive,jh7100-pinctrl.yaml      |  4 ++
 .../starfive/pinctrl-starfive-jh7100.c        | 66 +++++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
index f3258f2fd3a4..ce79d2ae3a32 100644
--- a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
@@ -88,6 +88,10 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     enum: [0, 1, 2, 3, 4, 5, 6]
 
+  starfive,keep-gpiomux:
+    description: Keep pinmux for these GPIOs from being reset at boot.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+
 required:
   - compatible
   - reg
diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
index 530fe340a9a1..6fe5e1e9baa9 100644
--- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
@@ -203,6 +203,10 @@ static u16 starfive_drive_strength_from_max_mA(u32 i)
 	return (clamp(i, 14U, 63U) - 14) / 7;
 }
 
+static bool keepmux;
+module_param(keepmux, bool, 0644);
+MODULE_PARM_DESC(keepmux, "Keep pinmux settings from previous boot stage");
+
 struct starfive_pinctrl {
 	struct gpio_chip gc;
 	struct pinctrl_gpio_range gpios;
@@ -1225,6 +1229,65 @@ static void starfive_disable_clock(void *data)
 	clk_disable_unprepare(data);
 }
 
+#define GPI_END (GPI_USB_OVER_CURRENT + 1)
+static void starfive_pinmux_reset(struct starfive_pinctrl *sfp)
+{
+	static const DECLARE_BITMAP(defaults, GPI_END) = {
+		BIT_MASK(GPI_I2C0_PAD_SCK_IN) |
+		BIT_MASK(GPI_I2C0_PAD_SDA_IN) |
+		BIT_MASK(GPI_I2C1_PAD_SCK_IN) |
+		BIT_MASK(GPI_I2C1_PAD_SDA_IN) |
+		BIT_MASK(GPI_I2C2_PAD_SCK_IN) |
+		BIT_MASK(GPI_I2C2_PAD_SDA_IN) |
+		BIT_MASK(GPI_I2C3_PAD_SCK_IN) |
+		BIT_MASK(GPI_I2C3_PAD_SDA_IN) |
+		BIT_MASK(GPI_SDIO0_PAD_CARD_DETECT_N) |
+
+		BIT_MASK(GPI_SDIO1_PAD_CARD_DETECT_N) |
+		BIT_MASK(GPI_SPI0_PAD_SS_IN_N) |
+		BIT_MASK(GPI_SPI1_PAD_SS_IN_N) |
+		BIT_MASK(GPI_SPI2_PAD_SS_IN_N) |
+		BIT_MASK(GPI_SPI2AHB_PAD_SS_N) |
+		BIT_MASK(GPI_SPI3_PAD_SS_IN_N),
+
+		BIT_MASK(GPI_UART0_PAD_SIN) |
+		BIT_MASK(GPI_UART1_PAD_SIN) |
+		BIT_MASK(GPI_UART2_PAD_SIN) |
+		BIT_MASK(GPI_UART3_PAD_SIN) |
+		BIT_MASK(GPI_USB_OVER_CURRENT)
+	};
+	DECLARE_BITMAP(keep, NR_GPIOS) = {};
+	struct device_node *np = sfp->gc.parent->of_node;
+	int len = of_property_count_u32_elems(np, "starfive,keep-gpiomux");
+	int i;
+
+	for (i = 0; i < len; i++) {
+		u32 gpio;
+
+		of_property_read_u32_index(np, "starfive,keep-gpiomux", i, &gpio);
+		if (gpio < NR_GPIOS)
+			set_bit(gpio, keep);
+	}
+
+	for (i = 0; i < NR_GPIOS; i++) {
+		if (test_bit(i, keep))
+			continue;
+
+		writel_relaxed(GPO_DISABLE, sfp->base + GPON_DOEN_CFG + 8 * i);
+		writel_relaxed(GPO_LOW,     sfp->base + GPON_DOUT_CFG + 8 * i);
+	}
+
+	for (i = 0; i < GPI_END; i++) {
+		void __iomem *reg = sfp->base + GPI_CFG_OFFSET + 4 * i;
+		u32 din = readl_relaxed(reg);
+
+		if (din >= 2 && din < (NR_GPIOS + 2) && test_bit(din - 2, keep))
+			continue;
+
+		writel_relaxed(test_bit(i, defaults), reg);
+	}
+}
+
 static int starfive_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -1286,6 +1349,9 @@ static int starfive_probe(struct platform_device *pdev)
 		writel(value, sfp->padctl + IO_PADSHARE_SEL);
 	}
 
+	if (!keepmux)
+		starfive_pinmux_reset(sfp);
+
 	value = readl(sfp->padctl + IO_PADSHARE_SEL);
 	switch (value) {
 	case 0:
-- 
2.41.0


From d73375992f93bde68aa512bd341b32ae4e7d82fe Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Mon, 7 Nov 2022 21:05:18 +0100
Subject: [PATCH 57/72] net: phy: motorcomm: Disable rgmii rx delay

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 drivers/net/phy/motorcomm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index 2fa5a90e073b..85b121f2736c 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c
@@ -1470,6 +1470,12 @@ static int yt8521_config_init(struct phy_device *phydev)
 		ret = ytphy_rgmii_clk_delay_config(phydev);
 		if (ret < 0)
 			goto err_restore_page;
+
+		/* disable rx delay */
+		ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG,
+				       YT8521_CCR_RXC_DLY_EN, 0);
+		if (ret < 0)
+			goto err_restore_page;
 	}
 
 	if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) {
-- 
2.41.0


From 4b1fafc6e99108eb55849da38ccbca6c370e34c8 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Date: Sat, 22 Jul 2023 18:50:49 +0200
Subject: [PATCH 58/72] usb: cdns3: starfive: Initialize JH7100 host mode

These settings are directly copied from StarFive's port of u-boot
for the JH7100:

  /* config strap */
  _SET_SYSCON_REG_SCFG_usb0_mode_strap(0x2);
  _SET_SYSCON_REG_SCFG_usb7_PLL_EN(0x1);
  _SET_SYSCON_REG_SCFG_usb7_U3_EQ_EN(0x1);
  _SET_SYSCON_REG_SCFG_usb7_U3_SSRX_SEL(0x1);
  _SET_SYSCON_REG_SCFG_usb7_U3_SSTX_SEL(0x1);
  _SET_SYSCON_REG_SCFG_usb3_utmi_iddig(0x1);

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 arch/riscv/boot/dts/starfive/jh7100.dtsi |  6 ++++
 drivers/usb/cdns3/cdns3-starfive.c       | 43 ++++++++++++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index bfdaa5ac1a55..ad03dabcddd0 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -248,6 +248,11 @@ audrst: reset-controller@10490000 {
 			#reset-cells = <1>;
 		};
 
+		sysaudio: syscon@104a0000 {
+			compatible = "starfive,jh7100-sysaudio", "syscon";
+			reg = <0x0 0x104a0000 0x0 0x10000>;
+		};
+
 		usb3: usb@104c0000 {
 			compatible = "starfive,jh7100-usb";
 			ranges = <0x0 0x0 0x104c0000 0x100000>;
@@ -261,6 +266,7 @@ usb3: usb@104c0000 {
 			resets = <&rstgen JH7100_RSTN_USB_AXI>,
 			         <&rstgen JH7100_RSTN_USBNOC_AXI>;
 			reset-names = "axi", "nocaxi";
+			starfive,syscon = <&sysaudio>;
 			status = "disabled";
 
 			usb_cdns3: usb@0 {
diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
index 5039f2f4eb1e..f3c48cb51978 100644
--- a/drivers/usb/cdns3/cdns3-starfive.c
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -20,6 +20,19 @@
 #include <linux/usb/otg.h>
 #include "core.h"
 
+#define JH7100_USB0			0x20
+#define JH7100_USB0_MODE_STRAP_MASK	GENMASK(2, 0)
+#define JH7100_USB0_MODE_STRAP_HOST	2
+
+#define JH7100_USB3			0x2c
+#define JH7100_USB3_UTMI_IDDIG		BIT(21)
+
+#define JH7100_USB7			0x3c
+#define JH7100_USB7_SSRX_SEL		BIT(18)
+#define JH7100_USB7_SSTX_SEL		BIT(19)
+#define JH7100_USB7_PLL_EN		BIT(23)
+#define JH7100_USB7_EQ_EN		BIT(25)
+
 #define JH7110_STRAP_HOST		BIT(17)
 #define JH7110_STRAP_DEVICE		BIT(18)
 #define JH7110_STRAP_MASK		GENMASK(18, 16)
@@ -42,6 +55,36 @@ typedef int (cdns_starfive_mode_init_t)(struct device *dev, struct cdns_starfive
 
 static int cdns_jh7100_mode_init(struct device *dev, struct cdns_starfive *data)
 {
+	struct regmap *syscon;
+	enum usb_dr_mode mode;
+
+	syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "starfive,syscon");
+	if (IS_ERR(syscon))
+		return dev_err_probe(dev, PTR_ERR(syscon),
+				     "failed to get starfive,syscon\n");
+
+	/* dr mode setting */
+	mode = usb_get_dr_mode(dev);
+
+	switch (mode) {
+	case USB_DR_MODE_HOST:
+		regmap_update_bits(syscon, JH7100_USB0,
+				   JH7100_USB0_MODE_STRAP_MASK, JH7100_USB0_MODE_STRAP_HOST);
+		regmap_update_bits(syscon, JH7100_USB7,
+				   JH7100_USB7_PLL_EN, JH7100_USB7_PLL_EN);
+		regmap_update_bits(syscon, JH7100_USB7,
+				   JH7100_USB7_EQ_EN, JH7100_USB7_EQ_EN);
+		regmap_update_bits(syscon, JH7100_USB7,
+				   JH7100_USB7_SSRX_SEL, JH7100_USB7_SSRX_SEL);
+		regmap_update_bits(syscon, JH7100_USB7,
+				   JH7100_USB7_SSTX_SEL, JH7100_USB7_SSTX_SEL);
+		regmap_update_bits(syscon, JH7100_USB3,
+				   JH7100_USB3_UTMI_IDDIG, JH7100_USB3_UTMI_IDDIG);
+		break;
+	default:
+		break;
+	}
+
 	return 0;
 }
 
-- 
2.41.0


From b007235b86b9a29e431a668128a9c519a59cf114 Mon Sep 17 00:00:00 2001
From: Matteo Croce <technoboy85@gmail.com>
Date: Fri, 21 May 2021 03:26:38 +0200
Subject: [PATCH 59/72] net: stmmac: use GFP_DMA32

Signed-off-by: Matteo Croce <mcroce@microsoft.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 4727f7be4f86..8c6c03ad88eb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1441,7 +1441,7 @@ static int stmmac_init_rx_buffers(struct stmmac_priv *priv,
 {
 	struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
 	struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
-	gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
+	gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32);
 
 	if (priv->dma_cap.host_dma_width <= 32)
 		gfp |= GFP_DMA32;
@@ -4603,7 +4603,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
 	struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
 	int dirty = stmmac_rx_dirty(priv, queue);
 	unsigned int entry = rx_q->dirty_rx;
-	gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
+	gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN | GFP_DMA32);
 
 	if (priv->dma_cap.host_dma_width <= 32)
 		gfp |= GFP_DMA32;
-- 
2.41.0


From 3d2e22395d9a513cbec0a651b05309205a686831 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Thu, 14 Oct 2021 20:56:54 +0200
Subject: [PATCH 60/72] serial: 8250_dw: Add starfive,jh7100-hsuart compatible

This adds a compatible for the high speed UARTs on the StarFive JH7100
RISC-V SoC. Just like the regular uarts we also need to keep the input
clocks at their default rate and rely only on the divisor in the UART.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/tty/serial/8250/8250_dw.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 7db51781289e..b749f2805df7 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -777,6 +777,7 @@ static const struct of_device_id dw8250_of_match[] = {
 	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
 	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
 	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
+	{ .compatible = "starfive,jh7100-hsuart", .data = &dw8250_starfive_jh7100_data },
 	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
 	{ /* Sentinel */ }
 };
-- 
2.41.0


From cb57e845c5ac094e10413e4bd9820832cd087cff Mon Sep 17 00:00:00 2001
From: Samin Guo <samin.guo@starfivetech.com>
Date: Fri, 8 Jan 2021 03:11:04 +0800
Subject: [PATCH 61/72] drivers/tty/serial/8250: update driver for JH7100

---
 drivers/tty/serial/8250/8250_port.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 16aeb1420137..d9d8e1eab645 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -72,8 +72,16 @@ static const struct serial8250_config uart_config[] = {
 	},
 	[PORT_16550] = {
 		.name		= "16550",
+#ifdef CONFIG_SOC_STARFIVE
+		.fifo_size	= 16,
+		.tx_loadsz	= 16,
+		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
+		.rxtrig_bytes	= {1, 4, 8, 14},
+		.flags		= UART_CAP_FIFO,
+#else
 		.fifo_size	= 1,
 		.tx_loadsz	= 1,
+#endif
 	},
 	[PORT_16550A] = {
 		.name		= "16550A",
-- 
2.41.0


From b006979676150e9ec7953eee17ebf23c380ec840 Mon Sep 17 00:00:00 2001
From: Huan Feng <huan.feng@starfivetech.com>
Date: Fri, 8 Jan 2021 03:35:42 +0800
Subject: [PATCH 62/72] hwrng: Add StarFive JH7100 Random Number Generator
 driver

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/char/hw_random/Kconfig            |  13 ++
 drivers/char/hw_random/Makefile           |   1 +
 drivers/char/hw_random/starfive-vic-rng.c | 256 ++++++++++++++++++++++
 drivers/char/hw_random/starfive-vic-rng.h | 167 ++++++++++++++
 4 files changed, 437 insertions(+)
 create mode 100644 drivers/char/hw_random/starfive-vic-rng.c
 create mode 100644 drivers/char/hw_random/starfive-vic-rng.h

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index e0b3786ca51b..4e55e8ccc804 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -322,6 +322,19 @@ config HW_RANDOM_POWERNV
 
 	  If unsure, say Y.
 
+config HW_RANDOM_STARFIVE_VIC
+	tristate "Starfive VIC Random Number Generator support"
+	depends on HW_RANDOM && (SOC_STARFIVE || COMPILE_TEST)
+	default SOC_STARFIVE
+	help
+	  This driver provides kernel-side support for the Random Number
+	  Generator hardware found on Starfive VIC SoC.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called starfive-vic-rng.
+
+	  If unsure, say Y.
+
 config HW_RANDOM_HISI
 	tristate "Hisilicon Random Number Generator support"
 	depends on HW_RANDOM && ARCH_HISI
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 32549a1186dc..146da12a69e1 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
 obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
 obj-$(CONFIG_HW_RANDOM_PSERIES) += pseries-rng.o
 obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o
+obj-$(CONFIG_HW_RANDOM_STARFIVE_VIC)	+= starfive-vic-rng.o
 obj-$(CONFIG_HW_RANDOM_HISI)	+= hisi-rng.o
 obj-$(CONFIG_HW_RANDOM_HISTB) += histb-rng.o
 obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
diff --git a/drivers/char/hw_random/starfive-vic-rng.c b/drivers/char/hw_random/starfive-vic-rng.c
new file mode 100644
index 000000000000..1e003b755a52
--- /dev/null
+++ b/drivers/char/hw_random/starfive-vic-rng.c
@@ -0,0 +1,256 @@
+/*
+ ******************************************************************************
+ * @file  starfive-vic-rng.c
+ * @author  StarFive Technology
+ * @version  V1.0
+ * @date  08/13/2020
+ * @brief
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
+ */
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/hw_random.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/random.h>
+
+#include "starfive-vic-rng.h"
+
+#define to_vic_rng(p)	container_of(p, struct vic_rng, rng)
+
+struct vic_rng {
+	struct device	*dev;
+	void __iomem	*base;
+	struct hwrng	rng;
+};
+
+static inline void vic_wait_till_idle(struct vic_rng *hrng)
+{
+	while(readl(hrng->base + VIC_STAT) & VIC_STAT_BUSY)
+		;
+}
+
+static inline void vic_rng_irq_mask_clear(struct vic_rng *hrng)
+{
+	// clear register: ISTAT
+	u32 data = readl(hrng->base + VIC_ISTAT);
+	writel(data, hrng->base + VIC_ISTAT);
+	writel(0, hrng->base + VIC_ALARM);
+}
+
+static int vic_trng_cmd(struct vic_rng *hrng, u32 cmd) {
+	int res = 0;
+	// wait till idle
+	vic_wait_till_idle(hrng);
+	switch (cmd) {
+	case VIC_CTRL_CMD_NOP:
+	case VIC_CTRL_CMD_GEN_NOISE:
+	case VIC_CTRL_CMD_GEN_NONCE:
+	case VIC_CTRL_CMD_CREATE_STATE:
+	case VIC_CTRL_CMD_RENEW_STATE:
+	case VIC_CTRL_CMD_REFRESH_ADDIN:
+	case VIC_CTRL_CMD_GEN_RANDOM:
+	case VIC_CTRL_CMD_ADVANCE_STATE:
+	case VIC_CTRL_CMD_KAT:
+	case VIC_CTRL_CMD_ZEROIZE:
+		writel(cmd, hrng->base + VIC_CTRL);
+		break;
+	default:
+		res = -1;
+		break;
+	}
+
+	return res;
+}
+
+static int vic_rng_init(struct hwrng *rng)
+{
+	struct vic_rng *hrng = to_vic_rng(rng);
+
+	// wait till idle
+
+	// clear register: ISTAT
+	vic_rng_irq_mask_clear(hrng);
+
+	// set mission mode
+	writel(VIC_SMODE_SECURE_EN(1), hrng->base + VIC_SMODE);
+
+	vic_trng_cmd(hrng, VIC_CTRL_CMD_GEN_NOISE);
+	vic_wait_till_idle(hrng);
+
+	// set interrupt
+	writel(VIC_IE_ALL, hrng->base + VIC_IE);
+
+	// zeroize
+	vic_trng_cmd(hrng, VIC_CTRL_CMD_ZEROIZE);
+
+	vic_wait_till_idle(hrng);
+
+	return 0;
+}
+
+static irqreturn_t vic_rng_irq(int irq, void *priv)
+{
+	u32 status, val;
+	struct vic_rng *hrng = (struct vic_rng *)priv;
+
+	/*
+	 * clearing the interrupt will also clear the error register
+	 * read error and status before clearing
+	 */
+	status = readl(hrng->base + VIC_ISTAT);
+
+	if (status & VIC_ISTAT_ALARMS) {
+		writel(VIC_ISTAT_ALARMS, hrng->base + VIC_ISTAT);
+		val = readl(hrng->base + VIC_ALARM);
+		if (val & VIC_ALARM_ILLEGAL_CMD_SEQ) {
+			writel(VIC_ALARM_ILLEGAL_CMD_SEQ, hrng->base + VIC_ALARM);
+			//dev_info(hrng->dev, "ILLEGAL CMD SEQ: LAST_CMD=0x%x\r\n",
+			//VIC_STAT_LAST_CMD(readl(hrng->base + VIC_STAT)));
+		} else {
+			dev_info(hrng->dev, "Failed test: %x\r\n", val);
+		}
+	}
+
+	if (status & VIC_ISTAT_ZEROIZE) {
+		writel(VIC_ISTAT_ZEROIZE, hrng->base + VIC_ISTAT);
+		//dev_info(hrng->dev, "zeroized\r\n");
+	}
+
+	if (status & VIC_ISTAT_KAT_COMPLETE) {
+		writel(VIC_ISTAT_KAT_COMPLETE, hrng->base + VIC_ISTAT);
+		//dev_info(hrng->dev, "kat_completed\r\n");
+	}
+
+	if (status & VIC_ISTAT_NOISE_RDY) {
+		writel(VIC_ISTAT_NOISE_RDY, hrng->base + VIC_ISTAT);
+		//dev_info(hrng->dev, "noise_rdy\r\n");
+	}
+
+	if (status & VIC_ISTAT_DONE) {
+		writel(VIC_ISTAT_DONE, hrng->base + VIC_ISTAT);
+		//dev_info(hrng->dev, "done\r\n");
+		/*
+		if (VIC_STAT_LAST_CMD(readl(hrng->base + VIC_STAT)) ==
+		    VIC_CTRL_CMD_GEN_RANDOM) {
+			dev_info(hrng->dev, "Need Update Buffer\r\n");
+		}
+		*/
+	}
+	vic_rng_irq_mask_clear(hrng);
+
+	return IRQ_HANDLED;
+}
+
+static void vic_rng_cleanup(struct hwrng *rng)
+{
+	struct vic_rng *hrng = to_vic_rng(rng);
+
+	writel(0, hrng->base + VIC_CTRL);
+}
+
+static int vic_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+	struct vic_rng *hrng = to_vic_rng(rng);
+
+	vic_trng_cmd(hrng, VIC_CTRL_CMD_ZEROIZE);
+	vic_trng_cmd(hrng, VIC_CTRL_CMD_GEN_NOISE);
+	vic_trng_cmd(hrng, VIC_CTRL_CMD_CREATE_STATE);
+
+	vic_wait_till_idle(hrng);
+	max = min_t(size_t, max, (VIC_RAND_LEN * 4));
+
+	writel(0x0, hrng->base + VIC_MODE);
+	vic_trng_cmd(hrng, VIC_CTRL_CMD_GEN_RANDOM);
+
+	vic_wait_till_idle(hrng);
+	memcpy_fromio(buf, hrng->base + VIC_RAND0, max);
+	vic_trng_cmd(hrng, VIC_CTRL_CMD_ZEROIZE);
+
+	vic_wait_till_idle(hrng);
+	return max;
+}
+
+static int vic_rng_probe(struct platform_device *pdev)
+{
+	int ret;
+	int irq;
+	struct vic_rng *rng;
+	struct resource *res;
+
+	rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
+	if (!rng){
+		return -ENOMEM;
+	}
+
+	platform_set_drvdata(pdev, rng);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	rng->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(rng->base)){
+		return PTR_ERR(rng->base);
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq <= 0) {
+		dev_err(&pdev->dev, "Couldn't get irq %d\n", irq);
+		return irq;
+	}
+
+	ret = devm_request_irq(&pdev->dev, irq, vic_rng_irq, 0, pdev->name,
+				(void *)rng);
+	if (ret) {
+		dev_err(&pdev->dev, "Can't get interrupt working.\n");
+		return ret;
+	}
+
+	rng->rng.name = pdev->name;
+	rng->rng.init = vic_rng_init;
+	rng->rng.cleanup = vic_rng_cleanup;
+	rng->rng.read = vic_rng_read;
+
+	rng->dev = &pdev->dev;
+
+	ret = devm_hwrng_register(&pdev->dev, &rng->rng);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register hwrng\n");
+		return ret;
+	}
+
+	dev_info(&pdev->dev, "Initialized\n");
+
+	return 0;
+}
+
+static const struct of_device_id vic_rng_dt_ids[] = {
+	{ .compatible = "starfive,vic-rng" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, vic_rng_dt_ids);
+
+static struct platform_driver vic_rng_driver = {
+	.probe		= vic_rng_probe,
+	.driver		= {
+		.name		= "vic-rng",
+		.of_match_table	= vic_rng_dt_ids,
+	},
+};
+
+module_platform_driver(vic_rng_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Huan Feng <huan.feng@starfivetech.com>");
+MODULE_DESCRIPTION("Starfive VIC random number generator driver");
diff --git a/drivers/char/hw_random/starfive-vic-rng.h b/drivers/char/hw_random/starfive-vic-rng.h
new file mode 100644
index 000000000000..b3bbabde0cfb
--- /dev/null
+++ b/drivers/char/hw_random/starfive-vic-rng.h
@@ -0,0 +1,167 @@
+/*
+ ******************************************************************************
+ * @file  starfive-vic-rng.h
+ * @author  StarFive Technology
+ * @version  V1.0
+ * @date  08/13/2020
+ * @brief
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
+ */
+
+#define VIC_CTRL		0x00
+#define VIC_MODE		0x04
+#define VIC_SMODE		0x08
+#define VIC_STAT		0x0C
+#define VIC_IE			0x10
+#define VIC_ISTAT		0x14
+#define VIC_ALARM		0x18
+#define VIC_BUILD_ID		0x1C
+#define VIC_FEATURES		0x20
+#define VIC_RAND0		0x24
+#define VIC_NPA_DATA0		0x34
+#define VIC_SEED0		0x74
+#define VIC_IA_RDATA		0xA4
+#define VIC_IA_WDATA		0xA8
+#define VIC_IA_ADDR		0xAC
+#define VIC_IA_CMD		0xB0
+
+/* CTRL */
+#define VIC_CTRL_CMD_NOP		0
+#define VIC_CTRL_CMD_GEN_NOISE		1
+#define VIC_CTRL_CMD_GEN_NONCE		2
+#define VIC_CTRL_CMD_CREATE_STATE	3
+#define VIC_CTRL_CMD_RENEW_STATE	4
+#define VIC_CTRL_CMD_REFRESH_ADDIN	5
+#define VIC_CTRL_CMD_GEN_RANDOM		6
+#define VIC_CTRL_CMD_ADVANCE_STATE	7
+#define VIC_CTRL_CMD_KAT		8
+#define VIC_CTRL_CMD_ZEROIZE		15
+
+/* MODE */
+#define _VIC_MODE_ADDIN_PRESENT		4
+#define _VIC_MODE_PRED_RESIST		3
+#define _VIC_MODE_KAT_SEL		2
+#define _VIC_MODE_KAT_VEC		1
+#define _VIC_MODE_SEC_ALG		0
+
+#define VIC_MODE_ADDIN_PRESENT	(1UL << _VIC_MODE_ADDIN_PRESENT)
+#define VIC_MODE_PRED_RESIST	(1UL << _VIC_MODE_PRED_RESIST)
+#define VIC_MODE_KAT_SEL	(1UL << _VIC_MODE_KAT_SEL)
+#define VIC_MODE_KAT_VEC	(1UL << _VIC_MODE_KAT_VEC)
+#define VIC_MODE_SEC_ALG	(1UL << _VIC_MODE_SEC_ALG)
+
+/* SMODE */
+#define _VIC_SMODE_MAX_REJECTS	2
+#define _VIC_SMODE_SECURE_EN	1
+#define _VIC_SMODE_NONCE	0
+
+#define VIC_SMODE_MAX_REJECTS(x)	((x) << _VIC_SMODE_MAX_REJECTS)
+#define VIC_SMODE_SECURE_EN(x)		((x) << _VIC_SMODE_SECURE_EN)
+#define VIC_SMODE_NONCE			(1UL << _VIC_SMODE_NONCE)
+
+/* STAT */
+#define _VIC_STAT_BUSY		31
+#define _VIC_STAT_DRBG_STATE	7
+#define _VIC_STAT_SECURE	6
+#define _VIC_STAT_NONCE_MODE	5
+#define _VIC_STAT_SEC_ALG	4
+#define _VIC_STAT_LAST_CMD	0
+
+#define VIC_STAT_BUSY		(1UL << _VIC_STAT_BUSY)
+#define VIC_STAT_DRBG_STATE	(1UL << _VIC_STAT_DRBG_STATE)
+#define VIC_STAT_SECURE		(1UL << _VIC_STAT_SECURE)
+#define VIC_STAT_NONCE_MODE	(1UL << _VIC_STAT_NONCE_MODE)
+#define VIC_STAT_SEC_ALG	(1UL << _VIC_STAT_SEC_ALG)
+#define VIC_STAT_LAST_CMD(x)	(((x) >> _VIC_STAT_LAST_CMD) & 0xF)
+
+/* IE */
+#define _VIC_IE_GLBL		31
+#define _VIC_IE_DONE		4
+#define _VIC_IE_ALARMS		3
+#define _VIC_IE_NOISE_RDY	2
+#define _VIC_IE_KAT_COMPLETE	1
+#define _VIC_IE_ZEROIZE		0
+
+#define VIC_IE_GLBL		(1UL << _VIC_IE_GLBL)
+#define VIC_IE_DONE		(1UL << _VIC_IE_DONE)
+#define VIC_IE_ALARMS		(1UL << _VIC_IE_ALARMS)
+#define VIC_IE_NOISE_RDY	(1UL << _VIC_IE_NOISE_RDY)
+#define VIC_IE_KAT_COMPLETE	(1UL << _VIC_IE_KAT_COMPLETE)
+#define VIC_IE_ZEROIZE		(1UL << _VIC_IE_ZEROIZE)
+#define VIC_IE_ALL		(VIC_IE_GLBL | VIC_IE_DONE | VIC_IE_ALARMS | \
+				 VIC_IE_NOISE_RDY | VIC_IE_KAT_COMPLETE | VIC_IE_ZEROIZE)
+
+/* ISTAT */
+#define _VIC_ISTAT_DONE		4
+#define _VIC_ISTAT_ALARMS	3
+#define _VIC_ISTAT_NOISE_RDY	2
+#define _VIC_ISTAT_KAT_COMPLETE	1
+#define _VIC_ISTAT_ZEROIZE	0
+
+#define VIC_ISTAT_DONE		(1UL << _VIC_ISTAT_DONE)
+#define VIC_ISTAT_ALARMS	(1UL << _VIC_ISTAT_ALARMS)
+#define VIC_ISTAT_NOISE_RDY	(1UL << _VIC_ISTAT_NOISE_RDY)
+#define VIC_ISTAT_KAT_COMPLETE	(1UL << _VIC_ISTAT_KAT_COMPLETE)
+#define VIC_ISTAT_ZEROIZE	(1UL << _VIC_ISTAT_ZEROIZE)
+
+/* ALARMS */
+#define VIC_ALARM_ILLEGAL_CMD_SEQ			(1UL << 4)
+#define VIC_ALARM_FAILED_TEST_ID_OK			0
+#define VIC_ALARM_FAILED_TEST_ID_KAT_STAT		1
+#define VIC_ALARM_FAILED_TEST_ID_KAT			2
+#define VIC_ALARM_FAILED_TEST_ID_MONOBIT		3
+#define VIC_ALARM_FAILED_TEST_ID_RUN			4
+#define VIC_ALARM_FAILED_TEST_ID_LONGRUN		5
+#define VIC_ALARM_FAILED_TEST_ID_AUTOCORRELATION	6
+#define VIC_ALARM_FAILED_TEST_ID_POKER			7
+#define VIC_ALARM_FAILED_TEST_ID_REPETITION_COUNT	8
+#define VIC_ALARM_FAILED_TEST_ID_ADAPATIVE_PROPORTION	9
+
+/* BUILD_ID */
+#define VIC_BUILD_ID_STEPPING(x)		(((x) >> 28) & 0xF)
+#define VIC_BUILD_ID_EPN(x)			((x) & 0xFFFF)
+
+/* FEATURES */
+#define VIC_FEATURES_AES_256(x)			(((x) >> 9) & 1)
+#define VIC_FEATURES_EXTRA_PS_PRESENT(x)	(((x) >> 8) & 1)
+#define VIC_FEATURES_DIAG_LEVEL_NS(x)		(((x) >> 7) & 1)
+#define VIC_FEATURES_DIAG_LEVEL_CLP800(x)	(((x) >> 4) & 7)
+#define VIC_FEATURES_DIAG_LEVEL_ST_HLT(x)	(((x) >> 1) & 7)
+#define VIC_FEATURES_SECURE_RST_STATE(x)	((x) & 1)
+
+/* IA_CMD */
+#define VIC_IA_CMD_GO			(1UL << 31)
+#define VIC_IA_CMD_WR			(1)
+
+#define _VIC_SMODE_MAX_REJECTS_MASK	255UL
+#define _VIC_SMODE_SECURE_EN_MASK	1UL
+#define _VIC_SMODE_NONCE_MASK		1UL
+#define _VIC_MODE_SEC_ALG_MASK		1UL
+#define _VIC_MODE_ADDIN_PRESENT_MASK	1UL
+#define _VIC_MODE_PRED_RESIST_MASK	1UL
+
+#define VIC_SMODE_SET_MAX_REJECTS(y, x)	(((y) & ~(_VIC_SMODE_MAX_REJECTS_MASK << _VIC_SMODE_MAX_REJECTS)) | ((x) << _VIC_SMODE_MAX_REJECTS))
+#define VIC_SMODE_SET_SECURE_EN(y, x)	(((y) & ~(_VIC_SMODE_SECURE_EN_MASK   << _VIC_SMODE_SECURE_EN))   | ((x) << _VIC_SMODE_SECURE_EN))
+#define VIC_SMODE_SET_NONCE(y, x)	(((y) & ~(_VIC_SMODE_NONCE_MASK       << _VIC_SMODE_NONCE))       | ((x) << _VIC_SMODE_NONCE))
+#define VIC_SMODE_GET_MAX_REJECTS(x)	(((x) >> _VIC_SMODE_MAX_REJECTS) & _VIC_SMODE_MAX_REJECTS_MASK)
+#define VIC_SMODE_GET_SECURE_EN(x)	(((x) >> _VIC_SMODE_SECURE_EN)   & _VIC_SMODE_SECURE_EN_MASK)
+#define VIC_SMODE_GET_NONCE(x)		(((x) >> _VIC_SMODE_NONCE)       & _VIC_SMODE_NONCE_MASK)
+
+#define VIC_MODE_SET_SEC_ALG(y, x)	(((y) & ~(_VIC_MODE_SEC_ALG_MASK       << _VIC_MODE_SEC_ALG))	| ((x) << _VIC_MODE_SEC_ALG))
+#define VIC_MODE_SET_PRED_RESIST(y, x)	(((y) & ~(_VIC_MODE_PRED_RESIST_MASK   << _VIC_MODE_PRED_RESIST))    | ((x) << _VIC_MODE_PRED_RESIST))
+#define VIC_MODE_SET_ADDIN_PRESENT(y, x) (((y) & ~(_VIC_MODE_ADDIN_PRESENT_MASK << _VIC_MODE_ADDIN_PRESENT))  | ((x) << _VIC_MODE_ADDIN_PRESENT))
+#define VIC_MODE_GET_SEC_ALG(x)		(((x) >> _VIC_MODE_SEC_ALG)       & _VIC_MODE_SEC_ALG_MASK)
+#define VIC_MODE_GET_PRED_RESIST(x)	(((x) >> _VIC_MODE_PRED_RESIST)   & _VIC_MODE_PRED_RESIST_MASK)
+#define VIC_MODE_GET_ADDIN_PRESENT(x)	(((x) >> _VIC_MODE_ADDIN_PRESENT) & _VIC_MODE_ADDIN_PRESENT_MASK)
+
+#define VIC_RAND_LEN 4
-- 
2.41.0


From 1bbfa79acc5c94b9703fd310caf168bbc30d1137 Mon Sep 17 00:00:00 2001
From: Chenjieqin <Jessica.Chen@starfivetech.com>
Date: Fri, 8 Jan 2021 03:56:54 +0800
Subject: [PATCH 63/72] pwm: sifive-ptc: Add SiFive PWM PTC driver

yiming.li: clear CNTR of PWM after setting period & duty_cycle
Emil: cleanups, clock, reset and div_u64

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/pwm/Kconfig          |  11 ++
 drivers/pwm/Makefile         |   1 +
 drivers/pwm/pwm-sifive-ptc.c | 260 +++++++++++++++++++++++++++++++++++
 3 files changed, 272 insertions(+)
 create mode 100644 drivers/pwm/pwm-sifive-ptc.c

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 6210babb0741..8d981b96346b 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -537,6 +537,17 @@ config PWM_SIFIVE
 	  To compile this driver as a module, choose M here: the module
 	  will be called pwm-sifive.
 
+config PWM_SIFIVE_PTC
+	tristate "SiFive PWM PTC support"
+	depends on SOC_SIFIVE || SOC_STARFIVE || COMPILE_TEST
+	depends on OF
+	depends on COMMON_CLK
+	help
+	  Generic PWM framework driver for SiFive SoCs.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called pwm-sifive-ptc.
+
 config PWM_SL28CPLD
 	tristate "Kontron sl28cpld PWM support"
 	depends on MFD_SL28CPLD || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index c822389c2a24..785bdd5c82c1 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_PWM_ROCKCHIP)	+= pwm-rockchip.o
 obj-$(CONFIG_PWM_RZ_MTU3)	+= pwm-rz-mtu3.o
 obj-$(CONFIG_PWM_SAMSUNG)	+= pwm-samsung.o
 obj-$(CONFIG_PWM_SIFIVE)	+= pwm-sifive.o
+obj-$(CONFIG_PWM_SIFIVE_PTC)	+= pwm-sifive-ptc.o
 obj-$(CONFIG_PWM_SL28CPLD)	+= pwm-sl28cpld.o
 obj-$(CONFIG_PWM_SPEAR)		+= pwm-spear.o
 obj-$(CONFIG_PWM_SPRD)		+= pwm-sprd.o
diff --git a/drivers/pwm/pwm-sifive-ptc.c b/drivers/pwm/pwm-sifive-ptc.c
new file mode 100644
index 000000000000..2bfc4d9f4932
--- /dev/null
+++ b/drivers/pwm/pwm-sifive-ptc.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2018 SiFive, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2, as published by
+ * the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/pwm/pwm.h>
+
+/* max channel of pwm */
+#define MAX_PWM				8
+
+/* PTC Register offsets */
+#define REG_RPTC_CNTR			0x0
+#define REG_RPTC_HRC			0x4
+#define REG_RPTC_LRC			0x8
+#define REG_RPTC_CTRL			0xC
+
+/* Bit for PWM clock */
+#define BIT_PWM_CLOCK_EN		31
+
+/* Bit for clock gen soft reset */
+#define BIT_CLK_GEN_SOFT_RESET		13
+
+#define NS_1				1000000000U
+
+/* Access PTC register (cntr hrc lrc and ctrl), need to replace PWM_BASE_ADDR */
+#define REG_PTC_BASE_ADDR_SUB(base, N)	\
+	((base) + (((N) > 3) ? (((N) - 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
+#define REG_PTC_RPTC_CNTR(base, N)	(REG_PTC_BASE_ADDR_SUB(base, N))
+#define REG_PTC_RPTC_HRC(base, N)	(REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
+#define REG_PTC_RPTC_LRC(base, N)	(REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
+#define REG_PTC_RPTC_CTRL(base, N)	(REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
+
+/* pwm ptc device */
+struct sifive_pwm_ptc_device {
+	struct pwm_chip	chip;
+	struct clk	*clk;
+	void __iomem	*regs;
+};
+
+static inline struct sifive_pwm_ptc_device *chip_to_sifive_ptc(struct pwm_chip *c)
+{
+	return container_of(c, struct sifive_pwm_ptc_device, chip);
+}
+
+static int sifive_pwm_ptc_get_state(struct pwm_chip *chip, struct pwm_device *dev,
+				    struct pwm_state *state)
+{
+	struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
+	u32 data_lrc;
+	u32 data_hrc;
+	u32 pwm_clk_ns = 0;
+
+	/* get lrc and hrc data from registe */
+	data_lrc = ioread32(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
+	data_hrc = ioread32(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
+
+	/* how many ns does apb clock elapse */
+	pwm_clk_ns = NS_1 / clk_get_rate(pwm->clk);
+
+	/* pwm period(ns) */
+	state->period     = data_lrc * pwm_clk_ns;
+
+	/* duty cycle(ns) means high level eclapse ns if it is normal polarity */
+	state->duty_cycle = data_hrc * pwm_clk_ns;
+
+	/* polarity, we don't use it now because it is not in dts */
+	state->polarity   = PWM_POLARITY_NORMAL;
+
+	/* enabled or not */
+	state->enabled    = 1;
+
+	dev_dbg(pwm->chip.dev, "%s: no:%d\n", __func__, dev->hwpwm);
+	dev_dbg(pwm->chip.dev, "data_hrc:0x%x 0x%x\n", data_hrc, data_lrc);
+	dev_dbg(pwm->chip.dev, "period:%llu\n", state->period);
+	dev_dbg(pwm->chip.dev, "duty_cycle:%llu\n", state->duty_cycle);
+	dev_dbg(pwm->chip.dev, "polarity:%d\n", state->polarity);
+	dev_dbg(pwm->chip.dev, "enabled:%d\n", state->enabled);
+
+	return 0;
+}
+
+static int sifive_pwm_ptc_apply(struct pwm_chip *chip, struct pwm_device *dev,
+				const struct pwm_state *state)
+{
+	struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
+	void __iomem *reg_addr;
+	u32 pwm_clk_ns = 0;
+	u32 data_hrc = 0;
+	u32 data_lrc = 0;
+	u32 period_data = 0;
+	u32 duty_data = 0;
+
+	dev_dbg(pwm->chip.dev, "%s: no:%d\n", __func__, dev->hwpwm);
+	dev_dbg(pwm->chip.dev, "period:%llu\n", state->period);
+	dev_dbg(pwm->chip.dev, "duty_cycle:%llu\n", state->duty_cycle);
+	dev_dbg(pwm->chip.dev, "polarity:%d\n", state->polarity);
+	dev_dbg(pwm->chip.dev, "enabled:%d\n", state->enabled);
+
+	/* duty_cycle should be less or equal than period */
+	if (state->duty_cycle > state->period)
+		return -EINVAL;
+
+	/* calculate pwm real period (ns) */
+	pwm_clk_ns = NS_1 / clk_get_rate(pwm->clk);
+
+	dev_dbg(pwm->chip.dev, "pwm_clk_ns:%u\n", pwm_clk_ns);
+
+	/* calculate period count */
+	period_data = div_u64(state->period, pwm_clk_ns);
+
+	if (!state->enabled)
+		/* if disabled, just set duty_data to 0, which means low level always */
+		duty_data = 0;
+	else
+		/* calculate duty count */
+		duty_data = div_u64(state->duty_cycle, pwm_clk_ns);
+
+	dev_dbg(pwm->chip.dev, "period_data:%u, duty_data:%u\n",
+		period_data, duty_data);
+
+	if (state->polarity == PWM_POLARITY_NORMAL)
+		/* calculate data_hrc */
+		data_hrc = period_data - duty_data;
+	else
+		/* calculate data_hrc */
+		data_hrc = duty_data;
+
+	data_lrc = period_data;
+
+	/* set hrc */
+	reg_addr = REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm);
+	dev_dbg(pwm->chip.dev, "%s: reg_addr:%p, data:%u\n",
+		__func__, reg_addr, data_hrc);
+
+	iowrite32(data_hrc, reg_addr);
+
+	dev_dbg(pwm->chip.dev, "%s: hrc ok\n", __func__);
+
+	/* set lrc */
+	reg_addr = REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm);
+	dev_dbg(pwm->chip.dev, "%s: reg_addr:%p, data:%u\n",
+		__func__, reg_addr, data_lrc);
+
+	iowrite32(data_lrc, reg_addr);
+	dev_dbg(pwm->chip.dev, "%s: lrc ok\n", __func__);
+
+	/* Clear REG_RPTC_CNTR after setting period & duty_cycle */
+	reg_addr = REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm);
+	iowrite32(0, reg_addr);
+	return 0;
+}
+
+static const struct pwm_ops sifive_pwm_ptc_ops = {
+	.get_state	= sifive_pwm_ptc_get_state,
+	.apply		= sifive_pwm_ptc_apply,
+	.owner		= THIS_MODULE,
+};
+
+static void sifive_pwm_ptc_disable_action(void *data)
+{
+	clk_disable_unprepare(data);
+}
+
+static int sifive_pwm_ptc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *node = pdev->dev.of_node;
+	struct sifive_pwm_ptc_device *pwm;
+	struct pwm_chip *chip;
+	struct reset_control *rst;
+	int ret;
+
+	pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
+	if (!pwm)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, pwm);
+
+	chip = &pwm->chip;
+	chip->dev = dev;
+	chip->ops = &sifive_pwm_ptc_ops;
+
+	/* how many parameters can be transferred to ptc, need to fix */
+	chip->of_pwm_n_cells = 3;
+	chip->base = -1;
+
+	/* get pwm channels count, max value is 8 */
+	ret = of_property_read_u32(node, "starfive,npwm", &chip->npwm);
+	if (ret < 0 || chip->npwm > MAX_PWM)
+		chip->npwm = MAX_PWM;
+
+	dev_dbg(dev, "%s: npwm:0x%x\n", __func__, chip->npwm);
+
+	/* get IO base address */
+	pwm->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(pwm->regs))
+		return dev_err_probe(dev, PTR_ERR(pwm->regs),
+				     "Unable to map IO resources\n");
+
+	pwm->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(pwm->clk))
+		return dev_err_probe(dev, PTR_ERR(pwm->clk),
+				     "Unable to get controller clock\n");
+
+	ret = clk_prepare_enable(pwm->clk);
+	if (ret)
+		return dev_err_probe(dev, ret, "Unable to enable clock\n");
+
+	ret = devm_add_action_or_reset(dev, sifive_pwm_ptc_disable_action, pwm->clk);
+	if (ret)
+		return ret;
+
+	rst = devm_reset_control_get_exclusive(dev, NULL);
+	if (IS_ERR(rst))
+		return dev_err_probe(dev, PTR_ERR(rst), "Unable to get reset\n");
+
+	ret = reset_control_deassert(rst);
+	if (ret)
+		return dev_err_probe(dev, ret, "Unable to deassert reset\n");
+
+	/*
+	 * after pwmchip_add it will show up as /sys/class/pwm/pwmchip0,
+	 * 0 is chip->base, pwm0 can be seen after running echo 0 > export
+	 */
+	ret = devm_pwmchip_add(dev, chip);
+	if (ret)
+		return dev_err_probe(dev, ret, "cannot register PTC: %d\n", ret);
+
+	dev_dbg(dev, "SiFive PWM PTC chip registered %d PWMs\n", chip->npwm);
+	return 0;
+}
+
+static const struct of_device_id sifive_pwm_ptc_of_match[] = {
+	{ .compatible = "starfive,pwm0" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sifive_pwm_ptc_of_match);
+
+static struct platform_driver sifive_pwm_ptc_driver = {
+	.probe = sifive_pwm_ptc_probe,
+	.driver = {
+		.name = "pwm-sifive-ptc",
+		.of_match_table = sifive_pwm_ptc_of_match,
+	},
+};
+module_platform_driver(sifive_pwm_ptc_driver);
+
+MODULE_DESCRIPTION("SiFive PWM PTC driver");
+MODULE_LICENSE("GPL v2");
-- 
2.41.0


From feb33451916da57445f3455e12844291100a96e5 Mon Sep 17 00:00:00 2001
From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: Thu, 27 May 2021 20:13:43 +0200
Subject: [PATCH 64/72] [WIP] dt-bindings: dma: dw-axi-dmac: Increase DMA
 channel limit to 16

The first DMAC instance in the StarFive JH7100 SoC supports 16 DMA
channels.

FIXME Given there are more changes to the driver than just increasing
      DMAC_MAX_CHANNELS, we probably need a new compatible value, too.

Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 363cf8bd150d..2c154a8c2f57 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -56,7 +56,7 @@ properties:
 
   dma-channels:
     minimum: 1
-    maximum: 8
+    maximum: 16
 
   resets:
     minItems: 1
@@ -80,14 +80,14 @@ properties:
       Channel priority specifier associated with the DMA channels.
     $ref: /schemas/types.yaml#/definitions/uint32-array
     minItems: 1
-    maxItems: 8
+    maxItems: 16
 
   snps,block-size:
     description: |
       Channel block size specifier associated with the DMA channels.
     $ref: /schemas/types.yaml#/definitions/uint32-array
     minItems: 1
-    maxItems: 8
+    maxItems: 16
 
   snps,axi-max-burst-len:
     description: |
-- 
2.41.0


From a20727efb4aaca1b812917dbeb255f34506d3e3b Mon Sep 17 00:00:00 2001
From: Samin Guo <samin.guo@starfivetech.com>
Date: Wed, 17 Nov 2021 14:50:45 +0800
Subject: [PATCH 65/72] dmaengine: dw-axi-dmac: Handle xfer start while
 non-idle

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Curry Zhang <curry.zhang@starfivetech.com>
---
 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 12 +++++++++++-
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h          |  1 +
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 796b6caf0bab..cfdd002ad691 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -382,11 +382,13 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
 	u32 irq_mask;
 	u8 lms = 0; /* Select AXI0 master for LLI fetching */
 
+	chan->is_err = false;
 	if (unlikely(axi_chan_is_hw_enable(chan))) {
 		dev_err(chan2dev(chan), "%s is non-idle!\n",
 			axi_chan_name(chan));
 
-		return;
+		axi_chan_disable(chan);
+		chan->is_err = true;
 	}
 
 	axi_dma_enable(chan->chip);
@@ -1028,6 +1030,14 @@ static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status)
 			axi_chan_name(chan));
 		goto out;
 	}
+	if (chan->is_err) {
+		struct axi_dma_desc *desc = vd_to_axi_desc(vd);
+
+		axi_chan_block_xfer_start(chan, desc);
+		chan->is_err = false;
+		goto out;
+	}
+
 	/* Remove the completed descriptor from issued list */
 	list_del(&vd->node);
 
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index eb267cb24f67..10d96a423bb2 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -50,6 +50,7 @@ struct axi_dma_chan {
 	struct dma_slave_config		config;
 	enum dma_transfer_direction	direction;
 	bool				cyclic;
+	bool 				is_err;
 	/* these other elements are all protected by vc.lock */
 	bool				is_paused;
 };
-- 
2.41.0


From bb26e16b79f123645e4d3315b2df158a57877b38 Mon Sep 17 00:00:00 2001
From: Samin Guo <samin.guo@starfivetech.com>
Date: Wed, 17 Nov 2021 14:50:45 +0800
Subject: [PATCH 66/72] dmaengine: dw-axi-dmac: Add StarFive JH7100 support

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 12 ++++++++++++
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h          |  4 ++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index cfdd002ad691..6aaec13d6648 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -677,8 +677,13 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
 
 	hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
 
+#ifdef CONFIG_SOC_STARFIVE
+	ctllo |= DWAXIDMAC_BURST_TRANS_LEN_16 << CH_CTL_L_DST_MSIZE_POS |
+		 DWAXIDMAC_BURST_TRANS_LEN_16 << CH_CTL_L_SRC_MSIZE_POS;
+#else
 	ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
 		 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
+#endif
 	hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
 
 	set_desc_src_master(hw_desc);
@@ -1505,7 +1510,11 @@ static int dw_probe(struct platform_device *pdev)
 	 * Therefore, set constraint to 1024 * 4.
 	 */
 	dw->dma.dev->dma_parms = &dw->dma_parms;
+#ifdef CONFIG_SOC_STARFIVE
+	dma_set_max_seg_size(&pdev->dev, DMAC_MAX_BLK_SIZE);
+#else
 	dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
+#endif
 	platform_set_drvdata(pdev, chip);
 
 	pm_runtime_enable(chip->dev);
@@ -1589,6 +1598,9 @@ static const struct of_device_id dw_dma_of_id_table[] = {
 	}, {
 		.compatible = "intel,kmb-axi-dma",
 		.data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
+	}, {
+		.compatible = "starfive,jh7100-axi-dma",
+		.data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
 	}, {
 		.compatible = "starfive,jh7110-axi-dma",
 		.data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 10d96a423bb2..0964b0588f95 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -283,7 +283,11 @@ enum {
 #define CH_CTL_L_SRC_MAST		BIT(0)
 
 /* CH_CFG_H */
+#ifdef CONFIG_SOC_STARFIVE
+#define CH_CFG_H_PRIORITY_POS		15
+#else
 #define CH_CFG_H_PRIORITY_POS		17
+#endif
 #define CH_CFG_H_DST_PER_POS		12
 #define CH_CFG_H_SRC_PER_POS		7
 #define CH_CFG_H_HS_SEL_DST_POS		4
-- 
2.41.0


From ee873b7f976330818bb2f091781cfaf5fbeaaeef Mon Sep 17 00:00:00 2001
From: Walker Chen <walker.chen@starfivetech.com>
Date: Wed, 17 Nov 2021 15:50:50 +0800
Subject: [PATCH 67/72] ASoC: starfive: Add StarFive JH7100 audio drivers

Signed-off-by: Michael Yan <michael.yan@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 sound/soc/Makefile                      |    1 +
 sound/soc/starfive/Kconfig              |   56 ++
 sound/soc/starfive/Makefile             |   21 +
 sound/soc/starfive/i2svad-pcm.c         |  249 ++++++
 sound/soc/starfive/i2svad.c             | 1042 +++++++++++++++++++++++
 sound/soc/starfive/i2svad.h             |  246 ++++++
 sound/soc/starfive/pdm.c                |  362 ++++++++
 sound/soc/starfive/pdm.h                |   43 +
 sound/soc/starfive/pwmdac-pcm.c         |  233 +++++
 sound/soc/starfive/pwmdac-transmitter.c |   81 ++
 sound/soc/starfive/pwmdac.c             |  862 +++++++++++++++++++
 sound/soc/starfive/pwmdac.h             |  161 ++++
 sound/soc/starfive/spdif-pcm.c          |  288 +++++++
 sound/soc/starfive/spdif.c              |  384 +++++++++
 sound/soc/starfive/spdif.h              |  154 ++++
 15 files changed, 4183 insertions(+)
 create mode 100644 sound/soc/starfive/i2svad-pcm.c
 create mode 100644 sound/soc/starfive/i2svad.c
 create mode 100644 sound/soc/starfive/i2svad.h
 create mode 100644 sound/soc/starfive/pdm.c
 create mode 100644 sound/soc/starfive/pdm.h
 create mode 100644 sound/soc/starfive/pwmdac-pcm.c
 create mode 100644 sound/soc/starfive/pwmdac-transmitter.c
 create mode 100644 sound/soc/starfive/pwmdac.c
 create mode 100644 sound/soc/starfive/pwmdac.h
 create mode 100644 sound/soc/starfive/spdif-pcm.c
 create mode 100644 sound/soc/starfive/spdif.c
 create mode 100644 sound/soc/starfive/spdif.h

diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 8376fdb217ed..e586a58400f6 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_SND_SOC)	+= pxa/
 obj-$(CONFIG_SND_SOC)	+= qcom/
 obj-$(CONFIG_SND_SOC)	+= rockchip/
 obj-$(CONFIG_SND_SOC)	+= samsung/
+obj-$(CONFIG_SND_SOC)	+= starfive/
 obj-$(CONFIG_SND_SOC)	+= sh/
 obj-$(CONFIG_SND_SOC)	+= sof/
 obj-$(CONFIG_SND_SOC)	+= spear/
diff --git a/sound/soc/starfive/Kconfig b/sound/soc/starfive/Kconfig
index fafb681f8c0a..a397896e4a4f 100644
--- a/sound/soc/starfive/Kconfig
+++ b/sound/soc/starfive/Kconfig
@@ -13,3 +13,59 @@ config SND_SOC_JH7110_TDM
 	select SND_SOC_GENERIC_DMAENGINE_PCM
 	help
 	  Say Y or M if you want to add support for StarFive TDM driver.
+
+config SND_STARFIVE_SPDIF
+	tristate "starfive spdif"
+	depends on SOC_STARFIVE || COMPILE_TEST
+	select SND_SOC_GENERIC_DMAENGINE_PCM
+	select REGMAP_MMIO
+	help
+	  Say Y or M if you want to add support for codecs attached to the
+	  I2S interface on VIC vic_starlight board. You will also need to select
+	  the drivers for the rest of VIC audio subsystem.
+
+config SND_STARFIVE_SPDIF_PCM
+	bool "PCM PIO extension for spdif driver"
+	depends on SND_STARFIVE_SPDIF
+	help
+	 Say Y or N if you want to add a custom ALSA extension that registers
+	 a PCM and uses PIO to transfer data.
+
+config SND_STARFIVE_PWMDAC
+	tristate "starfive pwmdac Device Driver"
+	depends on SOC_STARFIVE || COMPILE_TEST
+	select SND_SOC_GENERIC_DMAENGINE_PCM
+	help
+	 Say Y or M if you want to add support for sf pwmdac driver.
+
+config SND_STARFIVE_PWMDAC_PCM
+	bool "PCM PIO extension for pwmdac driver"
+	depends on SND_STARFIVE_PWMDAC
+	help
+	 Say Y or N if you want to add a custom ALSA extension that registers
+	 a PCM and uses PIO to transfer data.
+
+config SND_STARFIVE_PDM
+	tristate "starfive pdm Device Driver"
+	depends on SOC_STARFIVE || COMPILE_TEST
+	select REGMAP_MMIO
+	help
+	 Say Y or M if you want to add support for sf pdm driver.
+
+config SND_STARFIVE_I2SVAD
+	tristate "starfive I2SVAD Device Driver"
+	depends on SOC_STARFIVE || COMPILE_TEST
+	select SND_SOC_GENERIC_DMAENGINE_PCM
+	help
+	 Say Y or M if you want to add support for I2SVAD driver for
+	 starfive I2SVAD device.
+
+config SND_STARFIVE_I2SVAD_PCM
+	bool "PCM PIO extension for I2SVAD driver"
+	depends on SND_STARFIVE_I2SVAD
+	help
+	 Say Y or N if you want to add a custom ALSA extension that registers
+	 a PCM and uses PIO to transfer data.
+
+	 This functionality is specially suited for I2SVAD devices that don't have
+	 DMA support.
diff --git a/sound/soc/starfive/Makefile b/sound/soc/starfive/Makefile
index f7d960211d72..5352c4c2dd9f 100644
--- a/sound/soc/starfive/Makefile
+++ b/sound/soc/starfive/Makefile
@@ -1,2 +1,23 @@
 # StarFive Platform Support
 obj-$(CONFIG_SND_SOC_JH7110_TDM) += jh7110_tdm.o
+
+snd-soc-starfive-spdif-y := spdif.o
+snd-soc-starfive-spdif-$(CONFIG_SND_STARFIVE_SPDIF_PCM) += spdif-pcm.o
+
+obj-$(CONFIG_SND_STARFIVE_SPDIF) += snd-soc-starfive-spdif.o
+
+snd-soc-starfive-pwmdac-y := pwmdac.o
+snd-soc-starfive-pwmdac-$(CONFIG_SND_STARFIVE_PWMDAC_PCM) += pwmdac-pcm.o
+snd-soc-starfive-pwmdac-transmitter-y := pwmdac-transmitter.o
+
+obj-$(CONFIG_SND_STARFIVE_PWMDAC) += snd-soc-starfive-pwmdac.o
+obj-$(CONFIG_SND_STARFIVE_PWMDAC) += snd-soc-starfive-pwmdac-transmitter.o
+
+snd-soc-starfive-pdm-y := pdm.o
+
+obj-$(CONFIG_SND_STARFIVE_PDM) += snd-soc-starfive-pdm.o
+
+snd-soc-starfive-i2svad-y := i2svad.o
+snd-soc-starfive-i2svad-$(CONFIG_SND_STARFIVE_I2SVAD_PCM) += i2svad-pcm.o
+
+obj-$(CONFIG_SND_STARFIVE_I2SVAD) += snd-soc-starfive-i2svad.o
diff --git a/sound/soc/starfive/i2svad-pcm.c b/sound/soc/starfive/i2svad-pcm.c
new file mode 100644
index 000000000000..61f6339d00d2
--- /dev/null
+++ b/sound/soc/starfive/i2svad-pcm.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/io.h>
+#include <linux/rcupdate.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+
+#include "i2svad.h"
+
+#define BUFFER_BYTES_MAX	(3 * 2 * 8 * PERIOD_BYTES_MIN)
+#define PERIOD_BYTES_MIN	4096
+#define PERIODS_MIN		2
+
+#define i2svad_pcm_tx_fn(sample_bits) \
+static unsigned int i2svad_pcm_tx_##sample_bits(struct i2svad_dev *dev, \
+		struct snd_pcm_runtime *runtime, unsigned int tx_ptr, \
+		bool *period_elapsed) \
+{ \
+	const u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
+	unsigned int period_pos = tx_ptr % runtime->period_size; \
+	int i; \
+\
+	for (i = 0; i < dev->fifo_th; i++) { \
+		iowrite32(p[tx_ptr][0], dev->i2s_base + LRBR_LTHR(0)); \
+		iowrite32(p[tx_ptr][1], dev->i2s_base + RRBR_RTHR(0)); \
+		period_pos++; \
+		if (++tx_ptr >= runtime->buffer_size) \
+			tx_ptr = 0; \
+	} \
+	*period_elapsed = period_pos >= runtime->period_size; \
+	return tx_ptr; \
+}
+
+#define i2svad_pcm_rx_fn(sample_bits) \
+static unsigned int i2svad_pcm_rx_##sample_bits(struct i2svad_dev *dev, \
+		struct snd_pcm_runtime *runtime, unsigned int rx_ptr, \
+		bool *period_elapsed) \
+{ \
+	u##sample_bits (*p)[2] = (void *)runtime->dma_area; \
+	unsigned int period_pos = rx_ptr % runtime->period_size; \
+	int i; \
+\
+	for (i = 0; i < dev->fifo_th; i++) { \
+		p[rx_ptr][0] = ioread32(dev->i2s_base + LRBR_LTHR(0)); \
+		p[rx_ptr][1] = ioread32(dev->i2s_base + RRBR_RTHR(0)); \
+		period_pos++; \
+		if (++rx_ptr >= runtime->buffer_size) \
+			rx_ptr = 0; \
+	} \
+	*period_elapsed = period_pos >= runtime->period_size; \
+	return rx_ptr; \
+}
+
+i2svad_pcm_tx_fn(16);
+i2svad_pcm_rx_fn(16);
+
+#undef i2svad_pcm_tx_fn
+#undef i2svad_pcm_rx_fn
+
+static const struct snd_pcm_hardware i2svad_pcm_hardware = {
+	.info = SNDRV_PCM_INFO_INTERLEAVED |
+		SNDRV_PCM_INFO_MMAP |
+		SNDRV_PCM_INFO_MMAP_VALID |
+		SNDRV_PCM_INFO_BLOCK_TRANSFER,
+	.rates = SNDRV_PCM_RATE_32000 |
+		SNDRV_PCM_RATE_44100 |
+		SNDRV_PCM_RATE_48000,
+	.rate_min = 32000,
+	.rate_max = 48000,
+	.formats = SNDRV_PCM_FMTBIT_S16_LE,
+	.channels_min = 2,
+	.channels_max = 2,
+	.buffer_bytes_max = BUFFER_BYTES_MAX,
+	.period_bytes_min = PERIOD_BYTES_MIN,
+	.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
+	.periods_min = PERIODS_MIN,
+	.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
+	.fifo_size = 16,
+};
+
+static void i2svad_pcm_transfer(struct i2svad_dev *dev, bool push)
+{
+	struct snd_pcm_substream *substream;
+	bool active, period_elapsed;
+
+	rcu_read_lock();
+	if (push)
+		substream = rcu_dereference(dev->tx_substream);
+	else
+		substream = rcu_dereference(dev->rx_substream);
+	active = substream && snd_pcm_running(substream);
+	if (active) {
+		unsigned int ptr;
+		unsigned int new_ptr;
+
+		if (push) {
+			ptr = READ_ONCE(dev->tx_ptr);
+			new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
+					&period_elapsed);
+			cmpxchg(&dev->tx_ptr, ptr, new_ptr);
+		} else {
+			ptr = READ_ONCE(dev->rx_ptr);
+			new_ptr = dev->rx_fn(dev, substream->runtime, ptr,
+					&period_elapsed);
+			cmpxchg(&dev->rx_ptr, ptr, new_ptr);
+		}
+
+		if (period_elapsed)
+			snd_pcm_period_elapsed(substream);
+	}
+	rcu_read_unlock();
+}
+
+void i2svad_pcm_push_tx(struct i2svad_dev *dev)
+{
+	i2svad_pcm_transfer(dev, true);
+}
+
+void i2svad_pcm_pop_rx(struct i2svad_dev *dev)
+{
+	i2svad_pcm_transfer(dev, false);
+}
+
+static int i2svad_pcm_open(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct i2svad_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+	snd_soc_set_runtime_hwparams(substream, &i2svad_pcm_hardware);
+	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
+	runtime->private_data = dev;
+
+	return 0;
+}
+
+static int i2svad_pcm_close(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream)
+{
+	synchronize_rcu();
+	return 0;
+}
+
+static int i2svad_pcm_hw_params(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream,
+			struct snd_pcm_hw_params *hw_params)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct i2svad_dev *dev = runtime->private_data;
+
+	switch (params_channels(hw_params)) {
+	case 2:
+		break;
+	default:
+		dev_err(dev->dev, "invalid channels number\n");
+		return -EINVAL;
+	}
+
+	switch (params_format(hw_params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		dev->tx_fn = i2svad_pcm_tx_16;
+		dev->rx_fn = i2svad_pcm_rx_16;
+		break;
+	default:
+		dev_err(dev->dev, "invalid format\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int i2svad_pcm_trigger(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream, int cmd)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct i2svad_dev *dev = runtime->private_data;
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			WRITE_ONCE(dev->tx_ptr, 0);
+			rcu_assign_pointer(dev->tx_substream, substream);
+		} else {
+			WRITE_ONCE(dev->rx_ptr, 0);
+			rcu_assign_pointer(dev->rx_substream, substream);
+		}
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			rcu_assign_pointer(dev->tx_substream, NULL);
+		else
+			rcu_assign_pointer(dev->rx_substream, NULL);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static snd_pcm_uframes_t i2svad_pcm_pointer(struct snd_soc_component *component,
+					struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct i2svad_dev *dev = runtime->private_data;
+	snd_pcm_uframes_t pos;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		pos = READ_ONCE(dev->tx_ptr);
+	else
+		pos = READ_ONCE(dev->rx_ptr);
+
+	return pos < runtime->buffer_size ? pos : 0;
+}
+
+static int i2svad_pcm_new(struct snd_soc_component *component,
+			struct snd_soc_pcm_runtime *rtd)
+{
+	size_t size = i2svad_pcm_hardware.buffer_bytes_max;
+
+	snd_pcm_set_managed_buffer_all(rtd->pcm,
+			SNDRV_DMA_TYPE_CONTINUOUS,
+			NULL, size, size);
+	return 0;
+}
+
+static const struct snd_soc_component_driver i2svad_pcm_component = {
+	.open		= i2svad_pcm_open,
+	.close		= i2svad_pcm_close,
+	.hw_params	= i2svad_pcm_hw_params,
+	.trigger	= i2svad_pcm_trigger,
+	.pointer	= i2svad_pcm_pointer,
+	.pcm_construct	= i2svad_pcm_new,
+};
+
+int i2svad_pcm_register(struct platform_device *pdev)
+{
+	return devm_snd_soc_register_component(&pdev->dev, &i2svad_pcm_component,
+					NULL, 0);
+}
diff --git a/sound/soc/starfive/i2svad.c b/sound/soc/starfive/i2svad.c
new file mode 100644
index 000000000000..74978d30702c
--- /dev/null
+++ b/sound/soc/starfive/i2svad.c
@@ -0,0 +1,1042 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <sound/designware_i2s.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/dmaengine_pcm.h>
+#include <linux/kthread.h>
+
+#include "i2svad.h"
+
+/* vad control function*/
+static void vad_start(struct vad_params *vad)
+{
+	regmap_update_bits(vad->vad_map, VAD_MEM_SW,
+			VAD_MEM_SW_MASK, VAD_MEM_SW_TO_VAD);
+	regmap_update_bits(vad->vad_map, VAD_SW,
+			VAD_SW_MASK, VAD_SW_VAD_XMEM_ENABLE|VAD_SW_ADC_ENABLE);
+	regmap_update_bits(vad->vad_map, VAD_SPINT_EN,
+			VAD_SPINT_EN_MASK, VAD_SPINT_EN_ENABLE);
+	regmap_update_bits(vad->vad_map, VAD_SLINT_EN,
+			VAD_SLINT_EN_MASK, VAD_SLINT_EN_ENABLE);
+}
+
+static void vad_stop(struct vad_params *vad)
+{
+	regmap_update_bits(vad->vad_map, VAD_SPINT_EN,
+			VAD_SPINT_EN_MASK, VAD_SLINT_EN_DISABLE);
+	regmap_update_bits(vad->vad_map, VAD_SLINT_EN,
+			VAD_SLINT_EN_MASK, VAD_SLINT_EN_DISABLE);
+	regmap_update_bits(vad->vad_map, VAD_SW,
+			VAD_SW_MASK, VAD_SW_VAD_XMEM_DISABLE|VAD_SW_ADC_DISABLE);
+	regmap_update_bits(vad->vad_map, VAD_MEM_SW,
+			VAD_MEM_SW_MASK, VAD_MEM_SW_TO_AXI);
+}
+
+static void vad_status(struct vad_params *vad)
+{
+	u32 sp_value,sp_en;
+	u32 sl_value,sl_en;
+
+	regmap_read(vad->vad_map, VAD_SPINT,&sp_value);
+	regmap_read(vad->vad_map, VAD_SPINT_EN,&sp_en);
+	if (sp_value&sp_en){
+		regmap_update_bits(vad->vad_map, VAD_SPINT_CLR,
+				VAD_SPINT_CLR_MASK, VAD_SPINT_CLR_VAD_SPINT);
+		vad->vstatus = VAD_STATUS_SPINT;
+		vad_stop(vad);
+		vad_start(vad);
+	}
+
+	regmap_read(vad->vad_map, VAD_SLINT,&sl_value);
+	regmap_read(vad->vad_map, VAD_SLINT_EN,&sl_en);
+	if (sl_value&sl_en){
+		regmap_update_bits(vad->vad_map, VAD_SLINT_CLR,
+				VAD_SLINT_CLR_MASK, VAD_SLINT_CLR_VAD_SLINT);
+		vad->vstatus = VAD_STATUS_SLINT;
+	}
+}
+
+static int vad_trigger(struct vad_params *vad,int cmd)
+{
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if(vad->vswitch)
+		{
+			vad_start(vad);
+		}
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		vad_stop(vad);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static void vad_init(struct vad_params *vad)
+{
+	/* left_margin */
+	regmap_update_bits(vad->vad_map, VAD_LEFT_MARGIN,
+			VAD_LEFT_MARGIN_MASK, 0x0);
+	/* right_margin */
+	regmap_update_bits(vad->vad_map, VAD_RIGHT_MARGIN,
+			VAD_RIGHT_MARGIN_MASK, 0x0);
+	/*low-energy transition range threshold ——NL*/
+	regmap_update_bits(vad->vad_map, VAD_N_LOW_CONT_FRAMES,
+			VAD_N_LOW_CONT_FRAMES_MASK, 0x3);
+	/* low-energy transition range */
+	regmap_update_bits(vad->vad_map, VAD_N_LOW_SEEK_FRAMES,
+			VAD_N_LOW_SEEK_FRAMES_MASK, 0x8);
+	/* high-energy transition range threshold——NH */
+	regmap_update_bits(vad->vad_map, VAD_N_HIGH_CONT_FRAMES,
+			VAD_N_HIGH_CONT_FRAMES_MASK, 0x5);
+	/* high-energy transition range */
+	regmap_update_bits(vad->vad_map, VAD_N_HIGH_SEEK_FRAMES,
+			VAD_N_HIGH_SEEK_FRAMES_MASK, 0x1E);
+	/*low-energy voice range threshold——NVL*/
+	regmap_update_bits(vad->vad_map, VAD_N_SPEECH_LOW_HIGH_FRAMES,
+			VAD_N_SPEECH_LOW_HIGH_FRAMES_MASK, 0x2);
+	/*low-energy voice range*/
+	regmap_update_bits(vad->vad_map, VAD_N_SPEECH_LOW_SEEK_FRAMES,
+			VAD_N_SPEECH_LOW_SEEK_FRAMES_MASK, 0x12);
+	/*mean silence frame range*/
+	regmap_update_bits(vad->vad_map, VAD_MEAN_SIL_FRAMES,
+			VAD_MEAN_SIL_FRAMES_MASK, 0xA);
+	/*low-energy threshold scaling factor,12bit(0~0xFFF)*/
+	regmap_update_bits(vad->vad_map, VAD_N_ALPHA,
+			VAD_N_ALPHA_MASK, 0x1A);
+	/*high-energy threshold scaling factor,12bit(0~0xFFF)*/
+	regmap_update_bits(vad->vad_map, VAD_N_BETA,
+			VAD_N_BETA_MASK, 0x34);
+	regmap_update_bits(vad->vad_map, VAD_LEFT_WD,
+			VAD_LEFT_WD_MASK, VAD_LEFT_WD_BIT_15_0);
+	regmap_update_bits(vad->vad_map, VAD_RIGHT_WD,
+			VAD_RIGHT_WD_MASK, VAD_RIGHT_WD_BIT_15_0);
+	regmap_update_bits(vad->vad_map, VAD_LR_SEL,
+			VAD_LR_SEL_MASK, VAD_LR_SEL_L);
+	regmap_update_bits(vad->vad_map, VAD_STOP_DELAY,
+			VAD_STOP_DELAY_MASK, VAD_STOP_DELAY_0_SAMPLE);
+	regmap_update_bits(vad->vad_map, VAD_ADDR_START,
+			VAD_ADDR_START_MASK, 0x0);
+	regmap_update_bits(vad->vad_map, VAD_ADDR_WRAP,
+			VAD_ADDR_WRAP_MASK, 0x2000);
+	regmap_update_bits(vad->vad_map, VAD_MEM_SW,
+			VAD_MEM_SW_MASK, VAD_MEM_SW_TO_AXI);
+	regmap_update_bits(vad->vad_map, VAD_SPINT_CLR,
+			VAD_SPINT_CLR_MASK, VAD_SPINT_CLR_VAD_SPINT);
+	regmap_update_bits(vad->vad_map, VAD_SLINT_CLR,
+			VAD_SLINT_CLR_MASK, VAD_SLINT_CLR_VAD_SLINT);
+}
+
+
+static int vad_switch_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = 1;
+
+	return 0;
+}
+
+static int vad_switch_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.integer.value[0] = dev->vad.vswitch;
+
+	return 0;
+}
+
+static int vad_switch_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
+	int val;
+
+	val = ucontrol->value.integer.value[0];
+	if (val && !dev->vad.vswitch) {
+		dev->vad.vswitch = true;
+	} else if (!val && dev->vad.vswitch) {
+		dev->vad.vswitch = false;
+		vad_stop(&(dev->vad));
+	}
+
+	return 0;
+}
+
+
+static int vad_status_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = 2;
+
+	return 0;
+}
+
+static int vad_status_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.integer.value[0] = dev->vad.vstatus;
+	dev->vad.vstatus = VAD_STATUS_NORMAL;
+
+	return 0;
+}
+
+
+#define SOC_VAD_SWITCH_DECL(xname) \
+{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+	.info = vad_switch_info, .get = vad_switch_get, \
+	.put = vad_switch_put, }
+
+#define SOC_VAD_STATUS_DECL(xname) \
+{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+	.info = vad_status_info, .get = vad_status_get, }
+
+
+static const struct snd_kcontrol_new vad_snd_controls[] = {
+	SOC_VAD_SWITCH_DECL("vad switch"),
+	SOC_VAD_STATUS_DECL("vad status"),
+};
+
+static int vad_probe(struct snd_soc_component *component)
+{
+	struct i2svad_dev *priv = snd_soc_component_get_drvdata(component);
+
+	snd_soc_component_init_regmap(component, priv->vad.vad_map);
+	snd_soc_add_component_controls(component, vad_snd_controls,
+				ARRAY_SIZE(vad_snd_controls));
+
+	return 0;
+}
+
+/* i2s control function*/
+static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
+{
+	writel(val, io_base + reg);
+}
+
+static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
+{
+	return readl(io_base + reg);
+}
+
+static inline void i2s_disable_channels(struct i2svad_dev *dev, u32 stream)
+{
+	u32 i = 0;
+
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		for (i = 0; i < ALL_CHANNEL_NUM; i++)
+			i2s_write_reg(dev->i2s_base, TER(i), 0);
+	} else {
+		for (i = 0; i < ALL_CHANNEL_NUM; i++)
+			i2s_write_reg(dev->i2s_base, RER(i), 0);
+	}
+}
+
+static inline void i2s_clear_irqs(struct i2svad_dev *dev, u32 stream)
+{
+	u32 i = 0;
+
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		for (i = 0; i < ALL_CHANNEL_NUM; i++)
+			i2s_read_reg(dev->i2s_base, TOR(i));
+	} else {
+		for (i = 0; i < ALL_CHANNEL_NUM; i++)
+			i2s_read_reg(dev->i2s_base, ROR(i));
+	}
+}
+
+static inline void i2s_disable_irqs(struct i2svad_dev *dev, u32 stream,
+				int chan_nr)
+{
+	u32 i, irq;
+
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		for (i = 0; i < (chan_nr / 2); i++) {
+			irq = i2s_read_reg(dev->i2s_base, IMR(i));
+			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
+		}
+	} else {
+		for (i = 0; i < (chan_nr / 2); i++) {
+			irq = i2s_read_reg(dev->i2s_base, IMR(i));
+			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
+		}
+	}
+}
+
+static inline void i2s_enable_irqs(struct i2svad_dev *dev, u32 stream,
+				int chan_nr)
+{
+	u32 i, irq;
+
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		for (i = 0; i < (chan_nr / 2); i++) {
+			irq = i2s_read_reg(dev->i2s_base, IMR(i));
+			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
+		}
+	} else {
+		for (i = 0; i < (chan_nr / 2); i++) {
+			irq = i2s_read_reg(dev->i2s_base, IMR(i));
+			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
+		}
+	}
+}
+
+static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
+{
+	struct i2svad_dev *dev = dev_id;
+	bool irq_valid = false;
+	u32 isr[4];
+	int i;
+
+	for (i = 0; i < ALL_CHANNEL_NUM; i++)
+		isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
+
+	i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
+	i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
+
+	for (i = 0; i < 4; i++) {
+		/*
+		 * Check if TX fifo is empty. If empty fill FIFO with samples
+		 * NOTE: Only two channels supported
+		 */
+		if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
+			i2svad_pcm_push_tx(dev);
+			irq_valid = true;
+		}
+
+		/*
+		 * Data available. Retrieve samples from FIFO
+		 * NOTE: Only two channels supported
+		 */
+		if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
+			i2svad_pcm_pop_rx(dev);
+			irq_valid = true;
+		}
+
+		/* Error Handling: TX */
+		if (isr[i] & ISR_TXFO) {
+			//dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i);
+			irq_valid = true;
+		}
+
+		/* Error Handling: TX */
+		if (isr[i] & ISR_RXFO) {
+			//dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i);
+			irq_valid = true;
+		}
+	}
+
+	vad_status(&(dev->vad));
+
+	if (irq_valid)
+		return IRQ_HANDLED;
+	else
+		return IRQ_NONE;
+}
+
+static void i2s_start(struct i2svad_dev *dev,
+			struct snd_pcm_substream *substream)
+{
+	struct i2s_clk_config_data *config = &dev->config;
+
+	i2s_write_reg(dev->i2s_base, IER, 1);
+	i2s_enable_irqs(dev, substream->stream, config->chan_nr);
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(dev->i2s_base, ITER, 1);
+	else
+		i2s_write_reg(dev->i2s_base, IRER, 1);
+
+	i2s_write_reg(dev->i2s_base, CER, 1);
+}
+
+static void i2s_stop(struct i2svad_dev *dev,
+		struct snd_pcm_substream *substream)
+{
+
+	i2s_clear_irqs(dev, substream->stream);
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(dev->i2s_base, ITER, 0);
+	else
+		i2s_write_reg(dev->i2s_base, IRER, 0);
+
+	i2s_disable_irqs(dev, substream->stream, 8);
+
+	if (!dev->active) {
+		i2s_write_reg(dev->i2s_base, CER, 0);
+		i2s_write_reg(dev->i2s_base, IER, 0);
+	}
+}
+
+static int dw_i2s_startup(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *cpu_dai)
+{
+	struct i2svad_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
+	union dw_i2s_snd_dma_data *dma_data = NULL;
+
+
+	if (!(dev->capability & DWC_I2S_RECORD) &&
+			(substream->stream == SNDRV_PCM_STREAM_CAPTURE))
+		return -EINVAL;
+
+	if (!(dev->capability & DWC_I2S_PLAY) &&
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
+		return -EINVAL;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		dma_data = &dev->play_dma_data;
+	else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+		dma_data = &dev->capture_dma_data;
+
+	snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
+
+	return 0;
+}
+
+static void dw_i2s_config(struct i2svad_dev *dev, int stream)
+{
+	u32 ch_reg;
+	struct i2s_clk_config_data *config = &dev->config;
+
+
+	i2s_disable_channels(dev, stream);
+
+	for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
+		if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			i2s_write_reg(dev->i2s_base, TCR(ch_reg),
+					dev->xfer_resolution);
+			i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
+					dev->fifo_th - 1);
+			i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
+		} else {
+			i2s_write_reg(dev->i2s_base, RCR(ch_reg),
+					dev->xfer_resolution);
+			i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
+					dev->fifo_th - 1);
+			i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
+		}
+
+	}
+}
+
+static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
+		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+	struct i2svad_dev *dev = snd_soc_dai_get_drvdata(dai);
+	struct i2s_clk_config_data *config = &dev->config;
+	int ret;
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		config->data_width = 16;
+		dev->ccr = 0x00;
+		dev->xfer_resolution = 0x02;
+		break;
+
+	case SNDRV_PCM_FORMAT_S24_LE:
+		config->data_width = 24;
+		dev->ccr = 0x08;
+		dev->xfer_resolution = 0x04;
+		break;
+
+	case SNDRV_PCM_FORMAT_S32_LE:
+		config->data_width = 32;
+		dev->ccr = 0x10;
+		dev->xfer_resolution = 0x05;
+		break;
+
+	default:
+		dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
+		return -EINVAL;
+	}
+
+	config->chan_nr = params_channels(params);
+
+	switch (config->chan_nr) {
+	case EIGHT_CHANNEL_SUPPORT:
+	case SIX_CHANNEL_SUPPORT:
+	case FOUR_CHANNEL_SUPPORT:
+	case TWO_CHANNEL_SUPPORT:
+		break;
+	default:
+		dev_err(dev->dev, "channel not supported\n");
+		return -EINVAL;
+	}
+
+	dw_i2s_config(dev, substream->stream);
+
+	i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
+
+	config->sample_rate = params_rate(params);
+
+	if (dev->capability & DW_I2S_MASTER) {
+		if (dev->i2s_clk_cfg) {
+			ret = dev->i2s_clk_cfg(config);
+			if (ret < 0) {
+				dev_err(dev->dev, "runtime audio clk config fail\n");
+				return ret;
+			}
+		} else {
+			u32 bitclk = config->sample_rate *
+					config->data_width * 2;
+
+			ret = clk_set_rate(dev->clk, bitclk);
+			if (ret) {
+				dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
+					ret);
+				return ret;
+			}
+		}
+	}
+	return 0;
+}
+
+static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	snd_soc_dai_set_dma_data(dai, substream, NULL);
+}
+
+static int dw_i2s_prepare(struct snd_pcm_substream *substream,
+			struct snd_soc_dai *dai)
+{
+	struct i2svad_dev *dev = snd_soc_dai_get_drvdata(dai);
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		i2s_write_reg(dev->i2s_base, TXFFR, 1);
+	else
+		i2s_write_reg(dev->i2s_base, RXFFR, 1);
+
+	return 0;
+}
+
+static int dw_i2s_trigger(struct snd_pcm_substream *substream,
+		int cmd, struct snd_soc_dai *dai)
+{
+	struct i2svad_dev *dev = snd_soc_dai_get_drvdata(dai);
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		dev->active++;
+		i2s_start(dev, substream);
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		dev->active--;
+		i2s_stop(dev, substream);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
+	{
+		vad_trigger(&(dev->vad),cmd);
+	}
+	return ret;
+}
+
+static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
+{
+	struct i2svad_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
+	int ret = 0;
+
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBM_CFM:
+		if (dev->capability & DW_I2S_SLAVE)
+			ret = 0;
+		else
+			ret = -EINVAL;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFS:
+		if (dev->capability & DW_I2S_MASTER)
+			ret = 0;
+		else
+			ret = -EINVAL;
+		break;
+	case SND_SOC_DAIFMT_CBM_CFS:
+	case SND_SOC_DAIFMT_CBS_CFM:
+		ret = -EINVAL;
+		break;
+	default:
+		dev_dbg(dev->dev, "dwc : Invalid master/slave format\n");
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
+	.startup	= dw_i2s_startup,
+	.shutdown	= dw_i2s_shutdown,
+	.hw_params	= dw_i2s_hw_params,
+	.prepare	= dw_i2s_prepare,
+	.trigger	= dw_i2s_trigger,
+	.set_fmt	= dw_i2s_set_fmt,
+};
+
+#ifdef CONFIG_PM
+static int dw_i2s_runtime_suspend(struct device *dev)
+{
+	struct i2svad_dev *dw_dev = dev_get_drvdata(dev);
+
+	if (dw_dev->capability & DW_I2S_MASTER)
+		clk_disable(dw_dev->clk);
+	return 0;
+}
+
+static int dw_i2s_runtime_resume(struct device *dev)
+{
+	struct i2svad_dev *dw_dev = dev_get_drvdata(dev);
+
+	if (dw_dev->capability & DW_I2S_MASTER)
+		clk_enable(dw_dev->clk);
+	return 0;
+}
+
+static int dw_i2s_suspend(struct snd_soc_component *component)
+{
+	struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
+
+	if (dev->capability & DW_I2S_MASTER)
+		clk_disable(dev->clk);
+	return 0;
+}
+
+static int dw_i2s_resume(struct snd_soc_component *component)
+{
+	struct i2svad_dev *dev = snd_soc_component_get_drvdata(component);
+	struct snd_soc_dai *dai;
+	int stream;
+
+	if (dev->capability & DW_I2S_MASTER)
+		clk_enable(dev->clk);
+
+	for_each_component_dais(component, dai) {
+		for_each_pcm_streams(stream)
+			if (snd_soc_dai_stream_active(dai, stream))
+				dw_i2s_config(dev, stream);
+	}
+
+	return 0;
+}
+
+#else
+#define dw_i2s_suspend	NULL
+#define dw_i2s_resume	NULL
+#endif
+
+static int dw_i2svad_probe(struct snd_soc_component *component)
+{
+	vad_probe(component);
+	return 0;
+}
+
+static const struct snd_soc_component_driver dw_i2s_component = {
+	.name		= "dw-i2s",
+	.probe		= dw_i2svad_probe,
+	.suspend	= dw_i2s_suspend,
+	.resume		= dw_i2s_resume,
+};
+
+/*
+ * The following tables allow a direct lookup of various parameters
+ * defined in the I2S block's configuration in terms of sound system
+ * parameters.  Each table is sized to the number of entries possible
+ * according to the number of configuration bits describing an I2S
+ * block parameter.
+ */
+
+/* Maximum bit resolution of a channel - not uniformly spaced */
+static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
+	12, 16, 20, 24, 32, 0, 0, 0
+};
+
+/* Width of (DMA) bus */
+static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
+	DMA_SLAVE_BUSWIDTH_1_BYTE,
+	DMA_SLAVE_BUSWIDTH_2_BYTES,
+	DMA_SLAVE_BUSWIDTH_4_BYTES,
+	DMA_SLAVE_BUSWIDTH_UNDEFINED
+};
+
+/* PCM format to support channel resolution */
+static const u32 formats[COMP_MAX_WORDSIZE] = {
+	SNDRV_PCM_FMTBIT_S16_LE,
+	SNDRV_PCM_FMTBIT_S16_LE,
+	SNDRV_PCM_FMTBIT_S24_LE,
+	SNDRV_PCM_FMTBIT_S24_LE,
+	SNDRV_PCM_FMTBIT_S32_LE,
+	0,
+	0,
+	0
+};
+
+static const struct regmap_config sf_i2s_regmap_cfg = {
+	.reg_bits	= 32,
+	.val_bits	= 32,
+	.reg_stride	= 4,
+	.max_register	= 0x1000,
+};
+
+static int dw_configure_dai(struct i2svad_dev *dev,
+				struct snd_soc_dai_driver *dw_i2s_dai,
+				unsigned int rates)
+{
+	/*
+	 * Read component parameter registers to extract
+	 * the I2S block's configuration.
+	 */
+	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
+	u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
+	u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
+	u32 idx;
+
+	if (dev->capability & DWC_I2S_RECORD &&
+			dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
+		comp1 = comp1 & ~BIT(5);
+
+	if (dev->capability & DWC_I2S_PLAY &&
+			dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
+		comp1 = comp1 & ~BIT(6);
+
+	if (COMP1_TX_ENABLED(comp1)) {
+		dev_dbg(dev->dev, " designware: play supported\n");
+		idx = COMP1_TX_WORDSIZE_0(comp1);
+		if (WARN_ON(idx >= ARRAY_SIZE(formats)))
+			return -EINVAL;
+		if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+			idx = 1;
+		dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
+		dw_i2s_dai->playback.channels_max =
+				1 << (COMP1_TX_CHANNELS(comp1) + 1);
+		//dw_i2s_dai->playback.formats = formats[idx];
+		dw_i2s_dai->playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
+		dw_i2s_dai->playback.rates = rates;
+	}
+
+	if (COMP1_RX_ENABLED(comp1)) {
+		dev_dbg(dev->dev, "designware: record supported\n");
+		idx = COMP2_RX_WORDSIZE_0(comp2);
+		if (WARN_ON(idx >= ARRAY_SIZE(formats)))
+			return -EINVAL;
+		if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+			idx = 1;
+		dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
+		dw_i2s_dai->capture.channels_max =
+				1 << (COMP1_RX_CHANNELS(comp1) + 1);
+		//dw_i2s_dai->capture.formats = formats[idx];
+		dw_i2s_dai->capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
+		dw_i2s_dai->capture.rates = rates;
+	}
+
+	if (COMP1_MODE_EN(comp1)) {
+		dev_dbg(dev->dev, "designware: i2s master mode supported\n");
+		dev->capability |= DW_I2S_MASTER;
+	} else {
+		dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
+		dev->capability |= DW_I2S_SLAVE;
+	}
+
+	dev->fifo_th = fifo_depth / 2;
+	return 0;
+}
+
+static int dw_configure_dai_by_pd(struct i2svad_dev *dev,
+				struct snd_soc_dai_driver *dw_i2s_dai,
+				struct resource *res,
+				const struct i2s_platform_data *pdata)
+{
+	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
+	u32 idx = COMP1_APB_DATA_WIDTH(comp1);
+	int ret;
+
+	if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
+		return -EINVAL;
+
+	ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
+	if (ret < 0)
+		return ret;
+
+	if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
+		idx = 1;
+	/* Set DMA slaves info */
+	dev->play_dma_data.pd.data = pdata->play_dma_data;
+	dev->capture_dma_data.pd.data = pdata->capture_dma_data;
+	dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
+	dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
+	dev->play_dma_data.pd.max_burst = 16;
+	dev->capture_dma_data.pd.max_burst = 16;
+	dev->play_dma_data.pd.addr_width = bus_widths[idx];
+	dev->capture_dma_data.pd.addr_width = bus_widths[idx];
+	dev->play_dma_data.pd.filter = pdata->filter;
+	dev->capture_dma_data.pd.filter = pdata->filter;
+
+	return 0;
+}
+
+static int dw_configure_dai_by_dt(struct i2svad_dev *dev,
+				struct snd_soc_dai_driver *dw_i2s_dai,
+				struct resource *res)
+{
+	u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
+	u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
+	u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
+	u32 idx = COMP1_APB_DATA_WIDTH(comp1);
+	u32 idx2;
+	int ret;
+
+	if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
+		return -EINVAL;
+
+	ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
+	if (ret < 0)
+		return ret;
+
+	if (COMP1_TX_ENABLED(comp1)) {
+		idx2 = COMP1_TX_WORDSIZE_0(comp1);
+
+		dev->capability |= DWC_I2S_PLAY;
+		dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
+		dev->play_dma_data.dt.addr_width = bus_widths[idx];
+		dev->play_dma_data.dt.fifo_size = fifo_depth *
+			(fifo_width[idx2]) >> 8;
+		dev->play_dma_data.dt.maxburst = 16;
+	}
+	if (COMP1_RX_ENABLED(comp1)) {
+		idx2 = COMP2_RX_WORDSIZE_0(comp2);
+
+		dev->capability |= DWC_I2S_RECORD;
+		dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
+		dev->capture_dma_data.dt.addr_width = bus_widths[idx];
+		dev->capture_dma_data.dt.fifo_size = fifo_depth *
+			(fifo_width[idx2] >> 8);
+		dev->capture_dma_data.dt.maxburst = 16;
+	}
+
+	return 0;
+
+}
+
+static int dw_i2s_probe(struct platform_device *pdev)
+{
+	const struct i2s_platform_data *pdata = pdev->dev.platform_data;
+	struct i2svad_dev *dev;
+	struct resource *res;
+	int ret, irq;
+	struct snd_soc_dai_driver *dw_i2s_dai;
+	const char *clk_id;
+
+	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
+	if (!dw_i2s_dai)
+		return -ENOMEM;
+
+	dw_i2s_dai->ops = &dw_i2s_dai_ops;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(dev->i2s_base))
+		return PTR_ERR(dev->i2s_base);
+
+	dev->vad.vad_base = dev->i2s_base;
+	dev->vad.vad_map = devm_regmap_init_mmio(&pdev->dev, dev->i2s_base, &sf_i2s_regmap_cfg);
+	if (IS_ERR(dev->vad.vad_map)) {
+		dev_err(&pdev->dev, "failed to init regmap: %ld\n",
+			PTR_ERR(dev->vad.vad_map));
+		return PTR_ERR(dev->vad.vad_map);
+	}
+
+	dev->dev = &pdev->dev;
+
+	dev->clk_apb_i2svad = devm_clk_get(&pdev->dev, "i2svad_apb");
+	if (IS_ERR(dev->clk_apb_i2svad))
+		return dev_err_probe(&pdev->dev, PTR_ERR(dev->clk_apb_i2svad),
+				     "failed to get apb clock\n");
+
+	dev->rst_apb_i2svad = devm_reset_control_get_exclusive(&pdev->dev, "apb_i2svad");
+	if (IS_ERR(dev->rst_apb_i2svad))
+		return dev_err_probe(&pdev->dev, PTR_ERR(dev->rst_apb_i2svad),
+				     "failed to get apb reset\n");
+
+	dev->rst_i2svad_srst = devm_reset_control_get_exclusive(&pdev->dev, "i2svad_srst");
+	if (IS_ERR(dev->rst_i2svad_srst))
+		return dev_err_probe(&pdev->dev, PTR_ERR(dev->rst_i2svad_srst),
+				     "failed to get source reset\n");
+
+	ret = clk_prepare_enable(dev->clk_apb_i2svad);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "failed to enable apb clock\n");
+
+	ret = reset_control_deassert(dev->rst_apb_i2svad);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "failed to deassert apb reset\n");
+
+	ret = reset_control_deassert(dev->rst_i2svad_srst);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "failed to deassert source reset\n");
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq >= 0) {
+		ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
+				pdev->name, dev);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "failed to request irq\n");
+			return ret;
+		}
+	}
+
+	dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
+	dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
+	if (pdata) {
+		dev->capability = pdata->cap;
+		clk_id = NULL;
+		dev->quirks = pdata->quirks;
+		if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
+			dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
+			dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
+		}
+		ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
+	} else {
+		clk_id = "i2sclk";
+		ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
+	}
+	if (ret < 0)
+		return ret;
+
+	if (dev->capability & DW_I2S_MASTER) {
+		if (pdata) {
+			dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
+			if (!dev->i2s_clk_cfg) {
+				dev_err(&pdev->dev, "no clock configure method\n");
+				return -ENODEV;
+			}
+		}
+		dev->clk = devm_clk_get(&pdev->dev, clk_id);
+
+		if (IS_ERR(dev->clk))
+			return PTR_ERR(dev->clk);
+
+		ret = clk_prepare_enable(dev->clk);
+		if (ret < 0)
+			return ret;
+	}
+
+	dev_set_drvdata(&pdev->dev, dev);
+	ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
+					 dw_i2s_dai, 1);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "not able to register dai\n");
+		goto err_clk_disable;
+	}
+
+	if (!pdata) {
+		if (irq >= 0) {
+			ret = i2svad_pcm_register(pdev);
+			dev->use_pio = true;
+		} else {
+			ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
+					0);
+			dev->use_pio = false;
+		}
+
+		if (ret) {
+			dev_err(&pdev->dev, "could not register pcm: %d\n",
+					ret);
+			goto err_clk_disable;
+		}
+	}
+
+	vad_init(&(dev->vad));
+	pm_runtime_enable(&pdev->dev);
+
+	return 0;
+
+err_clk_disable:
+	if (dev->capability & DW_I2S_MASTER)
+		clk_disable_unprepare(dev->clk);
+	return ret;
+}
+
+static int dw_i2s_remove(struct platform_device *pdev)
+{
+	struct i2svad_dev *dev = dev_get_drvdata(&pdev->dev);
+
+	if (dev->capability & DW_I2S_MASTER)
+		clk_disable_unprepare(dev->clk);
+
+	pm_runtime_disable(&pdev->dev);
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id dw_i2s_of_match[] = {
+	{ .compatible = "starfive,sf-i2svad", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
+#endif
+
+static const struct dev_pm_ops dwc_pm_ops = {
+	SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
+};
+
+static struct platform_driver dw_i2s_driver = {
+	.probe		= dw_i2s_probe,
+	.remove		= dw_i2s_remove,
+	.driver		= {
+		.name	= "sf-i2svad",
+		.of_match_table = of_match_ptr(dw_i2s_of_match),
+		.pm = &dwc_pm_ops,
+	},
+};
+
+module_platform_driver(dw_i2s_driver);
+
+MODULE_AUTHOR("jenny zhang <jenny.zhang@starfivetech.com>");
+MODULE_DESCRIPTION("starfive I2SVAD SoC Interface");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:sf-i2svad");
diff --git a/sound/soc/starfive/i2svad.h b/sound/soc/starfive/i2svad.h
new file mode 100644
index 000000000000..cd14cb4ce813
--- /dev/null
+++ b/sound/soc/starfive/i2svad.h
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef __SND_SOC_STARFIVE_I2SVAD_H
+#define __SND_SOC_STARFIVE_I2SVAD_H
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/reset.h>
+#include <linux/types.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm.h>
+#include <sound/designware_i2s.h>
+
+/* common register for all channel */
+#define IER		0x000
+#define IRER		0x004
+#define ITER		0x008
+#define CER		0x00C
+#define CCR		0x010
+#define RXFFR		0x014
+#define TXFFR		0x018
+
+/* Interrupt status register fields */
+#define ISR_TXFO	BIT(5)
+#define ISR_TXFE	BIT(4)
+#define ISR_RXFO	BIT(1)
+#define ISR_RXDA	BIT(0)
+
+/* I2STxRxRegisters for all channels */
+#define LRBR_LTHR(x)	(0x40 * x + 0x020)
+#define RRBR_RTHR(x)	(0x40 * x + 0x024)
+#define RER(x)		(0x40 * x + 0x028)
+#define TER(x)		(0x40 * x + 0x02C)
+#define RCR(x)		(0x40 * x + 0x030)
+#define TCR(x)		(0x40 * x + 0x034)
+#define ISR(x)		(0x40 * x + 0x038)
+#define IMR(x)		(0x40 * x + 0x03C)
+#define ROR(x)		(0x40 * x + 0x040)
+#define TOR(x)		(0x40 * x + 0x044)
+#define RFCR(x)		(0x40 * x + 0x048)
+#define TFCR(x)		(0x40 * x + 0x04C)
+#define RFF(x)		(0x40 * x + 0x050)
+#define TFF(x)		(0x40 * x + 0x054)
+
+/* I2SCOMPRegisters */
+#define I2S_COMP_PARAM_2	0x01F0
+#define I2S_COMP_PARAM_1	0x01F4
+#define I2S_COMP_VERSION	0x01F8
+#define I2S_COMP_TYPE		0x01FC
+
+/* VAD Registers */
+#define VAD_LEFT_MARGIN				0x800  /* left_margin */
+#define VAD_RIGHT_MARGIN			0x804  /* right_margin */
+#define VAD_N_LOW_CONT_FRAMES			0x808  /* low-energy transition range threshold ——NL*/
+#define VAD_N_LOW_SEEK_FRAMES			0x80C  /* low-energy transition range */
+#define VAD_N_HIGH_CONT_FRAMES			0x810  /* high-energy transition range threshold——NH */
+#define VAD_N_HIGH_SEEK_FRAMES			0x814  /* high-energy transition range */
+#define VAD_N_SPEECH_LOW_HIGH_FRAMES		0x818  /* low-energy voice range threshold——NVL*/
+#define VAD_N_SPEECH_LOW_SEEK_FRAMES		0x81C  /* low-energy voice range*/
+#define VAD_MEAN_SIL_FRAMES			0x820  /* mean silence frame range*/
+#define VAD_N_ALPHA				0x824  /* low-energy threshold scaling factor,12bit(0~0xFFF)*/
+#define VAD_N_BETA				0x828  /* high-energy threshold scaling factor,12bit(0~0xFFF)*/
+#define VAD_FIFO_DEPTH				0x82C  /* status register for VAD */
+#define VAD_LR_SEL				0x840  /* L/R channel data selection for processing */
+#define VAD_SW					0x844  /* push enable signal*/
+#define VAD_LEFT_WD				0x848  /* select left channel*/
+#define VAD_RIGHT_WD				0x84C  /* select right channel*/
+#define VAD_STOP_DELAY				0x850  /* delay stop for 0-3 samples*/
+#define VAD_ADDR_START				0x854  /* vad memory start address, align with 64bit*/
+#define VAD_ADDR_WRAP				0x858  /* vad memory highest address for Push, align with 64bit,(addr_wrap-1) is the max physical address*/
+#define VAD_MEM_SW				0x85C  /* xmem switch */
+#define VAD_SPINT_CLR				0x860  /* clear vad_spint interrup status*/
+#define VAD_SPINT_EN				0x864  /* disable/enable vad_spint from vad_flag rising edge*/
+#define VAD_SLINT_CLR				0x868  /* clear vad_slint interrup status*/
+#define VAD_SLINT_EN				0x86C  /* disable/enable  vad_slint from vad_flag falling edge*/
+#define VAD_RAW_SPINT				0x870  /* status of spint before vad_spint_en*/
+#define VAD_RAW_SLINT				0x874  /* status of slint before vad_slint_en*/
+#define VAD_SPINT				0x878  /* status of spint after vad_spint_en*/
+#define VAD_SLINT				0x87C  /* status of slint before vad_slint_en*/
+#define VAD_XMEM_ADDR				0x880  /* next xmem address ,align to 16bi*/
+#define VAD_I2S_CTRL_REG_ADDR			0x884
+
+/*
+ * vad parameter register fields
+ */
+#define VAD_LEFT_MARGIN_MASK			GENMASK(4, 0)
+#define VAD_RIGHT_MARGIN_MASK			GENMASK(4, 0)
+#define VAD_N_LOW_CONT_FRAMES_MASK		GENMASK(4, 0)
+#define VAD_N_LOW_SEEK_FRAMES_MASK		GENMASK(4, 0)
+#define VAD_N_HIGH_CONT_FRAMES_MASK		GENMASK(4, 0)
+#define VAD_N_HIGH_SEEK_FRAMES_MASK		GENMASK(4, 0)
+#define VAD_N_SPEECH_LOW_HIGH_FRAMES_MASK	GENMASK(4, 0)
+#define VAD_N_SPEECH_LOW_SEEK_FRAMES_MASK	GENMASK(4, 0)
+#define VAD_MEAN_SIL_FRAMES_MASK		GENMASK(4, 0)
+#define VAD_N_ALPHA_MASK			GENMASK(11, 0)
+#define VAD_N_BETA_MASK				GENMASK(11, 0)
+#define VAD_LR_SEL_MASK				GENMASK(0, 0)
+#define VAD_LR_SEL_L				(0 << 0)
+#define VAD_LR_SEL_R				(1 << 0)
+
+#define VAD_SW_MASK				GENMASK(1, 0)
+#define VAD_SW_VAD_XMEM_ENABLE			(1 << 0)
+#define VAD_SW_VAD_XMEM_DISABLE			(0 << 0)
+#define VAD_SW_ADC_ENABLE			(1 << 1)
+#define VAD_SW_ADC_DISABLE			(0 << 1)
+
+
+#define VAD_LEFT_WD_MASK			GENMASK(0, 0)
+#define VAD_LEFT_WD_BIT_31_16			(1 << 1)
+#define VAD_LEFT_WD_BIT_15_0			(0 << 1)
+
+
+#define VAD_RIGHT_WD_MASK			GENMASK(0, 0)
+#define VAD_RIGHT_WD_BIT_31_16			(1 << 1)
+#define VAD_RIGHT_WD_BIT_15_0			(0 << 1)
+
+
+#define VAD_STOP_DELAY_MASK			GENMASK(1, 0)
+#define VAD_STOP_DELAY_0_SAMPLE			0
+#define VAD_STOP_DELAY_1_SAMPLE			1
+#define VAD_STOP_DELAY_2_SAMPLE			2
+#define VAD_STOP_DELAY_3_SAMPLE			3
+
+#define VAD_ADDR_START_MASK			GENMASK(12, 0)
+#define VAD_ADDR_WRAP_MASK			GENMASK(13, 0)
+#define VAD_MEM_SW_MASK				GENMASK(0, 0)
+#define VAD_SPINT_CLR_MASK			GENMASK(0, 0)
+#define VAD_SPINT_EN_MASK			GENMASK(0, 0)
+#define VAD_SLINT_CLR_MASK			GENMASK(0, 0)
+#define VAD_SLINT_EN_MASK			GENMASK(0, 0)
+#define VAD_I2S_CTRL_REG_ADDR_MASK		GENMASK(0, 0)
+
+#define VAD_MEM_SW_TO_VAD			(1 << 0)
+#define VAD_MEM_SW_TO_AXI			(0 << 0)
+
+#define VAD_SPINT_CLR_VAD_SPINT			(1 << 0)
+
+#define VAD_SPINT_EN_ENABLE			(1 << 0)
+#define VAD_SPINT_EN_DISABLE			(0 << 0)
+
+#define VAD_SLINT_CLR_VAD_SLINT			(1 << 0)
+
+#define VAD_SLINT_EN_ENABLE			(1 << 0)
+#define VAD_SLINT_EN_DISABLE			(0 << 0)
+
+#define VAD_STATUS_NORMAL			0
+#define VAD_STATUS_SPINT			1
+#define VAD_STATUS_SLINT			2
+
+/*
+ * Component parameter register fields - define the I2S block's
+ * configuration.
+ */
+#define COMP1_TX_WORDSIZE_3(r)		(((r) & GENMASK(27, 25)) >> 25)
+#define COMP1_TX_WORDSIZE_2(r)		(((r) & GENMASK(24, 22)) >> 22)
+#define COMP1_TX_WORDSIZE_1(r)		(((r) & GENMASK(21, 19)) >> 19)
+#define COMP1_TX_WORDSIZE_0(r)		(((r) & GENMASK(18, 16)) >> 16)
+#define COMP1_TX_CHANNELS(r)		(((r) & GENMASK(10, 9)) >> 9)
+#define COMP1_RX_CHANNELS(r)		(((r) & GENMASK(8, 7)) >> 7)
+#define COMP1_RX_ENABLED(r)		(((r) & BIT(6)) >> 6)
+#define COMP1_TX_ENABLED(r)		(((r) & BIT(5)) >> 5)
+#define COMP1_MODE_EN(r)		(((r) & BIT(4)) >> 4)
+#define COMP1_FIFO_DEPTH_GLOBAL(r)	(((r) & GENMASK(3, 2)) >> 2)
+#define COMP1_APB_DATA_WIDTH(r)		(((r) & GENMASK(1, 0)) >> 0)
+
+#define COMP2_RX_WORDSIZE_3(r)		(((r) & GENMASK(12, 10)) >> 10)
+#define COMP2_RX_WORDSIZE_2(r)		(((r) & GENMASK(9, 7)) >> 7)
+#define COMP2_RX_WORDSIZE_1(r)		(((r) & GENMASK(5, 3)) >> 3)
+#define COMP2_RX_WORDSIZE_0(r)		(((r) & GENMASK(2, 0)) >> 0)
+
+/* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
+#define COMP_MAX_WORDSIZE		(1 << 3)
+#define COMP_MAX_DATA_WIDTH		(1 << 2)
+
+#define MAX_CHANNEL_NUM		8
+#define MIN_CHANNEL_NUM		2
+#define ALL_CHANNEL_NUM		4
+
+
+union dw_i2s_snd_dma_data {
+	struct i2s_dma_data pd;
+	struct snd_dmaengine_dai_dma_data dt;
+};
+
+struct vad_params {
+	void __iomem *vad_base;
+	struct regmap *vad_map;
+	unsigned int vswitch;
+	unsigned int vstatus; /*vad detect status: 1:SPINT 2:SLINT 0:normal*/
+};
+
+struct i2svad_dev {
+	void __iomem *i2s_base;
+	struct clk *clk;
+	int active;
+	unsigned int capability;
+	unsigned int quirks;
+	unsigned int i2s_reg_comp1;
+	unsigned int i2s_reg_comp2;
+	struct device *dev;
+	u32 ccr;
+	u32 xfer_resolution;
+	u32 fifo_th;
+
+	struct clk *clk_apb_i2svad;
+	struct reset_control *rst_apb_i2svad;
+	struct reset_control *rst_i2svad_srst;
+
+	/* data related to DMA transfers b/w i2s and DMAC */
+	union dw_i2s_snd_dma_data play_dma_data;
+	union dw_i2s_snd_dma_data capture_dma_data;
+	struct i2s_clk_config_data config;
+	int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
+
+	/* data related to PIO transfers */
+	bool use_pio;
+	struct snd_pcm_substream __rcu *tx_substream;
+	struct snd_pcm_substream __rcu *rx_substream;
+	unsigned int (*tx_fn)(struct i2svad_dev *dev,
+			struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
+			bool *period_elapsed);
+	unsigned int (*rx_fn)(struct i2svad_dev *dev,
+			struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
+			bool *period_elapsed);
+	unsigned int tx_ptr;
+	unsigned int rx_ptr;
+
+	struct vad_params vad;
+};
+
+#if IS_ENABLED(CONFIG_SND_STARFIVE_I2SVAD_PCM)
+void i2svad_pcm_push_tx(struct i2svad_dev *dev);
+void i2svad_pcm_pop_rx(struct i2svad_dev *dev);
+int i2svad_pcm_register(struct platform_device *pdev);
+#else
+static inline void i2svad_pcm_push_tx(struct i2svad_dev *dev) { }
+static inline void i2svad_pcm_pop_rx(struct i2svad_dev *dev) { }
+static inline int i2svad_pcm_register(struct platform_device *pdev)
+{
+	return -EINVAL;
+}
+#endif
+
+#endif
diff --git a/sound/soc/starfive/pdm.c b/sound/soc/starfive/pdm.c
new file mode 100644
index 000000000000..af5efd8adfb7
--- /dev/null
+++ b/sound/soc/starfive/pdm.c
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <sound/soc.h>
+#include <sound/soc-dai.h>
+#include <sound/pcm_params.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+
+#include "pdm.h"
+
+#define AUDIOC_CLK 	(12288000)
+#define PDM_MUL 	(128)
+
+struct sf_pdm {
+	struct regmap *pdm_map;
+	struct regmap *clk_map;
+	struct clk *clk;
+};
+
+static const DECLARE_TLV_DB_SCALE(volume_tlv, -9450, 150, 0);
+
+static const struct snd_kcontrol_new sf_pdm_snd_controls[] = {
+	SOC_SINGLE("DC compensation Control", PDM_DMIC_CTRL0, 30, 1, 0),
+	SOC_SINGLE("High Pass Filter Control", PDM_DMIC_CTRL0, 28, 1, 0),
+	SOC_SINGLE("Left Channel Volume Control", PDM_DMIC_CTRL0, 23, 1, 0),
+	SOC_SINGLE("Right Channel Volume Control", PDM_DMIC_CTRL0, 22, 1, 0),
+	SOC_SINGLE_TLV("Volume", PDM_DMIC_CTRL0, 16, 0x3F, 1, volume_tlv),
+	SOC_SINGLE("Data MSB Shift", PDM_DMIC_CTRL0, 1, 7, 0),
+	SOC_SINGLE("SCALE", PDM_DC_SCALE0, 0, 0x3F, 0),
+	SOC_SINGLE("DC offset", PDM_DC_SCALE0, 8, 0xFFFFF, 0),
+};
+
+static int sf_pdm_set_mclk(struct regmap *map, unsigned int clk, unsigned int weight)
+{
+	int mclk_div,bclk_div,lrclk_div;
+	u32	pdm_div;
+
+	/*
+	audio source clk:12288000, mclk_div:4, mclk:3M
+	support 8K/16K/32K/48K sample reate
+	suapport 16/24/32 bit weight
+	bit weight 32
+	mclk bclk  lrclk
+	3M   1.5M  48K
+	3M   1M    32K
+	3M   0.5M  16K
+	3M   0.25M  8K
+
+	bit weight 24,set lrclk_div as 32
+	mclk bclk  lrclk
+	3M   1.5M  48K
+	3M   1M    32K
+	3M   0.5M  16K
+	3M   0.25M  8K
+
+	bit weight 16
+	mclk bclk   lrclk
+	3M   0.75M  48K
+	3M   0.5M   32K
+	3M   0.25M  16K
+	3M   0.125M 8K
+	*/
+
+	switch (clk) {
+	case 8000:
+	case 16000:
+	case 32000:
+	case 48000:
+		break;
+	default:
+		printk(KERN_ERR "sample rate:%d\n", clk);
+		return -EINVAL;
+	}
+
+	switch (weight) {
+	case 16:
+	case 24:
+	case 32:
+		break;
+	default:
+		printk(KERN_ERR "bit weight:%d\n", weight);
+		return -EINVAL;
+	}
+
+	if (24 == weight) {
+		weight = 32;
+	}
+
+	mclk_div = 4;
+	bclk_div = AUDIOC_CLK/mclk_div/(clk*weight);
+	lrclk_div = weight;
+
+	/* PDM MCLK = 128*LRCLK */
+	pdm_div = AUDIOC_CLK/(PDM_MUL*clk);
+
+	regmap_update_bits(map, AUDIO_CLK_ADC_MCLK, 0x0F, mclk_div);
+	regmap_update_bits(map, AUDIO_CLK_I2SADC_BCLK, 0x1F, bclk_div);
+	regmap_update_bits(map, AUDIO_CLK_ADC_LRCLK, 0x3F, lrclk_div);
+	regmap_update_bits(map, AUDIO_CLK_PDM_CLK, 0x0F, pdm_div);
+
+	return 0;
+}
+
+static void sf_pdm_enable(struct regmap *map)
+{
+	/* Enable PDM */
+	regmap_update_bits(map, PDM_DMIC_CTRL0, 0x01<<PDM_DMIC_RVOL_OFFSET, 0);
+	regmap_update_bits(map, PDM_DMIC_CTRL0, 0x01<<PDM_DMIC_LVOL_OFFSET, 0);
+}
+
+static void sf_pdm_disable(struct regmap *map)
+{
+	regmap_update_bits(map, PDM_DMIC_CTRL0,
+		0x01<<PDM_DMIC_RVOL_OFFSET, 0x01<<PDM_DMIC_RVOL_OFFSET);
+	regmap_update_bits(map, PDM_DMIC_CTRL0,
+		0x01<<PDM_DMIC_LVOL_OFFSET, 0x01<<PDM_DMIC_LVOL_OFFSET);
+}
+
+static int sf_pdm_trigger(struct snd_pcm_substream *substream, int cmd,
+			struct snd_soc_dai *dai)
+{
+	struct sf_pdm *priv = snd_soc_dai_get_drvdata(dai);
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		sf_pdm_enable(priv->pdm_map);
+		return 0;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		sf_pdm_disable(priv->pdm_map);
+		return 0;
+
+	default:
+		return -EINVAL;
+	}
+}
+
+static int sf_pdm_hw_params(struct snd_pcm_substream *substream,
+			struct snd_pcm_hw_params *params,
+			struct snd_soc_dai *dai)
+{
+	struct sf_pdm *priv = snd_soc_dai_get_drvdata(dai);
+	unsigned int rate = params_rate(params);
+	unsigned int width;
+	int ret;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		return 0;
+
+	width = params_width(params);
+	switch (width) {
+	case 16:
+	case 24:
+	case 32:
+		break;
+	default:
+		dev_err(dai->dev, "unsupported sample width\n");
+		return -EINVAL;
+	}
+
+	ret = sf_pdm_set_mclk(priv->clk_map, rate, width);
+	if (ret < 0) {
+		dev_err(dai->dev, "unsupported sample rate\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct snd_soc_dai_ops sf_pdm_dai_ops = {
+	.trigger	= sf_pdm_trigger,
+	.hw_params	= sf_pdm_hw_params,
+};
+
+static int sf_pdm_dai_probe(struct snd_soc_dai *dai)
+{
+	struct sf_pdm *priv = snd_soc_dai_get_drvdata(dai);
+
+	/* Reset */
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x01<<PDM_DMIC_SW_RSTN_OFFSET, 0x00);
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x01<<PDM_DMIC_SW_RSTN_OFFSET, 0x01<<PDM_DMIC_SW_RSTN_OFFSET);
+
+	/* Make sure the device is initially disabled */
+	sf_pdm_disable(priv->pdm_map);
+
+	/* MUTE */
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x3F<<PDM_DMIC_VOL_OFFSET, 0x3F<<PDM_DMIC_VOL_OFFSET);
+
+	/* UNMUTE */
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x3F<<PDM_DMIC_VOL_OFFSET, 0);
+
+	/* enable high pass filter */
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x01<<PDM_DMIC_ENHPF_OFFSET, 0x01<<PDM_DMIC_ENHPF_OFFSET);
+
+	/* i2s slaver mode */
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x01<<PDM_DMIC_I2SMODE_OFFSET, 0x01<<PDM_DMIC_I2SMODE_OFFSET);
+
+	/* disable fast mode */
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x01<<PDM_DMIC_FASTMODE_OFFSET, 0);
+
+	/* enable dc bypass mode */
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x01<<PDM_DMIC_DCBPS_OFFSET, 0);
+
+	/* dmic msb shift 0 */
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x07<<PDM_DMIC_MSB_SHIFT_OFFSET, 0);
+
+	/* scale:0 */
+	regmap_update_bits(priv->pdm_map, PDM_DC_SCALE0, 0x3F, 0x08);
+
+	/* DC offset:0 */
+	regmap_update_bits(priv->pdm_map, PDM_DC_SCALE0,
+		0xFFFFF<<PDM_DMIC_DCOFF1_OFFSET, 0xC0005<<PDM_DMIC_DCOFF1_OFFSET);
+
+	return 0;
+}
+
+static int sf_pdm_dai_remove(struct snd_soc_dai *dai)
+{
+	struct sf_pdm *priv = snd_soc_dai_get_drvdata(dai);
+
+	/* MUTE */
+	regmap_update_bits(priv->pdm_map, PDM_DMIC_CTRL0,
+		0x3F<<PDM_DMIC_VOL_OFFSET, 0x3F<<PDM_DMIC_VOL_OFFSET);
+
+	return 0;
+}
+
+#define SF_PCM_RATE (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|\
+					SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_48000)
+
+static struct snd_soc_dai_driver sf_pdm_dai_drv = {
+	.name = "PDM",
+	.id = 0,
+	.capture = {
+		.stream_name	= "Capture",
+		.channels_min	= 2,
+		.channels_max	= 2,
+		.rates		= 	SF_PCM_RATE,
+		.formats	= 	SNDRV_PCM_FMTBIT_S16_LE|\
+						SNDRV_PCM_FMTBIT_S24_LE|\
+						SNDRV_PCM_FMTBIT_S32_LE,
+	},
+	.ops		= &sf_pdm_dai_ops,
+	.probe		= sf_pdm_dai_probe,
+	.remove		= sf_pdm_dai_remove,
+	.symmetric_rate = 1,
+};
+
+static int pdm_probe(struct snd_soc_component *component)
+{
+	struct sf_pdm *priv = snd_soc_component_get_drvdata(component);
+
+	snd_soc_component_init_regmap(component, priv->pdm_map);
+	snd_soc_add_component_controls(component, sf_pdm_snd_controls,
+				ARRAY_SIZE(sf_pdm_snd_controls));
+
+	return 0;
+}
+
+static const struct snd_soc_component_driver sf_pdm_component_drv = {
+	.name = "sf-pdm",
+	.probe = pdm_probe,
+};
+
+static const struct regmap_config sf_pdm_regmap_cfg = {
+	.reg_bits	= 32,
+	.val_bits	= 32,
+	.reg_stride	= 4,
+	.max_register	= 0x20,
+};
+
+static const struct regmap_config sf_audio_clk_regmap_cfg = {
+	.reg_bits	= 32,
+	.val_bits	= 32,
+	.reg_stride	= 4,
+	.max_register	= 0x100,
+};
+
+static int sf_pdm_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct sf_pdm *priv;
+	struct resource *res;
+	void __iomem *regs;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+	platform_set_drvdata(pdev, priv);
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pdm");
+	regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	priv->pdm_map = devm_regmap_init_mmio(dev, regs, &sf_pdm_regmap_cfg);
+	if (IS_ERR(priv->pdm_map)) {
+		dev_err(dev, "failed to init regmap: %ld\n",
+			PTR_ERR(priv->pdm_map));
+		return PTR_ERR(priv->pdm_map);
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "audio-clk");
+	regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	priv->clk_map = devm_regmap_init_mmio(dev, regs, &sf_audio_clk_regmap_cfg);
+	if (IS_ERR(priv->clk_map)) {
+		dev_err(dev, "failed to init regmap: %ld\n",
+			PTR_ERR(priv->clk_map));
+		return PTR_ERR(priv->clk_map);
+	}
+
+	return devm_snd_soc_register_component(dev, &sf_pdm_component_drv,
+					&sf_pdm_dai_drv, 1);
+}
+
+static int sf_pdm_dev_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+static const struct of_device_id sf_pdm_of_match[] = {
+	{.compatible = "starfive,sf-pdm",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, sf_pdm_of_match);
+
+static struct platform_driver sf_pdm_driver = {
+
+	.driver = {
+		.name = "sf-pdm",
+		.of_match_table = sf_pdm_of_match,
+	},
+	.probe = sf_pdm_probe,
+	.remove = sf_pdm_dev_remove,
+};
+module_platform_driver(sf_pdm_driver);
+
+MODULE_AUTHOR("michael.yan <michael.yan@starfivetech.com>");
+MODULE_DESCRIPTION("starfive PDM Controller Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/starfive/pdm.h b/sound/soc/starfive/pdm.h
new file mode 100644
index 000000000000..cbc0a9ecd378
--- /dev/null
+++ b/sound/soc/starfive/pdm.h
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef __SND_SOC_STARFIVE_PDM_H
+#define __SND_SOC_STARFIVE_PDM_H
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/types.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm.h>
+#include <linux/dmaengine.h>
+#include <linux/types.h>
+
+#define PDM_DMIC_CTRL0			(0x00)
+#define PDM_DC_SCALE0			(0x04)
+#define PDM_DMIC_CTRL1			(0x10)
+#define PDM_DC_SCALE1			(0x14)
+
+/* PDM CTRL OFFSET */
+#define PDM_DMIC_MSB_SHIFT_OFFSET	(1)
+#define PDM_DMIC_VOL_OFFSET		(16)
+#define PDM_DMIC_RVOL_OFFSET		(22)
+#define PDM_DMIC_LVOL_OFFSET		(23)
+#define PDM_DMIC_I2SMODE_OFFSET		(24)
+#define PDM_DMIC_ENHPF_OFFSET		(28)
+#define PDM_DMIC_FASTMODE_OFFSET	(29)
+#define PDM_DMIC_DCBPS_OFFSET		(30)
+#define PDM_DMIC_SW_RSTN_OFFSET		(31)
+
+/* PDM SCALE OFFSET */
+#define PDM_DMIC_DCOFF3_OFFSET		(24)
+#define PDM_DMIC_DCOFF2_OFFSET		(16)
+#define PDM_DMIC_DCOFF1_OFFSET		(8)
+#define PDM_DMIC_SCALE_OFFSET		(0)
+
+#define AUDIO_CLK_ADC_MCLK		0x0
+#define AUDIO_CLK_I2SADC_BCLK		0xC
+#define AUDIO_CLK_ADC_LRCLK		0x14
+#define AUDIO_CLK_PDM_CLK		0x1C
+
+#endif /* __SND_SOC_STARFIVE_PDM_H */
diff --git a/sound/soc/starfive/pwmdac-pcm.c b/sound/soc/starfive/pwmdac-pcm.c
new file mode 100644
index 000000000000..decd08bc289e
--- /dev/null
+++ b/sound/soc/starfive/pwmdac-pcm.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/io.h>
+#include <linux/rcupdate.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include "pwmdac.h"
+
+#define BUFFER_BYTES_MAX	(3 * 2 * 8 * PERIOD_BYTES_MIN)
+#define PERIOD_BYTES_MIN	4096
+#define PERIODS_MIN		2
+
+static unsigned int sf_pwmdac_pcm_tx_8(struct sf_pwmdac_dev *dev,
+		struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
+		bool *period_elapsed)
+{
+	const u8 (*p)[2] = (void *)runtime->dma_area;
+	unsigned int period_pos = tx_ptr % runtime->period_size;
+	int i;
+	u32 basedat = 0;
+
+	for (i = 0; i < dev->fifo_th; i++) {
+		basedat = (p[tx_ptr][0]<<8)|(p[tx_ptr][1] << 24);
+		iowrite32(basedat,dev->pwmdac_base + PWMDAC_WDATA);
+		period_pos++;
+		if (++tx_ptr >= runtime->buffer_size)
+			tx_ptr = 0;
+	}
+
+	*period_elapsed = period_pos >= runtime->period_size;
+
+	return tx_ptr;
+}
+
+
+static unsigned int sf_pwmdac_pcm_tx_16(struct sf_pwmdac_dev *dev,
+		struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
+		bool *period_elapsed)
+{
+	const u16 (*p)[2] = (void *)runtime->dma_area;
+	unsigned int period_pos = tx_ptr % runtime->period_size;
+	int i;
+	u32 basedat = 0;
+
+	for (i = 0; i < dev->fifo_th; i++) {
+		basedat = (p[tx_ptr][0])|(p[tx_ptr][1] << 16);
+		iowrite32(basedat,dev->pwmdac_base + PWMDAC_WDATA);
+		period_pos++;
+		if (++tx_ptr >= runtime->buffer_size)
+			tx_ptr = 0;
+	}
+
+	*period_elapsed = period_pos >= runtime->period_size;
+	return tx_ptr;
+}
+
+static const struct snd_pcm_hardware sf_pcm_hardware = {
+	.info = SNDRV_PCM_INFO_INTERLEAVED |
+		SNDRV_PCM_INFO_MMAP |
+		SNDRV_PCM_INFO_MMAP_VALID |
+		SNDRV_PCM_INFO_BLOCK_TRANSFER,
+	.rates = SNDRV_PCM_RATE_16000,
+	.rate_min = 16000,
+	.rate_max = 16000,
+	.formats = SNDRV_PCM_FMTBIT_S16_LE,
+	.channels_min = 2,
+	.channels_max = 2,
+	.buffer_bytes_max = BUFFER_BYTES_MAX,
+	.period_bytes_min = PERIOD_BYTES_MIN,
+	.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
+	.periods_min = PERIODS_MIN,
+	.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
+	.fifo_size = 2,
+};
+
+static void sf_pcm_transfer(struct sf_pwmdac_dev *dev, bool push)
+{
+	struct snd_pcm_substream *substream = NULL;
+	bool period_elapsed = false;
+	bool active;
+
+	rcu_read_lock();
+	if (push)
+		substream = rcu_dereference(dev->tx_substream);
+
+	active = substream && snd_pcm_running(substream);
+	if (active) {
+		unsigned int ptr;
+		unsigned int new_ptr;
+
+		if (push) {
+			ptr = READ_ONCE(dev->tx_ptr);
+			new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
+					&period_elapsed);
+			cmpxchg(&dev->tx_ptr, ptr, new_ptr);
+		}
+
+		if (period_elapsed)
+			snd_pcm_period_elapsed(substream);
+	}
+	rcu_read_unlock();
+}
+
+void sf_pwmdac_pcm_push_tx(struct sf_pwmdac_dev *dev)
+{
+	sf_pcm_transfer(dev, true);
+}
+
+
+static int sf_pcm_open(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct sf_pwmdac_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+	snd_soc_set_runtime_hwparams(substream, &sf_pcm_hardware);
+	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
+	runtime->private_data = dev;
+
+	return 0;
+}
+
+
+static int sf_pcm_close(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream)
+{
+	synchronize_rcu();
+	return 0;
+}
+
+static int sf_pcm_hw_params(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream,
+			struct snd_pcm_hw_params *hw_params)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sf_pwmdac_dev *dev = runtime->private_data;
+
+	switch (params_channels(hw_params)) {
+	case 2:
+		break;
+	default:
+		dev_err(dev->dev, "invalid channels number\n");
+		return -EINVAL;
+	}
+
+	switch (params_format(hw_params)) {
+	case SNDRV_PCM_FORMAT_U8:
+	case SNDRV_PCM_FORMAT_S8:
+		dev->tx_fn = sf_pwmdac_pcm_tx_8;
+		break;
+	case SNDRV_PCM_FORMAT_S16_LE:
+		dev->tx_fn = sf_pwmdac_pcm_tx_16;
+		break;
+	default:
+		dev_err(dev->dev, "invalid format\n");
+		return -EINVAL;
+	}
+
+		return 0;
+}
+
+
+static int sf_pcm_trigger(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream, int cmd)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sf_pwmdac_dev *dev = runtime->private_data;
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			WRITE_ONCE(dev->tx_ptr, 0);
+			rcu_assign_pointer(dev->tx_substream, substream);
+		}
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			rcu_assign_pointer(dev->tx_substream, NULL);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static snd_pcm_uframes_t sf_pcm_pointer(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sf_pwmdac_dev *dev = runtime->private_data;
+	snd_pcm_uframes_t pos = 0;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		pos = READ_ONCE(dev->tx_ptr);
+
+	return pos < runtime->buffer_size ? pos : 0;
+}
+
+static int sf_pcm_new(struct snd_soc_component *component,
+			struct snd_soc_pcm_runtime *rtd)
+{
+	size_t size = sf_pcm_hardware.buffer_bytes_max;
+
+	snd_pcm_set_managed_buffer_all(rtd->pcm,
+			SNDRV_DMA_TYPE_CONTINUOUS,
+			NULL, size, size);
+	return 0;
+}
+
+static const struct snd_soc_component_driver dw_pcm_component = {
+	.open		= sf_pcm_open,
+	.close		= sf_pcm_close,
+	.hw_params	= sf_pcm_hw_params,
+	.trigger	= sf_pcm_trigger,
+	.pointer	= sf_pcm_pointer,
+	.pcm_construct	= sf_pcm_new,
+};
+
+int sf_pwmdac_pcm_register(struct platform_device *pdev)
+{
+	return devm_snd_soc_register_component(&pdev->dev, &dw_pcm_component,
+					NULL, 0);
+}
diff --git a/sound/soc/starfive/pwmdac-transmitter.c b/sound/soc/starfive/pwmdac-transmitter.c
new file mode 100644
index 000000000000..46c2e5041ffb
--- /dev/null
+++ b/sound/soc/starfive/pwmdac-transmitter.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/slab.h>
+#include <sound/soc.h>
+#include <sound/pcm.h>
+#include <sound/initval.h>
+#include <linux/of.h>
+
+#define DRV_NAME "pwmdac-dit"
+
+#define STUB_RATES	SNDRV_PCM_RATE_8000_192000
+#define STUB_FORMATS	(SNDRV_PCM_FMTBIT_S8|\
+			SNDRV_PCM_FMTBIT_U8      |\
+			SNDRV_PCM_FMTBIT_S16_LE  | \
+			SNDRV_PCM_FMTBIT_S20_3LE | \
+			SNDRV_PCM_FMTBIT_S24_LE  | \
+			SNDRV_PCM_FMTBIT_S32_LE)
+
+static const struct snd_soc_dapm_widget dit_widgets[] = {
+	SND_SOC_DAPM_OUTPUT("pwmdac-out"),
+};
+
+static const struct snd_soc_dapm_route dit_routes[] = {
+	{ "pwmdac-out", NULL, "Playback" },
+};
+
+static struct snd_soc_component_driver soc_codec_pwmdac_dit = {
+	.dapm_widgets		= dit_widgets,
+	.num_dapm_widgets	= ARRAY_SIZE(dit_widgets),
+	.dapm_routes		= dit_routes,
+	.num_dapm_routes	= ARRAY_SIZE(dit_routes),
+	.idle_bias_on		= 1,
+	.use_pmdown_time	= 1,
+	.endianness		= 1,
+};
+
+static struct snd_soc_dai_driver dit_stub_dai = {
+	.name		= "pwmdac-dit-hifi",
+	.playback 	= {
+		.stream_name	= "Playback",
+		.channels_min	= 1,
+		.channels_max	= 384,
+		.rates		= STUB_RATES,
+		.formats	= STUB_FORMATS,
+	},
+};
+
+static int pwmdac_dit_probe(struct platform_device *pdev)
+{
+
+	return devm_snd_soc_register_component(&pdev->dev,
+			&soc_codec_pwmdac_dit,
+			&dit_stub_dai, 1);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id pwmdac_dit_dt_ids[] = {
+	{ .compatible = "linux,pwmdac-dit", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, pwmdac_dit_dt_ids);
+#endif
+
+static struct platform_driver pwmdac_dit_driver = {
+	.probe		= pwmdac_dit_probe,
+	.driver		= {
+		.name	= DRV_NAME,
+		.of_match_table = of_match_ptr(pwmdac_dit_dt_ids),
+	},
+};
+
+module_platform_driver(pwmdac_dit_driver);
+
+MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
+MODULE_DESCRIPTION("pwmdac dummy codec driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform: starfive-pwmdac dummy codec");
diff --git a/sound/soc/starfive/pwmdac.c b/sound/soc/starfive/pwmdac.c
new file mode 100644
index 000000000000..78f2f9c62ec9
--- /dev/null
+++ b/sound/soc/starfive/pwmdac.c
@@ -0,0 +1,862 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PWMDAC driver for the StarFive JH7100 SoC
+ *
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/dmaengine_pcm.h>
+#include "pwmdac.h"
+#include <linux/kthread.h>
+
+struct ct_pwmdac {
+	char *name;
+	unsigned int vals;
+};
+
+static const struct ct_pwmdac pwmdac_ct_shift_bit[] = {
+	{ .name = "8bit", .vals = PWMDAC_SHIFT_8 },
+	{ .name = "10bit", .vals = PWMDAC_SHIFT_10 }
+};
+
+static const struct ct_pwmdac pwmdac_ct_duty_cycle[] = {
+	{ .name = "left", .vals = PWMDAC_CYCLE_LEFT },
+	{ .name = "right", .vals = PWMDAC_CYCLE_RIGHT },
+	{ .name = "center", .vals = PWMDAC_CYCLE_CENTER }
+};
+
+static const struct ct_pwmdac pwmdac_ct_data_mode[] = {
+	{ .name = "unsinged", .vals = UNSINGED_DATA },
+	{ .name = "inverter", .vals = INVERTER_DATA_MSB }
+};
+
+static const struct ct_pwmdac pwmdac_ct_lr_change[] = {
+	{ .name = "no_change", .vals = NO_CHANGE },
+	{ .name = "change", .vals = CHANGE }
+};
+
+static const struct ct_pwmdac pwmdac_ct_shift[] = {
+	{ .name = "left 0 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_0 },
+	{ .name = "left 1 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_1 },
+	{ .name = "left 2 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_2 },
+	{ .name = "left 3 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_3 },
+	{ .name = "left 4 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_4 },
+	{ .name = "left 5 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_5 },
+	{ .name = "left 6 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_6 }
+};
+
+static int pwmdac_shift_bit_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_shift_bit);
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = items;
+	if (uinfo->value.enumerated.item >= items) {
+		uinfo->value.enumerated.item = items - 1;
+	}
+	strcpy(uinfo->value.enumerated.name,
+			pwmdac_ct_shift_bit[uinfo->value.enumerated.item].name);
+
+	return 0;
+}
+static int pwmdac_shift_bit_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+	unsigned int item;
+
+	if (dev->shift_bit == pwmdac_ct_shift_bit[0].vals)
+		item = 0;
+	else
+		item = 1;
+
+	ucontrol->value.enumerated.item[0] = item;
+
+	return 0;
+}
+
+static int pwmdac_shift_bit_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+	int sel = ucontrol->value.enumerated.item[0];
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_shift_bit);
+
+	if (sel > items)
+		return 0;
+
+	switch (sel) {
+	case 1:
+		dev->shift_bit = pwmdac_ct_shift_bit[1].vals;
+		break;
+	default:
+		dev->shift_bit = pwmdac_ct_shift_bit[0].vals;
+		break;
+	}
+
+	return 0;
+}
+
+static int pwmdac_duty_cycle_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_duty_cycle);
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = items;
+	if (uinfo->value.enumerated.item >= items)
+		uinfo->value.enumerated.item = items - 1;
+	strcpy(uinfo->value.enumerated.name,
+		pwmdac_ct_duty_cycle[uinfo->value.enumerated.item].name);
+
+	return 0;
+}
+
+static int pwmdac_duty_cycle_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.enumerated.item[0] = dev->duty_cycle;
+	return 0;
+}
+
+static int pwmdac_duty_cycle_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+	int sel = ucontrol->value.enumerated.item[0];
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_duty_cycle);
+
+	if (sel > items)
+		return 0;
+
+	dev->duty_cycle = pwmdac_ct_duty_cycle[sel].vals;
+	return 0;
+}
+
+/*
+static int pwmdac_datan_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 1;
+	uinfo->value.integer.max = PWMDAC_SAMPLE_CNT_511;
+	uinfo->value.integer.step = 1;
+	return 0;
+}
+
+static int pwmdac_datan_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.integer.value[0] = dev->datan;
+
+	return 0;
+}
+
+static int pwmdac_datan_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+	int sel = ucontrol->value.integer.value[0];
+
+	if (sel > PWMDAC_SAMPLE_CNT_511)
+		return 0;
+
+	dev->datan = sel;
+
+	return 0;
+}
+*/
+
+static int pwmdac_data_mode_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_data_mode);
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = items;
+	if (uinfo->value.enumerated.item >= items)
+		uinfo->value.enumerated.item = items - 1;
+	strcpy(uinfo->value.enumerated.name,
+		pwmdac_ct_data_mode[uinfo->value.enumerated.item].name);
+
+	return 0;
+}
+
+static int pwmdac_data_mode_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.enumerated.item[0] = dev->data_mode;
+	return 0;
+}
+
+static int pwmdac_data_mode_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+	int sel = ucontrol->value.enumerated.item[0];
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_data_mode);
+
+	if (sel > items)
+		return 0;
+
+	dev->data_mode = pwmdac_ct_data_mode[sel].vals;
+	return 0;
+}
+
+static int pwmdac_shift_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_shift);
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = items;
+	if (uinfo->value.enumerated.item >= items)
+		uinfo->value.enumerated.item = items - 1;
+	strcpy(uinfo->value.enumerated.name,
+		pwmdac_ct_shift[uinfo->value.enumerated.item].name);
+
+	return 0;
+}
+
+static int pwmdac_shift_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+	unsigned int item = dev->shift;
+
+	ucontrol->value.enumerated.item[0] = pwmdac_ct_shift[item].vals;
+	return 0;
+}
+
+static int pwmdac_shift_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+	int sel = ucontrol->value.enumerated.item[0];
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_shift);
+
+	if (sel > items)
+		return 0;
+
+	dev->shift = pwmdac_ct_shift[sel].vals;
+	return 0;
+}
+
+static int pwmdac_lr_change_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_lr_change);
+
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+	uinfo->count = 1;
+	uinfo->value.enumerated.items = items;
+	if (uinfo->value.enumerated.item >= items)
+		uinfo->value.enumerated.item = items - 1;
+	strcpy(uinfo->value.enumerated.name,
+		pwmdac_ct_lr_change[uinfo->value.enumerated.item].name);
+
+	return 0;
+}
+
+static int pwmdac_lr_change_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+
+	ucontrol->value.enumerated.item[0] = dev->lr_change;
+	return 0;
+}
+
+static int pwmdac_lr_change_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct sf_pwmdac_dev *dev = snd_soc_component_get_drvdata(component);
+	int sel = ucontrol->value.enumerated.item[0];
+	unsigned int items = ARRAY_SIZE(pwmdac_ct_lr_change);
+
+	if (sel > items)
+		return 0;
+
+	dev->lr_change = pwmdac_ct_lr_change[sel].vals;
+	return 0;
+}
+
+static inline void pwmdc_write_reg(void __iomem *io_base, int reg, u32 val)
+{
+	writel(val, io_base + reg);
+}
+
+static inline u32 pwmdc_read_reg(void __iomem *io_base, int reg)
+{
+	return readl(io_base + reg);
+}
+
+/*
+ * 32bit-4byte
+*/
+static void pwmdac_set_ctrl_enable(struct sf_pwmdac_dev *dev)
+{
+	u32 date;
+	date = pwmdc_read_reg(dev->pwmdac_base, PWMDAC_CTRL);
+	pwmdc_write_reg(dev->pwmdac_base, PWMDAC_CTRL, date | BIT(0) );
+}
+
+/*
+ * 32bit-4byte
+*/
+static void pwmdac_set_ctrl_disable(struct sf_pwmdac_dev *dev)
+{
+	u32 date;
+	date = pwmdc_read_reg(dev->pwmdac_base, PWMDAC_CTRL);
+	pwmdc_write_reg(dev->pwmdac_base, PWMDAC_CTRL, date & ~ BIT(0));
+}
+
+/*
+ * 8:8-bit
+ * 10:10-bit
+*/
+static void pwmdac_set_ctrl_shift(struct sf_pwmdac_dev *dev, u8 data)
+{
+	u32 value = 0;
+
+	if (data == 8) {
+		value = (~((~value) | 0x02));
+		pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
+	}
+	else if(data == 10){
+		value |= 0x02;
+		pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
+	}
+}
+
+/*
+ * 00:left
+ * 01:right
+ * 10:center
+*/
+static void pwmdac_set_ctrl_dutyCycle(struct sf_pwmdac_dev *dev, u8 data)
+{
+	u32 value = 0;
+
+	value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
+	if (data == 0) { //left
+		value = (~((~value) | (0x03<<2)));
+		pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
+	}
+	else if (data == 1) { //right
+		value = (~((~value) | (0x01<<3))) | (0x01<<2);
+		pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
+	}
+	else if (data == 2) { //center
+		value = (~((~value) | (0x01<<2))) | (0x01<<3);
+		pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
+	}
+}
+
+
+static void pwmdac_set_ctrl_N(struct sf_pwmdac_dev *dev, u16 data)
+{
+	u32 value = 0;
+
+	value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
+	pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, (value & 0xF) | ((data - 1) << 4));
+}
+
+
+static void pwmdac_LR_data_change(struct sf_pwmdac_dev *dev, u8 data)
+{
+	u32 value = 0;
+
+	value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
+	switch (data) {
+	case NO_CHANGE:
+		value &= (~SFC_PWMDAC_LEFT_RIGHT_DATA_CHANGE);
+		break;
+	case CHANGE:
+		value |= SFC_PWMDAC_LEFT_RIGHT_DATA_CHANGE;
+		break;
+	}
+	pwmdc_write_reg(dev->pwmdac_base, PWMDAC_CTRL, value);
+}
+
+static void pwmdac_data_mode(struct sf_pwmdac_dev *dev, u8 data)
+{
+	u32 value = 0;
+
+	value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
+	if (data == UNSINGED_DATA) {
+		value &= (~SFC_PWMDAC_DATA_MODE);
+	}
+	else if (data == INVERTER_DATA_MSB) {
+		value |= SFC_PWMDAC_DATA_MODE;
+	}
+	pwmdc_write_reg(dev->pwmdac_base,PWMDAC_CTRL, value);
+}
+
+static int pwmdac_data_shift(struct sf_pwmdac_dev *dev,u8 data)
+{
+	u32 value = 0;
+
+	if ((data < PWMDAC_DATA_LEFT_SHIFT_BIT_0) || (data > PWMDAC_DATA_LEFT_SHIFT_BIT_7)) {
+		return -1;
+	}
+
+	value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_CTRL);
+	value &= ( ~ ( PWMDAC_DATA_LEFT_SHIFT_BIT_ALL << 15 ) );
+	value |= (data<<15);
+	pwmdc_write_reg(dev->pwmdac_base , PWMDAC_CTRL, value);
+	return 0;
+}
+
+static int get_pwmdac_fifo_state(struct sf_pwmdac_dev *dev)
+{
+	u32 value;
+
+	value = pwmdc_read_reg(dev->pwmdac_base , PWMDAC_SATAE);
+	if ((value & 0x02) == 0)
+		return FIFO_UN_FULL;
+
+	return FIFO_FULL;
+}
+
+
+static void pwmdac_set(struct sf_pwmdac_dev *dev)
+{
+	///8-bit + left + N=16
+	pwmdac_set_ctrl_shift(dev, dev->shift_bit);
+	pwmdac_set_ctrl_dutyCycle(dev, dev->duty_cycle);
+	pwmdac_set_ctrl_N(dev, dev->datan);
+	pwmdac_set_ctrl_enable(dev);
+
+	pwmdac_LR_data_change(dev, dev->lr_change);
+	pwmdac_data_mode(dev, dev->data_mode);
+	if (dev->shift) {
+		pwmdac_data_shift(dev, dev->shift);
+	}
+}
+
+static void pwmdac_stop(struct sf_pwmdac_dev *dev)
+{
+	pwmdac_set_ctrl_disable(dev);
+}
+
+static int pwmdac_config(struct sf_pwmdac_dev *dev)
+{
+	switch (dev->mode) {
+	case shift_8Bit_unsigned:
+	case shift_8Bit_unsigned_dataShift:
+		/* 8 bit, unsigned */
+		dev->shift_bit	= PWMDAC_SHIFT_8;
+		dev->duty_cycle	= PWMDAC_CYCLE_CENTER;
+		dev->datan		= PWMDAC_SAMPLE_CNT_8;
+		dev->data_mode	= UNSINGED_DATA;
+		break;
+
+	case shift_8Bit_inverter:
+	case shift_8Bit_inverter_dataShift:
+		/* 8 bit, invert */
+		dev->shift_bit	= PWMDAC_SHIFT_8;
+		dev->duty_cycle	= PWMDAC_CYCLE_CENTER;
+		dev->datan		= PWMDAC_SAMPLE_CNT_8;
+		dev->data_mode	= INVERTER_DATA_MSB;
+		break;
+
+	case shift_10Bit_unsigned:
+	case shift_10Bit_unsigned_dataShift:
+		/* 10 bit, unsigend */
+		dev->shift_bit	= PWMDAC_SHIFT_10;
+		dev->duty_cycle	= PWMDAC_CYCLE_CENTER;
+		dev->datan		= PWMDAC_SAMPLE_CNT_8;
+		dev->data_mode	= UNSINGED_DATA;
+		break;
+
+	case shift_10Bit_inverter:
+	case shift_10Bit_inverter_dataShift:
+		/* 10 bit, invert */
+		dev->shift_bit	= PWMDAC_SHIFT_10;
+		dev->duty_cycle	= PWMDAC_CYCLE_CENTER;
+		dev->datan		= PWMDAC_SAMPLE_CNT_8;
+		dev->data_mode	= INVERTER_DATA_MSB;
+		break;
+
+	default:
+		return -1;
+	}
+
+	if ((dev->mode == shift_8Bit_unsigned_dataShift) || (dev->mode == shift_8Bit_inverter_dataShift)
+		|| (dev->mode == shift_10Bit_unsigned_dataShift) || (dev->mode == shift_10Bit_inverter_dataShift)) {
+		dev->shift = 4; /*0~7*/
+	} else {
+		dev->shift = 0;
+	}
+	dev->lr_change = NO_CHANGE;
+	return 0;
+}
+
+static int sf_pwmdac_prepare(struct snd_pcm_substream *substream,
+			struct snd_soc_dai *dai)
+{
+	//struct sf_pwmdac_dev *dev = snd_soc_dai_get_drvdata(dai);
+	//pwmdac_set(dev);
+	return 0;
+}
+
+static int pwmdac_tx_thread(void *dev)
+{
+	struct sf_pwmdac_dev *pwmdac_dev = (struct sf_pwmdac_dev *)dev;
+
+	set_current_state(TASK_INTERRUPTIBLE);
+	while (!schedule_timeout(usecs_to_jiffies(50))) {
+		if (pwmdac_dev->tx_thread_exit)
+			break;
+		if (get_pwmdac_fifo_state(pwmdac_dev)==0) {
+			sf_pwmdac_pcm_push_tx(pwmdac_dev);
+		}
+
+		set_current_state(TASK_INTERRUPTIBLE);
+	}
+
+	pwmdac_dev->tx_thread = NULL;
+	return 0;
+}
+
+static int sf_pwmdac_trigger(struct snd_pcm_substream *substream,
+		int cmd, struct snd_soc_dai *dai)
+{
+	struct sf_pwmdac_dev *dev = snd_soc_dai_get_drvdata(dai);
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		dev->active++;
+		pwmdac_set(dev);
+		if (dev->use_pio) {
+			dev->tx_thread = kthread_create(pwmdac_tx_thread, (void *)dev, "pwmdac");
+			if (IS_ERR(dev->tx_thread)) {
+				return PTR_ERR(dev->tx_thread);
+			}
+			wake_up_process(dev->tx_thread);
+			dev->tx_thread_exit = 0;
+		}
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		dev->active--;
+		pwmdac_stop(dev);
+		if (dev->use_pio) {
+			if(dev->tx_thread) {
+				dev->tx_thread_exit = 1;
+			}
+		}
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+
+	return 0;
+}
+
+static int sf_pwmdac_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+	struct sf_pwmdac_dev *dev = dev_get_drvdata(dai->dev);
+
+	dev->play_dma_data.addr = dev->mapbase + PWMDAC_WDATA;
+
+	switch (params_channels(params)) {
+	case 2:
+		dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+		break;
+	case 1:
+		dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+		break;
+	default:
+		dev_err(dai->dev, "%d channels not supported\n",
+				params_channels(params));
+		return -EINVAL;
+	}
+
+	dev->play_dma_data.fifo_size = 1;
+	dev->play_dma_data.maxburst = 16;
+
+	snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, NULL);
+	snd_soc_dai_set_drvdata(dai, dev);
+
+	return 0;
+}
+
+static int sf_pwmdac_clks_get(struct platform_device *pdev,
+			      struct sf_pwmdac_dev *dev)
+{
+	static const char *const clock_names[PWMDAC_CLK_NUM] = {
+		[PWMDAC_CLK_AUDIO_ROOT]  = "audio_root",
+		[PWMDAC_CLK_AUDIO_SRC]   = "audio_src",
+		[PWMDAC_CLK_AUDIO_12288] = "audio_12288",
+		[PWMDAC_CLK_DMA1P_AHB]   = "dma1p_ahb",
+		[PWMDAC_CLK_PWMDAC_APB]  = "pwmdac_apb",
+		[PWMDAC_CLK_DAC_MCLK]    = "dac_mclk",
+	};
+	int i;
+
+	for (i = 0; i < PWMDAC_CLK_NUM; i++)
+		dev->clk[i].id = clock_names[i];
+
+	return devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(dev->clk), dev->clk);
+}
+
+static int sf_pwmdac_resets_get(struct platform_device *pdev,
+				struct sf_pwmdac_dev *dev)
+{
+	static const char *const reset_names[PWMDAC_RST_NUM] = {
+		[PWMDAC_RST_APB_BUS]    = "apb_bus",
+		[PWMDAC_RST_DMA1P_AHB]  = "dma1p_ahb",
+		[PWMDAC_RST_APB_PWMDAC] = "apb_pwmdac",
+	};
+	int i;
+
+	for (i = 0; i < PWMDAC_RST_NUM; i++)
+		dev->rst[i].id = reset_names[i];
+
+	return devm_reset_control_bulk_get_exclusive(&pdev->dev, ARRAY_SIZE(dev->rst), dev->rst);
+}
+
+static int sf_pwmdac_clk_init(struct platform_device *pdev,
+				struct sf_pwmdac_dev *dev)
+{
+	int ret;
+	int i;
+
+	for (i = 0; i <= PWMDAC_CLK_DMA1P_AHB; i++) {
+		ret = clk_prepare_enable(dev->clk[i].clk);
+		if (ret)
+			return dev_err_probe(&pdev->dev, ret,
+					     "failed to enable %s\n", dev->clk[i].id);
+	}
+
+	for (i = 0; i <= PWMDAC_RST_DMA1P_AHB; i++) {
+		ret = reset_control_deassert(dev->rst[i].rstc);
+		if (ret)
+			return dev_err_probe(&pdev->dev, ret,
+					     "failed to deassert %s\n", dev->rst[i].id);
+	}
+
+	ret = clk_set_rate(dev->clk[PWMDAC_CLK_AUDIO_SRC].clk, 12288000);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret,
+				     "failed to set 12.288 MHz rate for clk_audio_src\n");
+
+	ret = reset_control_assert(dev->rst[PWMDAC_RST_APB_PWMDAC].rstc);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "failed to assert apb_pwmdac\n");
+
+	ret = clk_prepare_enable(dev->clk[PWMDAC_CLK_DAC_MCLK].clk);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "failed to prepare enable clk_dac_mclk\n");
+
+	/* we want 4096kHz but the clock driver always rounds down so add a little slack */
+	ret = clk_set_rate(dev->clk[PWMDAC_CLK_DAC_MCLK].clk, 4096000 + 64);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "failed to set 4096kHz rate for clk_dac_mclk\n");
+
+	ret = clk_prepare_enable(dev->clk[PWMDAC_CLK_PWMDAC_APB].clk);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "failed to prepare enable clk_pwmdac_apb\n");
+
+	ret = reset_control_deassert(dev->rst[PWMDAC_RST_APB_PWMDAC].rstc);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "failed to deassert apb_pwmdac\n");
+
+	return 0;
+}
+
+static int sf_pwmdac_dai_probe(struct snd_soc_dai *dai)
+{
+	struct sf_pwmdac_dev *dev = dev_get_drvdata(dai->dev);
+
+	dev->play_dma_data.addr = dev->mapbase + PWMDAC_WDATA;
+	dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	dev->play_dma_data.fifo_size = 1;
+	dev->play_dma_data.maxburst = 16;
+
+	snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, NULL);
+	snd_soc_dai_set_drvdata(dai, dev);
+
+	return 0;
+}
+#define SOC_PWMDAC_ENUM_DECL(xname, xinfo, xget, xput) \
+{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+	.info = xinfo, .get = xget, \
+	.put = xput,}
+static const struct snd_kcontrol_new pwmdac_snd_controls[] = {
+	SOC_PWMDAC_ENUM_DECL("shift_bit", pwmdac_shift_bit_info,
+		pwmdac_shift_bit_get, pwmdac_shift_bit_put),
+	SOC_PWMDAC_ENUM_DECL("duty_cycle", pwmdac_duty_cycle_info,
+		pwmdac_duty_cycle_get, pwmdac_duty_cycle_put),
+	SOC_PWMDAC_ENUM_DECL("data_mode", pwmdac_data_mode_info,
+		pwmdac_data_mode_get, pwmdac_data_mode_put),
+	SOC_PWMDAC_ENUM_DECL("shift", pwmdac_shift_info,
+		pwmdac_shift_get, pwmdac_shift_put),
+	SOC_PWMDAC_ENUM_DECL("lr_change", pwmdac_lr_change_info,
+		pwmdac_lr_change_get, pwmdac_lr_change_put),
+};
+static int pwmdac_probe(struct snd_soc_component *component)
+{
+//	struct sf_pwmdac_dev *priv = snd_soc_component_get_drvdata(component);
+	snd_soc_add_component_controls(component, pwmdac_snd_controls,
+				ARRAY_SIZE(pwmdac_snd_controls));
+	return 0;
+}
+
+
+static const struct snd_soc_dai_ops sf_pwmdac_dai_ops = {
+	.hw_params	= sf_pwmdac_hw_params,
+	.prepare	= sf_pwmdac_prepare,
+	.trigger	= sf_pwmdac_trigger,
+};
+
+static const struct snd_soc_component_driver sf_pwmdac_component = {
+	.name		= "sf-pwmdac",
+	.probe		= pwmdac_probe,
+};
+
+static struct snd_soc_dai_driver pwmdac_dai = {
+	.name = "pwmdac",
+	.id = 0,
+	.probe	= sf_pwmdac_dai_probe,
+	.playback = {
+		.channels_min = 1,
+		.channels_max = 2,
+		.rates = SNDRV_PCM_RATE_16000,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE,
+	},
+	.ops = &sf_pwmdac_dai_ops,
+};
+
+static int sf_pwmdac_probe(struct platform_device *pdev)
+{
+	struct sf_pwmdac_dev *dev;
+	struct resource *res;
+	int ret;
+
+	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	dev->mapbase = res->start;
+	dev->pwmdac_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(dev->pwmdac_base))
+		return PTR_ERR(dev->pwmdac_base);
+
+	ret = sf_pwmdac_clks_get(pdev, dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to get audio clock\n");
+		return ret;
+	}
+
+	ret = sf_pwmdac_resets_get(pdev, dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to get audio reset controls\n");
+		return ret;
+        }
+
+	ret = sf_pwmdac_clk_init(pdev, dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to enable audio clock\n");
+		return ret;
+	}
+
+	dev->dev = &pdev->dev;
+	dev->mode = shift_8Bit_inverter;
+	dev->fifo_th = 1;//8byte
+	pwmdac_config(dev);
+
+	dev->use_pio = false;
+	dev_set_drvdata(&pdev->dev, dev);
+	ret = devm_snd_soc_register_component(&pdev->dev, &sf_pwmdac_component,
+					 &pwmdac_dai, 1);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "not able to register dai\n");
+		return ret;
+	}
+
+	if (dev->use_pio) {
+		ret = sf_pwmdac_pcm_register(pdev);
+	} else {
+		ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
+				0);
+	}
+	return 0;
+}
+
+
+static int sf_pwmdac_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id sf_pwmdac_of_match[] = {
+	{ .compatible = "starfive,pwmdac",	 },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, sf_pwmdac_of_match);
+#endif
+
+
+static struct platform_driver sf_pwmdac_driver = {
+	.probe		= sf_pwmdac_probe,
+	.remove		= sf_pwmdac_remove,
+	.driver		= {
+		.name	= "sf-pwmdac",
+		.of_match_table = of_match_ptr(sf_pwmdac_of_match),
+	},
+};
+
+module_platform_driver(sf_pwmdac_driver);
+
+MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("starfive pwmdac SoC Interface");
+MODULE_ALIAS("platform:starfive-pwmdac");
diff --git a/sound/soc/starfive/pwmdac.h b/sound/soc/starfive/pwmdac.h
new file mode 100644
index 000000000000..b9f651fc59f1
--- /dev/null
+++ b/sound/soc/starfive/pwmdac.h
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef __SND_SOC_STARFIVE_PWMDAC_H
+#define __SND_SOC_STARFIVE_PWMDAC_H
+
+#include <linux/clk.h>
+#include <linux/reset.h>
+#include <linux/device.h>
+#include <linux/types.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm.h>
+
+#define PWMDAC_WDATA	0	// PWMDAC_BASE_ADDR
+#define PWMDAC_CTRL	0x04	// PWMDAC_BASE_ADDR + 0x04
+#define PWMDAC_SATAE	0x08	// PWMDAC_BASE_ADDR + 0x08
+#define PWMDAC_RESERVED	0x0C	// PWMDAC_BASE_ADDR + 0x0C
+
+#define SFC_PWMDAC_SHIFT	BIT(1)
+#define SFC_PWMDAC_DUTY_CYCLE	BIT(2)
+#define SFC_PWMDAC_CNT_N	BIT(4)
+
+#define SFC_PWMDAC_LEFT_RIGHT_DATA_CHANGE	BIT(13)
+#define SFC_PWMDAC_DATA_MODE			BIT(14)
+
+#define FIFO_UN_FULL	0
+#define FIFO_FULL	1
+
+enum pwmdac_lr_change{
+	NO_CHANGE = 0,
+	CHANGE,
+};
+
+enum pwmdac_d_mode{
+	UNSINGED_DATA = 0,
+	INVERTER_DATA_MSB,
+};
+
+enum pwmdac_shift_bit{
+	PWMDAC_SHIFT_8 = 8,	/* pwmdac shift 8 bit */
+	PWMDAC_SHIFT_10 = 10,	/* pwmdac shift 10 bit */
+};
+
+enum pwmdac_duty_cycle{
+	PWMDAC_CYCLE_LEFT = 0,		/* pwmdac duty cycle left */
+	PWMDAC_CYCLE_RIGHT = 1,		/* pwmdac duty cycle right */
+	PWMDAC_CYCLE_CENTER = 2,	/* pwmdac duty cycle center */
+};
+
+/*sample count [12:4] <511*/
+enum pwmdac_sample_count{
+	PWMDAC_SAMPLE_CNT_1 = 1,
+	PWMDAC_SAMPLE_CNT_2,
+	PWMDAC_SAMPLE_CNT_3,
+	PWMDAC_SAMPLE_CNT_4,
+	PWMDAC_SAMPLE_CNT_5,
+	PWMDAC_SAMPLE_CNT_6,
+	PWMDAC_SAMPLE_CNT_7,
+	PWMDAC_SAMPLE_CNT_8 = 1,	//(32.468/8) == (12.288/3) == 4.096
+	PWMDAC_SAMPLE_CNT_9,
+	PWMDAC_SAMPLE_CNT_10,
+	PWMDAC_SAMPLE_CNT_11,
+	PWMDAC_SAMPLE_CNT_12,
+	PWMDAC_SAMPLE_CNT_13,
+	PWMDAC_SAMPLE_CNT_14,
+	PWMDAC_SAMPLE_CNT_15,
+	PWMDAC_SAMPLE_CNT_16,
+	PWMDAC_SAMPLE_CNT_17,
+	PWMDAC_SAMPLE_CNT_18,
+	PWMDAC_SAMPLE_CNT_19,
+	PWMDAC_SAMPLE_CNT_20 = 20,
+	PWMDAC_SAMPLE_CNT_30 = 30,
+	PWMDAC_SAMPLE_CNT_511 = 511,
+};
+
+
+enum data_shift{
+	PWMDAC_DATA_LEFT_SHIFT_BIT_0 = 0,
+	PWMDAC_DATA_LEFT_SHIFT_BIT_1,
+	PWMDAC_DATA_LEFT_SHIFT_BIT_2,
+	PWMDAC_DATA_LEFT_SHIFT_BIT_3,
+	PWMDAC_DATA_LEFT_SHIFT_BIT_4,
+	PWMDAC_DATA_LEFT_SHIFT_BIT_5,
+	PWMDAC_DATA_LEFT_SHIFT_BIT_6,
+	PWMDAC_DATA_LEFT_SHIFT_BIT_7,
+	PWMDAC_DATA_LEFT_SHIFT_BIT_ALL,
+};
+
+enum pwmdac_config_list{
+	shift_8Bit_unsigned = 0,
+	shift_8Bit_unsigned_dataShift,
+	shift_10Bit_unsigned,
+	shift_10Bit_unsigned_dataShift,
+
+	shift_8Bit_inverter,
+	shift_8Bit_inverter_dataShift,
+	shift_10Bit_inverter,
+	shift_10Bit_inverter_dataShift,
+};
+
+enum pwmdac_clocks {
+	PWMDAC_CLK_AUDIO_ROOT,
+	PWMDAC_CLK_AUDIO_SRC,
+	PWMDAC_CLK_AUDIO_12288,
+	PWMDAC_CLK_DMA1P_AHB,
+	PWMDAC_CLK_PWMDAC_APB,
+	PWMDAC_CLK_DAC_MCLK,
+	PWMDAC_CLK_NUM,
+};
+
+enum pwmdac_resets {
+	PWMDAC_RST_APB_BUS,
+	PWMDAC_RST_DMA1P_AHB,
+	PWMDAC_RST_APB_PWMDAC,
+	PWMDAC_RST_NUM,
+};
+
+struct sf_pwmdac_dev {
+	void __iomem *pwmdac_base;
+	resource_size_t	mapbase;
+	u8  mode;
+	u8 shift_bit;
+	u8 duty_cycle;
+	u8 datan;
+	u8 data_mode;
+	u8 lr_change;
+	u8 shift;
+	u8 fifo_th;
+	bool use_pio;
+	spinlock_t lock;
+	int active;
+
+	struct clk_bulk_data clk[PWMDAC_CLK_NUM];
+	struct reset_control_bulk_data rst[PWMDAC_RST_NUM];
+
+	struct device *dev;
+	struct snd_dmaengine_dai_dma_data play_dma_data;
+	struct snd_pcm_substream __rcu *tx_substream;
+	unsigned int (*tx_fn)(struct sf_pwmdac_dev *dev,
+			struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
+			bool *period_elapsed);
+	unsigned int tx_ptr;
+	struct task_struct *tx_thread;
+	bool tx_thread_exit;
+};
+
+
+
+#if IS_ENABLED(CONFIG_SND_STARFIVE_PWMDAC_PCM)
+void sf_pwmdac_pcm_push_tx(struct sf_pwmdac_dev *dev);
+int sf_pwmdac_pcm_register(struct platform_device *pdev);
+#else
+static void sf_pwmdac_pcm_push_tx(struct sf_pwmdac_dev *dev) { }
+static int sf_pwmdac_pcm_register(struct platform_device *pdev)
+{
+	return -EINVAL;
+}
+#endif
+
+#endif
diff --git a/sound/soc/starfive/spdif-pcm.c b/sound/soc/starfive/spdif-pcm.c
new file mode 100644
index 000000000000..cd78ffd1e691
--- /dev/null
+++ b/sound/soc/starfive/spdif-pcm.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/io.h>
+#include <linux/rcupdate.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+
+#include "spdif.h"
+
+#define BUFFER_BYTES_MAX	(3 * 2 * 8 * PERIOD_BYTES_MIN)
+#define PERIOD_BYTES_MIN	4096
+#define PERIODS_MIN			2
+
+static unsigned int sf_spdif_pcm_tx(struct sf_spdif_dev *dev,
+		struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
+		bool *period_elapsed, snd_pcm_format_t format)
+{
+	const u16 (*p16)[2] = (void *)runtime->dma_area;
+	const u32 (*p32)[2] = (void *)runtime->dma_area;
+	u32 data[2];
+	unsigned int period_pos = tx_ptr % runtime->period_size;
+	int i;
+
+	for (i = 0; i < dev->fifo_th; i++) {
+		if (SNDRV_PCM_FORMAT_S16_LE == format) {
+			data[0] = p16[tx_ptr][0];
+			data[1] = p16[tx_ptr][1];
+			data[0] = data[0]<<8;
+			data[1] = data[1]<<8;
+		} else if (SNDRV_PCM_FORMAT_S24_LE == format) {
+			data[0] = p32[tx_ptr][0];
+			data[1] = p32[tx_ptr][1];
+		} else if (SNDRV_PCM_FORMAT_S32_LE == format) {
+			data[0] = p32[tx_ptr][0];
+			data[1] = p32[tx_ptr][1];
+			data[0] = data[0]>>8;
+			data[1] = data[1]>>8;
+		}
+
+		iowrite32(data[0], dev->spdif_base + SPDIF_FIFO_ADDR);
+		iowrite32(data[1], dev->spdif_base + SPDIF_FIFO_ADDR);
+		period_pos++;
+		if (++tx_ptr >= runtime->buffer_size) {
+			tx_ptr = 0;
+		}
+	}
+
+	*period_elapsed = period_pos >= runtime->period_size;
+	return tx_ptr;
+}
+
+static unsigned int sf_spdif_pcm_rx(struct sf_spdif_dev *dev,
+		struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
+		bool *period_elapsed, snd_pcm_format_t format)
+{
+	u16 (*p16)[2] = (void *)runtime->dma_area;
+	u32 (*p32)[2] = (void *)runtime->dma_area;
+	u32 data[2];
+	unsigned int period_pos = rx_ptr % runtime->period_size;
+	int i;
+
+	for (i = 0; i < dev->fifo_th; i++) {
+		data[0] = ioread32(dev->spdif_base + SPDIF_FIFO_ADDR);
+		data[1] = ioread32(dev->spdif_base + SPDIF_FIFO_ADDR);
+		if (SNDRV_PCM_FORMAT_S16_LE == format) {
+			p16[rx_ptr][0] = data[0]>>8;
+			p16[rx_ptr][1] = data[1]>>8;
+		} else if (SNDRV_PCM_FORMAT_S24_LE == format) {
+			p32[rx_ptr][0] = data[0];
+			p32[rx_ptr][1] = data[1];
+		} else if (SNDRV_PCM_FORMAT_S32_LE == format) {
+			p32[rx_ptr][0] = data[0]<<8;
+			p32[rx_ptr][1] = data[1]<<8;
+		}
+
+		period_pos++;
+		if (++rx_ptr >= runtime->buffer_size)
+			rx_ptr = 0;
+	}
+
+	*period_elapsed = period_pos >= runtime->period_size;
+	return rx_ptr;
+}
+
+static const struct snd_pcm_hardware sf_pcm_hardware = {
+	.info = SNDRV_PCM_INFO_INTERLEAVED |
+		SNDRV_PCM_INFO_MMAP |
+		SNDRV_PCM_INFO_MMAP_VALID |
+		SNDRV_PCM_INFO_BLOCK_TRANSFER,
+	.rates = SNDRV_PCM_RATE_8000 |
+		SNDRV_PCM_RATE_11025 |
+		SNDRV_PCM_RATE_16000 |
+		SNDRV_PCM_RATE_22050 |
+		SNDRV_PCM_RATE_32000 |
+		SNDRV_PCM_RATE_44100 |
+		SNDRV_PCM_RATE_48000,
+	.rate_min = 8000,
+	.rate_max = 48000,
+	.formats = SNDRV_PCM_FMTBIT_S16_LE |
+		SNDRV_PCM_FMTBIT_S24_LE |
+		SNDRV_PCM_FMTBIT_S32_LE,
+	.channels_min = 2,
+	.channels_max = 2,
+	.buffer_bytes_max = BUFFER_BYTES_MAX,
+	.period_bytes_min = PERIOD_BYTES_MIN,
+	.period_bytes_max = BUFFER_BYTES_MAX / PERIODS_MIN,
+	.periods_min = PERIODS_MIN,
+	.periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
+	.fifo_size = 16,
+};
+
+static void sf_spdif_pcm_transfer(struct sf_spdif_dev *dev, bool push)
+{
+	struct snd_pcm_substream *substream;
+	bool active, period_elapsed;
+
+	rcu_read_lock();
+	if (push)
+		substream = rcu_dereference(dev->tx_substream);
+	else
+		substream = rcu_dereference(dev->rx_substream);
+	active = substream && snd_pcm_running(substream);
+	if (active) {
+		unsigned int ptr;
+		unsigned int new_ptr;
+
+		if (push) {
+			ptr = READ_ONCE(dev->tx_ptr);
+			new_ptr = dev->tx_fn(dev, substream->runtime, ptr,
+					&period_elapsed, dev->format);
+			cmpxchg(&dev->tx_ptr, ptr, new_ptr);
+		} else {
+			ptr = READ_ONCE(dev->rx_ptr);
+			new_ptr = dev->rx_fn(dev, substream->runtime, ptr,
+					&period_elapsed, dev->format);
+			cmpxchg(&dev->rx_ptr, ptr, new_ptr);
+		}
+
+		if (period_elapsed)
+			snd_pcm_period_elapsed(substream);
+	}
+	rcu_read_unlock();
+}
+
+void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev)
+{
+	sf_spdif_pcm_transfer(dev, true);
+}
+
+void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev)
+{
+	sf_spdif_pcm_transfer(dev, false);
+}
+
+static int sf_pcm_open(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+	struct sf_spdif_dev *dev = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
+
+	snd_soc_set_runtime_hwparams(substream, &sf_pcm_hardware);
+	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
+	runtime->private_data = dev;
+
+	return 0;
+}
+
+static int sf_pcm_close(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream)
+{
+	synchronize_rcu();
+	return 0;
+}
+
+static int sf_pcm_hw_params(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream,
+			struct snd_pcm_hw_params *hw_params)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sf_spdif_dev *dev = runtime->private_data;
+
+	switch (params_channels(hw_params)) {
+	case 2:
+		break;
+	default:
+		dev_err(dev->dev, "invalid channels number\n");
+		return -EINVAL;
+	}
+
+	dev->format = params_format(hw_params);
+	switch (dev->format) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+	case SNDRV_PCM_FORMAT_S24_LE:
+	case SNDRV_PCM_FORMAT_S32_LE:
+		break;
+	default:
+		dev_err(dev->dev, "invalid format\n");
+		return -EINVAL;
+	}
+
+	dev->tx_fn = sf_spdif_pcm_tx;
+	dev->rx_fn = sf_spdif_pcm_rx;
+
+	return 0;
+}
+
+static int sf_pcm_trigger(struct snd_soc_component *component,
+			struct snd_pcm_substream *substream, int cmd)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sf_spdif_dev *dev = runtime->private_data;
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			WRITE_ONCE(dev->tx_ptr, 0);
+			rcu_assign_pointer(dev->tx_substream, substream);
+		} else {
+			WRITE_ONCE(dev->rx_ptr, 0);
+			rcu_assign_pointer(dev->rx_substream, substream);
+		}
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			rcu_assign_pointer(dev->tx_substream, NULL);
+		else
+			rcu_assign_pointer(dev->rx_substream, NULL);
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static snd_pcm_uframes_t sf_pcm_pointer(struct snd_soc_component *component,
+					struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct sf_spdif_dev *dev = runtime->private_data;
+	snd_pcm_uframes_t pos;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		pos = READ_ONCE(dev->tx_ptr);
+	}
+	else {
+		pos = READ_ONCE(dev->rx_ptr);
+	}
+
+	return pos < runtime->buffer_size ? pos : 0;
+}
+
+static int sf_pcm_new(struct snd_soc_component *component,
+			struct snd_soc_pcm_runtime *rtd)
+{
+	size_t size = sf_pcm_hardware.buffer_bytes_max;
+
+	snd_pcm_set_managed_buffer_all(rtd->pcm,
+			SNDRV_DMA_TYPE_CONTINUOUS,
+			NULL, size, size);
+
+	return 0;
+}
+
+static const struct snd_soc_component_driver sf_pcm_component = {
+	.open		= sf_pcm_open,
+	.close		= sf_pcm_close,
+	.hw_params	= sf_pcm_hw_params,
+	.trigger	= sf_pcm_trigger,
+	.pointer	= sf_pcm_pointer,
+	.pcm_construct	= sf_pcm_new,
+};
+
+int sf_spdif_pcm_register(struct platform_device *pdev)
+{
+	return devm_snd_soc_register_component(&pdev->dev, &sf_pcm_component,
+					NULL, 0);
+}
+
diff --git a/sound/soc/starfive/spdif.c b/sound/soc/starfive/spdif.c
new file mode 100644
index 000000000000..910333638056
--- /dev/null
+++ b/sound/soc/starfive/spdif.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+#include <linux/regmap.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+#include <sound/dmaengine_pcm.h>
+
+#include "spdif.h"
+
+static irqreturn_t spdif_irq_handler(int irq, void *dev_id)
+{
+	struct sf_spdif_dev *dev = dev_id;
+	bool irq_valid = false;
+	unsigned int intr;
+	unsigned int stat;
+
+	regmap_read(dev->regmap, SPDIF_INT_REG, &intr);
+	regmap_read(dev->regmap, SPDIF_STAT_REG, &stat);
+	regmap_update_bits(dev->regmap, SPDIF_CTRL,
+		SPDIF_MASK_ENABLE, 0);
+	regmap_update_bits(dev->regmap, SPDIF_INT_REG,
+		SPDIF_INT_REG_BIT, 0);
+
+	if ((stat & SPDIF_EMPTY_FLAG) || (stat & SPDIF_AEMPTY_FLAG)) {
+		sf_spdif_pcm_push_tx(dev);
+		irq_valid = true;
+	}
+
+	if ((stat & SPDIF_FULL_FLAG) || (stat & SPDIF_AFULL_FLAG)) {
+		sf_spdif_pcm_pop_rx(dev);
+		irq_valid = true;
+	}
+
+	if (stat & SPDIF_PARITY_FLAG) {
+		irq_valid = true;
+	}
+
+	if (stat & SPDIF_UNDERR_FLAG) {
+		irq_valid = true;
+	}
+
+	if (stat & SPDIF_OVRERR_FLAG) {
+		irq_valid = true;
+	}
+
+	if (stat & SPDIF_SYNCERR_FLAG) {
+		irq_valid = true;
+	}
+
+	if (stat & SPDIF_LOCK_FLAG) {
+		irq_valid = true;
+	}
+
+	if (stat & SPDIF_BEGIN_FLAG) {
+		irq_valid = true;
+	}
+
+	if (stat & SPDIF_RIGHT_LEFT) {
+		irq_valid = true;
+	}
+
+	regmap_update_bits(dev->regmap, SPDIF_CTRL,
+		SPDIF_MASK_ENABLE, SPDIF_MASK_ENABLE);
+
+	if (irq_valid)
+		return IRQ_HANDLED;
+	else
+		return IRQ_NONE;
+}
+
+static int sf_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
+	struct snd_soc_dai *dai)
+{
+	struct sf_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
+	bool tx;
+
+	tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+	if (tx) {
+		/* tx mode */
+		regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+			SPDIF_TR_MODE, SPDIF_TR_MODE);
+
+		regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+			SPDIF_MASK_FIFO, SPDIF_EMPTY_MASK | SPDIF_AEMPTY_MASK);
+	} else {
+		/* rx mode */
+		regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+			SPDIF_TR_MODE, 0);
+
+		regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+			SPDIF_MASK_FIFO, SPDIF_FULL_MASK | SPDIF_AFULL_MASK);
+	}
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		/* clock recovery form the SPDIF data stream  0:clk_enable */
+		regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+			SPDIF_CLK_ENABLE, 0);
+
+		regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+			SPDIF_ENABLE, SPDIF_ENABLE);
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		/* clock recovery form the SPDIF data stream  1:power save mode */
+		regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+			SPDIF_CLK_ENABLE, SPDIF_CLK_ENABLE);
+
+		regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+			SPDIF_ENABLE, 0);
+		break;
+	default:
+		printk(KERN_ERR "%s L.%d cmd:%d\n", __func__, __LINE__, cmd);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sf_spdif_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
+{
+	struct sf_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
+	unsigned int channels;
+	unsigned int rate;
+	unsigned int format;
+	unsigned int tsamplerate;
+
+	channels = params_channels(params);
+	rate = params_rate(params);
+	format = params_format(params);
+
+	switch (channels) {
+	case 2:
+		break;
+	default:
+		dev_err(dai->dev, "invalid channels number\n");
+		return -EINVAL;
+	}
+
+	switch (format) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+	case SNDRV_PCM_FORMAT_S24_LE:
+	case SNDRV_PCM_FORMAT_S32_LE:
+		break;
+	default:
+		dev_err(spdif->dev, "invalid format\n");
+		return -EINVAL;
+	}
+
+	switch (rate) {
+	case 8000:
+	case 11025:
+	case 16000:
+	case 22050:
+		break;
+	default:
+		printk(KERN_ERR "channel:%d sample rate:%d\n", channels, rate);
+		return -EINVAL;
+	}
+
+	/* 12288000/128=96000 */
+	tsamplerate = (96000 + rate/2)/rate - 1;
+
+	if (rate < 3) {
+		return -EINVAL;
+	}
+
+	/* transmission sample rate */
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL, 0xFF, tsamplerate);
+
+	return 0;
+}
+
+static int sf_spdif_dai_probe(struct snd_soc_dai *dai)
+{
+	struct sf_spdif_dev *spdif = snd_soc_dai_get_drvdata(dai);
+
+	#if 0
+	spdif->play_dma_data.addr = (dma_addr_t)spdif->spdif_base + SPDIF_FIFO_ADDR;
+	spdif->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	spdif->play_dma_data.fifo_size = 16;
+	spdif->play_dma_data.maxburst = 16;
+	spdif->capture_dma_data.addr = (dma_addr_t)spdif->spdif_base + SPDIF_FIFO_ADDR;
+	spdif->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+	spdif->capture_dma_data.fifo_size = 16;
+	spdif->capture_dma_data.maxburst = 16;
+	snd_soc_dai_init_dma_data(dai, &spdif->play_dma_data, &spdif->capture_dma_data);
+	snd_soc_dai_set_drvdata(dai, spdif);
+	#endif
+
+	/* reset */
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+		SPDIF_ENABLE | SPDIF_SFR_ENABLE | SPDIF_FIFO_ENABLE, 0);
+
+	/* clear irq */
+	regmap_update_bits(spdif->regmap, SPDIF_INT_REG,
+		SPDIF_INT_REG_BIT, 0);
+
+	/* power save mode */
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+		SPDIF_CLK_ENABLE, SPDIF_CLK_ENABLE);
+
+	/* power save mode */
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+		SPDIF_CLK_ENABLE, SPDIF_CLK_ENABLE);
+
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+		SPDIF_PARITCHECK|SPDIF_VALIDITYCHECK|SPDIF_DUPLICATE,
+		SPDIF_PARITCHECK|SPDIF_VALIDITYCHECK|SPDIF_DUPLICATE);
+
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+		SPDIF_SETPREAMBB, SPDIF_SETPREAMBB);
+
+	regmap_update_bits(spdif->regmap, SPDIF_INT_REG,
+		0x1FFF<<SPDIF_PREAMBLEDEL, 0x3<<SPDIF_PREAMBLEDEL);
+
+	regmap_update_bits(spdif->regmap, SPDIF_FIFO_CTRL,
+		0xFFFFFFFF, 0x20|(0x20<<SPDIF_AFULL_THRESHOLD));
+
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+		SPDIF_PARITYGEN, SPDIF_PARITYGEN);
+
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+		SPDIF_MASK_ENABLE, SPDIF_MASK_ENABLE);
+
+	/* APB access to FIFO enable, disable if use DMA/FIFO */
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+		SPDIF_USE_FIFO_IF, 0);
+
+	/* two channel */
+	regmap_update_bits(spdif->regmap, SPDIF_CTRL,
+		SPDIF_CHANNEL_MODE, 0);
+
+	return 0;
+}
+
+static const struct snd_soc_dai_ops sf_spdif_dai_ops = {
+	.trigger = sf_spdif_trigger,
+	.hw_params = sf_spdif_hw_params,
+};
+
+#define SF_PCM_RATE_44100_192000  (SNDRV_PCM_RATE_44100 | \
+									SNDRV_PCM_RATE_48000 | \
+									SNDRV_PCM_RATE_96000 | \
+									SNDRV_PCM_RATE_192000)
+
+#define SF_PCM_RATE_8000_22050  (SNDRV_PCM_RATE_8000 | \
+									SNDRV_PCM_RATE_11025 | \
+									SNDRV_PCM_RATE_16000 | \
+									SNDRV_PCM_RATE_22050)
+
+static struct snd_soc_dai_driver sf_spdif_dai = {
+	.name = "spdif",
+	.id = 0,
+	.probe = sf_spdif_dai_probe,
+	.playback = {
+		.stream_name = "Playback",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SF_PCM_RATE_8000_22050,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE \
+					|SNDRV_PCM_FMTBIT_S24_LE \
+					|SNDRV_PCM_FMTBIT_S32_LE,
+	},
+	.capture = {
+		.stream_name = "Capture",
+		.channels_min = 2,
+		.channels_max = 2,
+		.rates = SF_PCM_RATE_8000_22050,
+		.formats = SNDRV_PCM_FMTBIT_S16_LE \
+					|SNDRV_PCM_FMTBIT_S24_LE \
+					|SNDRV_PCM_FMTBIT_S32_LE,
+	},
+	.ops = &sf_spdif_dai_ops,
+	.symmetric_rate = 1,
+};
+
+static const struct snd_soc_component_driver sf_spdif_component = {
+	.name = "sf-spdif",
+};
+
+static const struct regmap_config sf_spdif_regmap_config = {
+	.reg_bits = 32,
+	.reg_stride = 4,
+	.val_bits = 32,
+	.max_register = 0x200,
+};
+
+static int sf_spdif_probe(struct platform_device *pdev)
+{
+	struct sf_spdif_dev *spdif;
+	struct resource *res;
+	void __iomem *base;
+	int ret;
+	int irq;
+
+	spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
+	if (!spdif)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, spdif);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	spdif->spdif_base = base;
+	spdif->regmap = devm_regmap_init_mmio(&pdev->dev, spdif->spdif_base,
+					&sf_spdif_regmap_config);
+	if (IS_ERR(spdif->regmap))
+		return PTR_ERR(spdif->regmap);
+
+	spdif->dev = &pdev->dev;
+	spdif->fifo_th = 16;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq >= 0) {
+		ret = devm_request_irq(&pdev->dev, irq, spdif_irq_handler, 0,
+				pdev->name, spdif);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "failed to request irq\n");
+			return ret;
+		}
+	}
+
+	ret = devm_snd_soc_register_component(&pdev->dev, &sf_spdif_component,
+					 &sf_spdif_dai, 1);
+	if (ret)
+		goto err_clk_disable;
+
+	if (irq >= 0) {
+		ret = sf_spdif_pcm_register(pdev);
+		spdif->use_pio = true;
+	} else {
+		ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
+					0);
+		spdif->use_pio = false;
+	}
+
+	if (ret)
+		goto err_clk_disable;
+
+	return 0;
+
+err_clk_disable:
+	return ret;
+}
+
+static const struct of_device_id sf_spdif_of_match[] = {
+	{ .compatible = "starfive,sf-spdif", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, sf_spdif_of_match);
+
+static struct platform_driver sf_spdif_driver = {
+	.driver = {
+		.name = "sf-spdif",
+		.of_match_table = sf_spdif_of_match,
+	},
+	.probe = sf_spdif_probe,
+};
+module_platform_driver(sf_spdif_driver);
+
+MODULE_AUTHOR("michael.yan <michael.yan@starfive.com>");
+MODULE_DESCRIPTION("starfive SPDIF driver");
+MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/starfive/spdif.h b/sound/soc/starfive/spdif.h
new file mode 100644
index 000000000000..b9b856db701b
--- /dev/null
+++ b/sound/soc/starfive/spdif.h
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef __SND_SOC_STARFIVE_SPDIF_H
+#define __SND_SOC_STARFIVE_SPDIF_H
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/types.h>
+#include <sound/dmaengine_pcm.h>
+#include <sound/pcm.h>
+#include <linux/dmaengine.h>
+#include <linux/types.h>
+
+#define SPDIF_CTRL		(0x0)
+#define SPDIF_INT_REG		(0x4)
+#define SPDIF_FIFO_CTRL		(0x8)
+#define SPDIF_STAT_REG		(0xC)
+
+#define SPDIF_FIFO_ADDR		(0x100)
+#define DMAC_SPDIF_POLLING_LEN	(256)
+
+///ctrl: sampled on the rising clock edge
+#define SPDIF_TSAMPLERATE	0///[SRATEW-1:0]
+#define SPDIF_SFR_ENABLE	(1<<8)	///0:SFR reg reset to defualt value; auto set back to '1' after reset
+#define SPDIF_ENABLE		(1<<9)	///0:reset of SPDIF block, SRF bits are unchanged; 1:enables SPDIF module
+#define SPDIF_FIFO_ENABLE	(1<<10)	///0:FIFO pointers are reset to zero,threshold levels for FIFO are unchaned; auto set back to '1'
+#define SPDIF_CLK_ENABLE	(1<<11)	///1:blocked and the modules are in power save mode; 0:block feeds the modules
+#define SPDIF_TR_MODE		(1<<12)	///0:rx; 1:tx
+#define SPDIF_PARITCHECK	(1<<13)	///0:party bit rx in a sub-frame is repeated on the parity; 1:check on a parity error
+#define SPDIF_PARITYGEN		(1<<14)	///0:parity bit from FIFO is transmitted in sub-frame;1:parity bit generated inside the core and added to a transmitted sub-frame
+#define SPDIF_VALIDITYCHECK	(1<<15)	///0:validity bit in frame isn't checked and all frame are written; 1:validity bit rx is checked
+#define SPDIF_CHANNEL_MODE	(1<<16)	///0:two-channel; 1:single-channel
+#define SPDIF_DUPLICATE		(1<<17)	///only tx -single-channel mode; 0:secondary channel; 1: left(primary) channel
+#define SPDIF_SETPREAMBB	(1<<18)	///only tx; 0:first preamble B after reset tx valid sub-frame; 1:first preamble B is tx after preambleddel(INT_REG)
+#define SPDIF_USE_FIFO_IF	(1<<19)	///0:FIFO disabled ,APB accese FIFO; 1:FIFO enable, APB access to FIFO disable;
+///#define RESERVED		(1<<20)
+#define SPDIF_PARITY_MASK	(1<<21)
+#define SPDIF_UNDERR_MASK	(1<<22)
+#define SPDIF_OVRERR_MASK	(1<<23)
+#define SPDIF_EMPTY_MASK	(1<<24)
+#define SPDIF_AEMPTY_MASK	(1<<25)
+#define SPDIF_FULL_MASK		(1<<26)
+#define SPDIF_AFULL_MASK	(1<<27)
+#define SPDIF_SYNCERR_MASK	(1<<28)
+#define SPDIF_LOCK_MASK		(1<<29)
+#define SPDIF_BEGIN_MASK	(1<<30)
+#define SPDIF_INTEREQ_MAKS	(1<<31)
+
+#define SPDIF_MASK_ENABLE	(SPDIF_PARITY_MASK | SPDIF_UNDERR_MASK | SPDIF_OVRERR_MASK | SPDIF_EMPTY_MASK |	\
+							 SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | SPDIF_AFULL_MASK | SPDIF_SYNCERR_MASK |	\
+							 SPDIF_LOCK_MASK | SPDIF_BEGIN_MASK | SPDIF_INTEREQ_MAKS)
+
+#define SPDIF_MASK_FIFO		(SPDIF_EMPTY_MASK | SPDIF_AEMPTY_MASK | SPDIF_FULL_MASK | SPDIF_AFULL_MASK)
+
+////INT_REG
+#define SPDIF_RSAMPLERATE	0		///[SRATEW-1:0]
+#define SPDIF_PREAMBLEDEL	8		///[PDELAYW+7:8]	first B delay
+#define SPDIF_PARITYO		(1<<21)	///0:clear parity error
+#define SPDIF_TDATA_UNDERR	(1<<22)	///tx data underrun error;0:clear
+#define SPDIF_RDATA_OVRERR	(1<<23)	///rx data overrun error; 0:clear
+#define SPDIF_FIFO_EMPTY	(1<<24)	///empty; 0:clear
+#define SPDIF_FIOF_AEMPTY	(1<<25)	///almost empty; 0:clear
+#define SPDIF_FIFO_FULL		(1<<26)	///FIFO full; 0:clear
+#define SPDIF_FIFO_AFULL	(1<<27)	///FIFO almost full; 0:clear
+#define SPDIF_SYNCERR		(1<<28)	///sync error; 0:clear
+#define SPDIF_LOCK			(1<<29)	///sync; 0:clear
+#define SPDIF_BLOCK_BEGIN	(1<<30)	///new start block rx data
+
+#define SPDIF_INT_REG_BIT	(SPDIF_PARITYO | SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR | SPDIF_FIFO_EMPTY |	\
+							 SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL | SPDIF_SYNCERR | 	\
+							 SPDIF_LOCK | SPDIF_BLOCK_BEGIN)
+
+#define SPDIF_ERROR_INT_STATUS	(SPDIF_PARITYO | SPDIF_TDATA_UNDERR | SPDIF_RDATA_OVRERR)
+#define SPDIF_FIFO_INT_STATUS	(SPDIF_FIFO_EMPTY | SPDIF_FIOF_AEMPTY | SPDIF_FIFO_FULL | SPDIF_FIFO_AFULL)
+
+#define SPDIF_INT_PARITY_ERROR	(-1)
+#define SPDIF_INT_TDATA_UNDERR	(-2)
+#define SPDIF_INT_RDATA_OVRERR	(-3)
+#define SPDIF_INT_FIFO_EMPTY	1
+#define SPDIF_INT_FIFO_AEMPTY	2
+#define SPDIF_INT_FIFO_FULL	3
+#define SPDIF_INT_FIFO_AFULL	4
+#define SPDIF_INT_SYNCERR	(-4)
+#define SPDIF_INT_LOCK		5	// reciever has become synchronized with input data stream
+#define SPDIF_INT_BLOCK_BEGIN	6	// start a new block in recieve data, written into FIFO
+
+///FIFO_CTRL
+#define SPDIF_AEMPTY_THRESHOLD	0	// [depth-1:0]
+#define SPDIF_AFULL_THRESHOLD	16	// [depth+15:16]
+
+///STAT_REG
+#define SPDIF_FIFO_LEVEL	(1<<0)
+#define SPDIF_PARITY_FLAG	(1<<21)	// 1:error; 0:repeated
+#define SPDIF_UNDERR_FLAG	(1<<22)	// 1:error
+#define SPDIF_OVRERR_FLAG	(1<<23)	// 1:error
+#define SPDIF_EMPTY_FLAG	(1<<24)	// 1:fifo empty
+#define SPDIF_AEMPTY_FLAG	(1<<25)	// 1:fifo almost empty
+#define SPDIF_FULL_FLAG		(1<<26)	// 1:fifo full
+#define SPDIF_AFULL_FLAG	(1<<27)	// 1:fifo almost full
+#define SPDIF_SYNCERR_FLAG	(1<<28)	// 1:rx sync error
+#define SPDIF_LOCK_FLAG		(1<<29)	// 1:RX sync
+#define SPDIF_BEGIN_FLAG	(1<<30)	// 1:start a new block
+#define SPDIF_RIGHT_LEFT	(1<<31)	// 1:left channel received and tx into FIFO; 0:right channel received and tx into FIFO
+
+#define SPDIF_STAT		(SPDIF_PARITY_FLAG | SPDIF_UNDERR_FLAG | SPDIF_OVRERR_FLAG | SPDIF_EMPTY_FLAG |		\
+						 SPDIF_AEMPTY_FLAG | SPDIF_FULL_FLAG | SPDIF_AFULL_FLAG | SPDIF_SYNCERR_FLAG | 		\
+						 SPDIF_LOCK_FLAG | SPDIF_BEGIN_FLAG | SPDIF_RIGHT_LEFT)
+struct sf_spdif_dev {
+	void __iomem *spdif_base;
+	struct regmap *regmap;
+	struct device *dev;
+	u32 fifo_th;
+	int active;
+
+	/* data related to DMA transfers b/w i2s and DMAC */
+	struct snd_dmaengine_dai_dma_data play_dma_data;
+	struct snd_dmaengine_dai_dma_data capture_dma_data;
+
+	bool use_pio;
+	struct snd_pcm_substream __rcu *tx_substream;
+	struct snd_pcm_substream __rcu *rx_substream;
+
+	unsigned int (*tx_fn)(struct sf_spdif_dev *dev,
+			struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
+			bool *period_elapsed, snd_pcm_format_t format);
+	unsigned int (*rx_fn)(struct sf_spdif_dev *dev,
+			struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
+			bool *period_elapsed, snd_pcm_format_t format);
+
+	snd_pcm_format_t format;
+	//unsigned int sample_bits;
+	unsigned int tx_ptr;
+	unsigned int rx_ptr;
+
+	struct snd_dmaengine_dai_dma_data dma_data;
+};
+
+#if IS_ENABLED(CONFIG_SND_STARFIVE_SPDIF_PCM)
+void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev);
+void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev);
+int sf_spdif_pcm_register(struct platform_device *pdev);
+#else
+static inline void sf_spdif_pcm_push_tx(struct sf_spdif_dev *dev) { }
+static inline void sf_spdif_pcm_pop_rx(struct sf_spdif_dev *dev) { }
+static inline int sf_spdif_pcm_register(struct platform_device *pdev)
+{
+	return -EINVAL;
+}
+#endif
+
+
+#endif	/* __SND_SOC_STARFIVE_SPDIF_H */
-- 
2.41.0


From 2231550ab5fccc3846324ada117eaa9ff7f1d4a6 Mon Sep 17 00:00:00 2001
From: "sw.multimedia" <sw.multimedia@starfivetech.com>
Date: Tue, 31 Aug 2021 16:48:57 +0800
Subject: [PATCH 68/72] drm/starfive: Add StarFive drm driver
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add starfive DRM Display driver framework

Signed-off-by: jack.zhu <jack.zhu@starfivetech.com>
Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: José Expósito <jose.exposito89@gmail.com>
Link: https://lore.kernel.org/r/a8ca722539672d6369d6e4092e1e08cb6b58c546.1645535955.git.geert@linux-m68k.org
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/gpu/drm/Kconfig                       |   2 +
 drivers/gpu/drm/Makefile                      |   1 +
 drivers/gpu/drm/starfive/Kconfig              |  17 +
 drivers/gpu/drm/starfive/Makefile             |  13 +
 drivers/gpu/drm/starfive/README.txt           |  56 ++
 drivers/gpu/drm/starfive/starfive_drm_crtc.c  | 511 +++++++++++
 drivers/gpu/drm/starfive/starfive_drm_crtc.h  |  86 ++
 drivers/gpu/drm/starfive/starfive_drm_drv.c   | 265 ++++++
 drivers/gpu/drm/starfive/starfive_drm_drv.h   |  25 +
 .../gpu/drm/starfive/starfive_drm_encoder.c   | 129 +++
 .../gpu/drm/starfive/starfive_drm_encoder.h   |  18 +
 drivers/gpu/drm/starfive/starfive_drm_gem.c   | 346 ++++++++
 drivers/gpu/drm/starfive/starfive_drm_gem.h   |  40 +
 drivers/gpu/drm/starfive/starfive_drm_lcdc.c  | 512 +++++++++++
 drivers/gpu/drm/starfive/starfive_drm_lcdc.h  | 160 ++++
 drivers/gpu/drm/starfive/starfive_drm_plane.c | 227 +++++
 drivers/gpu/drm/starfive/starfive_drm_plane.h |  12 +
 drivers/gpu/drm/starfive/starfive_drm_vpp.c   | 806 ++++++++++++++++++
 drivers/gpu/drm/starfive/starfive_drm_vpp.h   | 201 +++++
 drivers/soc/sifive/sifive_ccache.c            |   6 +
 include/soc/sifive/sifive_ccache.h            |   2 +
 21 files changed, 3435 insertions(+)
 create mode 100644 drivers/gpu/drm/starfive/Kconfig
 create mode 100644 drivers/gpu/drm/starfive/Makefile
 create mode 100644 drivers/gpu/drm/starfive/README.txt
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_crtc.c
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_crtc.h
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_drv.c
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_drv.h
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_encoder.c
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_encoder.h
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_gem.c
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_gem.h
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_lcdc.c
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_lcdc.h
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_plane.c
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_plane.h
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_vpp.c
 create mode 100644 drivers/gpu/drm/starfive/starfive_drm_vpp.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index afb3b2f5f425..ee4199c1e8da 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -293,6 +293,8 @@ source "drivers/gpu/drm/renesas/Kconfig"
 
 source "drivers/gpu/drm/sun4i/Kconfig"
 
+source "drivers/gpu/drm/starfive/Kconfig"
+
 source "drivers/gpu/drm/omapdrm/Kconfig"
 
 source "drivers/gpu/drm/tilcdc/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 7a09a89b493b..ca2787b0ec8a 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -160,6 +160,7 @@ obj-$(CONFIG_DRM_ATMEL_HLCDC)	+= atmel-hlcdc/
 obj-y			+= renesas/
 obj-y			+= omapdrm/
 obj-$(CONFIG_DRM_SUN4I) += sun4i/
+obj-$(CONFIG_DRM_STARFIVE) += starfive/
 obj-y			+= tilcdc/
 obj-$(CONFIG_DRM_QXL) += qxl/
 obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/
diff --git a/drivers/gpu/drm/starfive/Kconfig b/drivers/gpu/drm/starfive/Kconfig
new file mode 100644
index 000000000000..df8eea2c6549
--- /dev/null
+++ b/drivers/gpu/drm/starfive/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2021 StarFive Technology Co., Ltd.
+
+config DRM_STARFIVE
+	tristate "DRM Support for StarFive SoCs"
+	depends on DRM
+	depends on SIFIVE_CCACHE
+	depends on SOC_STARFIVE || COMPILE_TEST
+	select DRM_GEM_DMA_HELPER
+	select DRM_KMS_HELPER
+	select DRM_MIPI_DSI
+	select DRM_PANEL
+	help
+	  Choose this option if you have a StarFive SoCs.
+	  The module will be called starfive-drm
+	  This driver provides kernel mode setting and
+	  buffer management to userspace.
diff --git a/drivers/gpu/drm/starfive/Makefile b/drivers/gpu/drm/starfive/Makefile
new file mode 100644
index 000000000000..8ef9e5f469fd
--- /dev/null
+++ b/drivers/gpu/drm/starfive/Makefile
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2021 StarFive Technology Co., Ltd.
+#
+starfive-drm-y := starfive_drm_drv.o \
+		  starfive_drm_gem.o \
+		  starfive_drm_crtc.o \
+		  starfive_drm_encoder.o \
+		  starfive_drm_plane.o \
+		  starfive_drm_lcdc.o \
+		  starfive_drm_vpp.o
+
+obj-$(CONFIG_DRM_STARFIVE) += starfive-drm.o
diff --git a/drivers/gpu/drm/starfive/README.txt b/drivers/gpu/drm/starfive/README.txt
new file mode 100644
index 000000000000..dadec80c98bf
--- /dev/null
+++ b/drivers/gpu/drm/starfive/README.txt
@@ -0,0 +1,56 @@
+Display Subsystem:(default FBdev)
+
+Steps switch to DRM:
+1、Disable fbdev,close below config items：
+CONFIG_FB_STARFIVE=y
+CONFIG_FB_STARFIVE_HDMI_TDA998X=y
+CONFIG_FB_STARFIVE_VIDEO=y
+
+2、open DRM hdmi pipeline,enable items:
+CONFIG_DRM_I2C_NXP_TDA998X=y
+CONFIG_DRM_I2C_NXP_TDA9950=y
+CONFIG_DRM_STARFIVE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+
+Precautions：when use DRM hdmi pipeline,please make sure CONFIG_DRM_STARFIVE_MIPI_DSI is disable ,
+			 or will cause color abnormal.
+
+3、open DRM mipi pipeline
+
+enable items:
+	CONFIG_PHY_M31_DPHY_RX0=y
+	CONFIG_DRM_STARFIVE_MIPI_DSI=y
+
+
+change jh7100.dtsi display-encoder as below：
+
+	display-encoder {
+		compatible = "starfive,display-encoder";
+		encoder-type = <6>; //2-TMDS, 3-LVDS, 6-DSI, 8-DPI
+		status = "okay";
+
+		ports {
+			port@0 {
+				endpoint {
+					remote-endpoint = <&dsi_out_port>;
+				};
+			};
+
+			port@1 {
+				endpoint {
+					remote-endpoint = <&crtc_0_out>;
+				};
+			};
+		};
+	};
+
+install libdrm:
+make buildroot_initramfs-menuconfig
+choose:
+BR2_PACKAGE_LIBDRM=y
+BR2_PACKAGE_LIBDRM_RADEON=y
+BR2_PACKAGE_LIBDRM_AMDGPU=y
+BR2_PACKAGE_LIBDRM_NOUVEAU=y
+BR2_PACKAGE_LIBDRM_ETNAVIV=y
+BR2_PACKAGE_LIBDRM_INSTALL_TESTS=y
+
diff --git a/drivers/gpu/drm/starfive/starfive_drm_crtc.c b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
new file mode 100644
index 000000000000..5ba973377059
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
@@ -0,0 +1,511 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/reset.h>
+#include <linux/delay.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic_uapi.h>
+#include <drm/drm_fb_dma_helper.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+#include <drm/drm_gem_atomic_helper.h>
+#include "starfive_drm_drv.h"
+#include "starfive_drm_crtc.h"
+#include "starfive_drm_plane.h"
+#include "starfive_drm_lcdc.h"
+#include "starfive_drm_vpp.h"
+//#include <video/sys_comm_regs.h>
+
+static inline struct drm_encoder *
+starfive_head_atom_get_encoder(struct starfive_crtc *sf_crtc)
+{
+	struct drm_encoder *encoder = NULL;
+
+	/* We only ever have a single encoder */
+	drm_for_each_encoder_mask(encoder, sf_crtc->crtc.dev,
+				  sf_crtc->crtc.state->encoder_mask)
+		break;
+
+	return encoder;
+}
+
+static int ddrfmt_to_ppfmt(struct starfive_crtc *sf_crtc)
+{
+	int ddrfmt = sf_crtc->ddr_format;
+	int ret = 0;
+
+	sf_crtc->lcdcfmt = WIN_FMT_XRGB8888; //lcdc default used
+	sf_crtc->pp_conn_lcdc = 1;//default config
+	switch (ddrfmt) {
+	case DRM_FORMAT_UYVY:
+		sf_crtc->vpp_format = COLOR_YUV422_UYVY;
+		break;
+	case DRM_FORMAT_VYUY:
+		sf_crtc->vpp_format = COLOR_YUV422_VYUY;
+		break;
+	case DRM_FORMAT_YUYV:
+		sf_crtc->vpp_format = COLOR_YUV422_YUYV;
+		break;
+	case DRM_FORMAT_YVYU:
+		sf_crtc->vpp_format = COLOR_YUV422_YVYU;
+		break;
+	case DRM_FORMAT_YUV420:
+		sf_crtc->vpp_format = COLOR_YUV420P;
+		break;
+	case DRM_FORMAT_NV21:
+		sf_crtc->vpp_format = COLOR_YUV420_NV21;
+		break;
+	case DRM_FORMAT_NV12:
+		sf_crtc->vpp_format = COLOR_YUV420_NV12;
+		break;
+	case DRM_FORMAT_ARGB8888:
+		sf_crtc->vpp_format = COLOR_RGB888_ARGB;
+		break;
+	case DRM_FORMAT_ABGR8888:
+		sf_crtc->vpp_format = COLOR_RGB888_ABGR;
+		break;
+	case DRM_FORMAT_RGBA8888:
+		sf_crtc->vpp_format = COLOR_RGB888_RGBA;
+		break;
+	case DRM_FORMAT_BGRA8888:
+		sf_crtc->vpp_format = COLOR_RGB888_BGRA;
+		break;
+	case DRM_FORMAT_RGB565:
+		sf_crtc->vpp_format = COLOR_RGB565;
+		//sf_crtc->lcdcfmt = WIN_FMT_RGB565;
+		//this format no need pp, lcdc can direct read ddr buff
+		//sf_crtc->pp_conn_lcdc = -1;
+		break;
+	case DRM_FORMAT_XRGB1555:
+		sf_crtc->lcdcfmt = WIN_FMT_XRGB1555;
+		sf_crtc->pp_conn_lcdc = -1;//this format no need pp, lcdc can direct read ddr buff;
+		break;
+	case DRM_FORMAT_XRGB4444:
+		sf_crtc->lcdcfmt = WIN_FMT_XRGB4444;
+		sf_crtc->pp_conn_lcdc = -1;//this format no need pp, lcdc can direct read ddr buff;
+		break;
+
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+void starfive_crtc_hw_config_simple(struct starfive_crtc *starfive_crtc)
+{
+}
+
+static void starfive_crtc_destroy(struct drm_crtc *crtc)
+{
+	drm_crtc_cleanup(crtc);
+}
+
+static void starfive_crtc_destroy_state(struct drm_crtc *crtc,
+					struct drm_crtc_state *state)
+{
+	struct starfive_crtc_state *s = to_starfive_crtc_state(state);
+
+	__drm_atomic_helper_crtc_destroy_state(&s->base);
+	kfree(s);
+}
+
+static void starfive_crtc_reset(struct drm_crtc *crtc)
+{
+	struct starfive_crtc_state *crtc_state =
+	kzalloc(sizeof(*crtc_state), GFP_KERNEL);
+
+	if (crtc->state)
+		starfive_crtc_destroy_state(crtc, crtc->state);
+
+	__drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
+}
+
+static struct drm_crtc_state *starfive_crtc_duplicate_state(struct drm_crtc *crtc)
+{
+	struct starfive_crtc_state *starfive_state;
+
+	starfive_state = kzalloc(sizeof(*starfive_state), GFP_KERNEL);
+	if (!starfive_state)
+		return NULL;
+
+	__drm_atomic_helper_crtc_duplicate_state(crtc, &starfive_state->base);
+
+	return &starfive_state->base;
+}
+
+static int starfive_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+	//need set hw
+	return 0;
+}
+
+static void starfive_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+	//need set hw
+}
+
+static const struct drm_crtc_funcs starfive_crtc_funcs = {
+	.set_config = drm_atomic_helper_set_config,
+	.page_flip = drm_atomic_helper_page_flip,
+	.destroy = starfive_crtc_destroy,
+	.set_property = NULL,
+	.cursor_set = NULL, /* handled by drm_mode_cursor_universal */
+	.cursor_move = NULL, /* handled by drm_mode_cursor_universal */
+	.reset = starfive_crtc_reset,
+	.atomic_duplicate_state = starfive_crtc_duplicate_state,
+	.atomic_destroy_state = starfive_crtc_destroy_state,
+	//.gamma_set = drm_atomic_helper_legacy_gamma_set,
+	.enable_vblank = starfive_crtc_enable_vblank,
+	.disable_vblank = starfive_crtc_disable_vblank,
+	//.set_crc_source = starfive_crtc_set_crc_source,
+	//.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
+	//.verify_crc_source = starfive_crtc_verify_crc_source,
+};
+
+static bool starfive_crtc_mode_fixup(struct drm_crtc *crtc,
+				     const struct drm_display_mode *mode,
+				     struct drm_display_mode *adjusted_mode)
+{
+	/* Nothing to do here, but this callback is mandatory. */
+	return true;
+}
+
+static int starfive_crtc_atomic_check(struct drm_crtc *crtc,
+				      struct drm_atomic_state *state)
+{
+	//state->no_vblank = true;	// hardware without VBLANK interrupt ???
+	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
+										crtc);
+	crtc_state->no_vblank = true;
+
+	return 0;
+}
+
+static void starfive_crtc_atomic_begin(struct drm_crtc *crtc,
+				       struct drm_atomic_state *old_crtc_state)
+{
+	//starfive_crtc_gamma_set(crtcp, crtc, old_crtc_state);
+}
+
+static void starfive_crtc_atomic_flush(struct drm_crtc *crtc,
+				       struct drm_atomic_state *old_crtc_state)
+{
+	struct starfive_crtc *crtcp = to_starfive_crtc(crtc);
+
+	//starfive_flush_dcache(crtcp->dma_addr, 1920*1080*2);
+	DRM_DEBUG_DRIVER("ddr_format_change [%d], dma_addr_change [%d]\n",
+			 crtcp->ddr_format_change, crtcp->dma_addr_change);
+	if (crtcp->ddr_format_change || crtcp->dma_addr_change) {
+		ddrfmt_to_ppfmt(crtcp);
+		starfive_pp_update(crtcp);
+	} else {
+		DRM_DEBUG_DRIVER("%s with no change\n", __func__);
+	}
+}
+
+static void starfive_crtc_atomic_enable(struct drm_crtc *crtc,
+					struct drm_atomic_state *state)
+{
+	struct starfive_crtc *crtcp = to_starfive_crtc(crtc);
+
+// enable crtc HW
+#ifdef CONFIG_DRM_STARFIVE_MIPI_DSI
+	dsitx_vout_init(crtcp);
+	lcdc_dsi_sel(crtcp);
+#else
+	vout_reset(crtcp);
+#endif
+	ddrfmt_to_ppfmt(crtcp);
+	starfive_pp_enable(crtcp);
+	starfive_lcdc_enable(crtcp);
+	crtcp->is_enabled = true;  // should before
+}
+
+static void starfive_crtc_atomic_disable(struct drm_crtc *crtc,
+					 struct drm_atomic_state *state)
+{
+	struct starfive_crtc *crtcp = to_starfive_crtc(crtc);
+	int pp_id;
+
+	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
+		if (crtcp->pp[pp_id].inited == 1) {
+			pp_disable_intr(crtcp, pp_id);
+			vout_disable(crtcp); // disable crtc HW
+		}
+	}
+	crtcp->is_enabled = false;
+}
+
+static enum drm_mode_status starfive_crtc_mode_valid(struct drm_crtc *crtc,
+						     const struct drm_display_mode *mode)
+{
+	int refresh = drm_mode_vrefresh(mode);
+
+	if (refresh > 60) //lcdc miss support 60+ fps
+		return MODE_BAD;
+	else
+		return MODE_OK;
+}
+
+static const struct drm_crtc_helper_funcs starfive_crtc_helper_funcs = {
+	.mode_fixup = starfive_crtc_mode_fixup,
+	.atomic_check = starfive_crtc_atomic_check,
+	.atomic_begin = starfive_crtc_atomic_begin,
+	.atomic_flush = starfive_crtc_atomic_flush,
+	.atomic_enable = starfive_crtc_atomic_enable,
+	.atomic_disable = starfive_crtc_atomic_disable,
+	.mode_valid = starfive_crtc_mode_valid,
+};
+
+static int starfive_crtc_create(struct drm_device *drm_dev,
+				struct starfive_crtc *starfive_crtc,
+				const struct drm_crtc_funcs *crtc_funcs,
+				const struct drm_crtc_helper_funcs *crtc_helper_funcs)
+{
+	struct drm_crtc *crtc = &starfive_crtc->crtc;
+	struct device *dev = drm_dev->dev;
+	struct device_node *port;
+	int ret;
+
+	starfive_crtc->planes = devm_kzalloc(dev, sizeof(struct drm_plane), GFP_KERNEL);
+	ret = starfive_plane_init(drm_dev, starfive_crtc, DRM_PLANE_TYPE_PRIMARY);
+	if (ret) {
+		dev_err(drm_dev->dev, "failed to construct primary plane\n");
+		return ret;
+	}
+
+	drm_crtc_init_with_planes(drm_dev, crtc, starfive_crtc->planes, NULL,
+				  crtc_funcs, NULL);
+	drm_crtc_helper_add(crtc, crtc_helper_funcs);
+	port = of_get_child_by_name(starfive_crtc->dev->of_node, "port");
+	if (!port) {
+		DRM_ERROR("no port node found in %s\n", dev->of_node->full_name);
+		ret = -ENOENT;
+	}
+
+	crtc->port = port;
+	return ret;
+}
+
+static int starfive_crtc_get_memres(struct platform_device *pdev, struct starfive_crtc *sf_crtc)
+{
+	static const char *const mem_res_name[] = {
+		"lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys"
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(mem_res_name); i++) {
+		const char *name = mem_res_name[i];
+		void __iomem *regs = devm_platform_ioremap_resource_byname(pdev, name);
+
+		if (IS_ERR(regs))
+			return PTR_ERR(regs);
+
+		if (!strcmp(name, "lcdc"))
+			sf_crtc->base_lcdc = regs;
+		else if (!strcmp(name, "vpp0"))
+			sf_crtc->base_vpp0 = regs;
+		else if (!strcmp(name, "vpp1"))
+			sf_crtc->base_vpp1 = regs;
+		else if (!strcmp(name, "vpp2"))
+			sf_crtc->base_vpp2 = regs;
+		else if (!strcmp(name, "clk"))
+			sf_crtc->base_clk = regs;
+		else if (!strcmp(name, "rst"))
+			sf_crtc->base_rst = regs;
+		else if (!strcmp(name, "sys"))
+			sf_crtc->base_syscfg = regs;
+		else
+			dev_err(&pdev->dev, "Could not match resource name\n");
+	}
+
+	return 0;
+}
+
+static int starfive_parse_dt(struct device *dev, struct starfive_crtc *sf_crtc)
+{
+	int ret;
+	struct device_node *np = dev->of_node;
+	struct device_node *child;
+	int pp_num = 0;
+
+	if (!np)
+		return -EINVAL;
+
+	sf_crtc->pp = devm_kzalloc(dev, sizeof(struct pp_mode) * PP_NUM, GFP_KERNEL);
+	if (!sf_crtc->pp)
+		return -ENOMEM;
+
+	for_each_child_of_node(np, child) {
+		if (of_property_read_u32(child, "pp-id", &pp_num)) {
+			ret = -EINVAL;
+			continue;
+		}
+		if (pp_num >= PP_NUM)
+			dev_err(dev, " pp-id number %d is not support!\n", pp_num);
+
+		sf_crtc->pp[pp_num].pp_id = pp_num;
+		sf_crtc->pp[pp_num].bus_out = of_property_read_bool(child, "sys-bus-out");
+		sf_crtc->pp[pp_num].fifo_out = of_property_read_bool(child, "fifo-out");
+		if (of_property_read_u32(child, "src-format", &sf_crtc->pp[pp_num].src.format)) {
+			dev_err(dev, "Missing src-format property in the DT.\n");
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "src-width", &sf_crtc->pp[pp_num].src.width)) {
+			dev_err(dev, "Missing src-width property in the DT. w %d\n",
+				sf_crtc->pp[pp_num].src.width);
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "src-height", &sf_crtc->pp[pp_num].src.height)) {
+			dev_err(dev, "Missing src-height property in the DT.\n");
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "dst-format", &sf_crtc->pp[pp_num].dst.format)) {
+			dev_err(dev, "Missing dst-format property in the DT.\n");
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "dst-width", &sf_crtc->pp[pp_num].dst.width)) {
+			dev_err(dev, "Missing dst-width property in the DT.\n");
+			ret = -EINVAL;
+		}
+		if (of_property_read_u32(child, "dst-height", &sf_crtc->pp[pp_num].dst.height)) {
+			dev_err(dev, "Missing dst-height property in the DT.\n");
+			ret = -EINVAL;
+		}
+		sf_crtc->pp[pp_num].inited = 1;
+	}
+
+	return ret;
+}
+
+static int starfive_crtc_bind(struct device *dev, struct device *master, void *data)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct drm_device *drm_dev = data;
+	struct starfive_crtc *crtcp;
+	int ret;
+
+	crtcp = devm_kzalloc(dev, sizeof(*crtcp), GFP_KERNEL);
+	if (!crtcp)
+		return -ENOMEM;
+
+	crtcp->dev = dev;
+	crtcp->drm_dev = drm_dev;
+	dev_set_drvdata(dev, crtcp);
+
+	spin_lock_init(&crtcp->reg_lock);
+
+	ret = starfive_crtc_get_memres(pdev, crtcp);
+	if (ret)
+		return ret;
+
+	crtcp->clk_disp_axi = devm_clk_get(dev, "disp_axi");
+	if (IS_ERR(crtcp->clk_disp_axi))
+		return dev_err_probe(dev, PTR_ERR(crtcp->clk_disp_axi),
+				     "error getting axi clock\n");
+
+	crtcp->clk_vout_src = devm_clk_get(dev, "disp_axi");
+	if (IS_ERR(crtcp->clk_vout_src))
+		return dev_err_probe(dev, PTR_ERR(crtcp->clk_vout_src),
+				     "error getting vout clock\n");
+
+	crtcp->rst_disp_axi = devm_reset_control_get_exclusive(dev, "disp_axi");
+	if (IS_ERR(crtcp->rst_disp_axi))
+		return dev_err_probe(dev, PTR_ERR(crtcp->rst_disp_axi),
+				     "error getting axi reset\n");
+
+	crtcp->rst_vout_src = devm_reset_control_get_exclusive(dev, "vout_src");
+	if (IS_ERR(crtcp->rst_vout_src))
+		return dev_err_probe(dev, PTR_ERR(crtcp->rst_vout_src),
+				     "error getting vout reset\n");
+
+	ret = starfive_parse_dt(dev, crtcp);
+
+	crtcp->pp_conn_lcdc = starfive_pp_get_2lcdc_id(crtcp);
+
+	crtcp->lcdc_irq = platform_get_irq_byname(pdev, "lcdc_irq");
+	if (crtcp->lcdc_irq < 0)
+		return dev_err_probe(dev, crtcp->lcdc_irq, "error getting lcdc irq\n");
+
+	crtcp->vpp1_irq = platform_get_irq_byname(pdev, "vpp1_irq");
+	if (crtcp->vpp1_irq < 0)
+		return dev_err_probe(dev, crtcp->vpp1_irq, "error getting vpp1 irq\n");
+
+	ret = devm_request_irq(&pdev->dev, crtcp->lcdc_irq, lcdc_isr_handler, 0,
+			       "sf_lcdc", crtcp);
+	if (ret)
+		return dev_err_probe(dev, ret, "error requesting irq %d\n", crtcp->lcdc_irq);
+
+	ret = devm_request_irq(&pdev->dev, crtcp->vpp1_irq, vpp1_isr_handler, 0,
+			       "sf_vpp1", crtcp);
+	if (ret)
+		return dev_err_probe(dev, ret, "error requesting irq %d\n", crtcp->vpp1_irq);
+
+	ret = starfive_crtc_create(drm_dev, crtcp,
+				   &starfive_crtc_funcs,
+				   &starfive_crtc_helper_funcs);
+	if (ret)
+		return ret;
+
+	crtcp->is_enabled = false;
+
+	/* starfive_set_crtc_possible_masks(drm_dev, crtcp); */
+
+	/*
+	ret = drm_self_refresh_helper_init(crtcp);
+	if (ret)
+		DRM_DEV_DEBUG_KMS(crtcp->dev,
+			"Failed to init %s with SR helpers %d, ignoring\n",
+			crtcp->name, ret);
+	*/
+
+	return 0;
+}
+
+static void starfive_crtc_unbind(struct device *dev, struct device *master, void *data)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct starfive_crtc *crtcp = dev_get_drvdata(dev);
+
+	drm_crtc_cleanup(&crtcp->crtc);
+	platform_set_drvdata(pdev, NULL);
+}
+
+static const struct component_ops starfive_crtc_component_ops = {
+	.bind   = starfive_crtc_bind,
+	.unbind = starfive_crtc_unbind,
+};
+
+static const struct of_device_id starfive_crtc_driver_dt_match[] = {
+	{ .compatible = "starfive,jh7100-crtc" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, starfive_crtc_driver_dt_match);
+
+static int starfive_crtc_probe(struct platform_device *pdev)
+{
+	return component_add(&pdev->dev, &starfive_crtc_component_ops);
+}
+
+static int starfive_crtc_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &starfive_crtc_component_ops);
+	return 0;
+}
+
+struct platform_driver starfive_crtc_driver = {
+	.probe = starfive_crtc_probe,
+	.remove = starfive_crtc_remove,
+	.driver = {
+		.name = "starfive-crtc",
+		.of_match_table = of_match_ptr(starfive_crtc_driver_dt_match),
+	},
+};
diff --git a/drivers/gpu/drm/starfive/starfive_drm_crtc.h b/drivers/gpu/drm/starfive/starfive_drm_crtc.h
new file mode 100644
index 000000000000..b04706ae8282
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef _STARFIVE_DRM_CRTC_H
+#define _STARFIVE_DRM_CRTC_H
+#include <drm/drm_crtc.h>
+
+enum COLOR_FORMAT {
+	COLOR_YUV422_UYVY = 0,  //00={Y1,V0,Y0,U0}
+	COLOR_YUV422_VYUY = 1,  //01={Y1,U0,Y0,V0}
+	COLOR_YUV422_YUYV = 2,  //10={V0,Y1,U0,Y0}
+	COLOR_YUV422_YVYU = 3,  //11={U0,Y1,V0,Y0}
+
+	COLOR_YUV420P,
+	COLOR_YUV420_NV21,
+	COLOR_YUV420_NV12,
+
+	COLOR_RGB888_ARGB,
+	COLOR_RGB888_ABGR,
+	COLOR_RGB888_RGBA,
+	COLOR_RGB888_BGRA,
+	COLOR_RGB565,
+};
+
+struct starfive_crtc_state {
+	struct drm_crtc_state base;
+};
+
+#define to_starfive_crtc_state(s) \
+		container_of(s, struct starfive_crtc_state, base)
+
+struct starfive_crtc {
+	struct drm_crtc		crtc;
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	bool is_enabled;
+
+	void __iomem	*base_clk;	// 0x12240000
+	void __iomem	*base_rst;	// 0x12250000
+	void __iomem	*base_syscfg;	// 0x12260000
+	void __iomem	*base_vpp0;	// 0x12040000
+	void __iomem	*base_vpp1;	// 0x12080000
+	void __iomem	*base_vpp2;	// 0x120c0000
+	void __iomem	*base_lcdc;	// 0x12000000
+
+	struct clk *clk_disp_axi;
+	struct clk *clk_vout_src;
+
+	struct reset_control *rst_disp_axi;
+	struct reset_control *rst_vout_src;
+
+	int		lcdc_irq;
+	int		vpp0_irq;
+	int		vpp1_irq;
+	int		vpp2_irq;
+
+	struct pp_mode	*pp;
+
+	int		win_num;
+	int		pp_conn_lcdc;
+	unsigned int	ddr_format;
+	bool		ddr_format_change;
+	enum		COLOR_FORMAT vpp_format;
+	int		lcdcfmt;
+
+	/* one time only one process allowed to config the register */
+	spinlock_t	reg_lock;
+
+	struct drm_plane	*planes;
+
+	u8		lut_r[256];
+	u8		lut_g[256];
+	u8		lut_b[256];
+
+	bool		gamma_lut;
+	dma_addr_t	dma_addr;
+	bool		dma_addr_change;
+	size_t		size;
+};
+
+#define to_starfive_crtc(x) container_of(x, struct starfive_crtc, crtc)
+
+void starfive_crtc_hw_config_simple(struct starfive_crtc *starfive_crtc);
+
+#endif /* _STARFIVE_DRM_CRTC_H */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_drv.c b/drivers/gpu/drm/starfive/starfive_drm_drv.c
new file mode 100644
index 000000000000..0027035f3e51
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_drv.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/component.h>
+#include <linux/iommu.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/dma-mapping.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_fbdev_generic.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+#include "starfive_drm_drv.h"
+#include "starfive_drm_gem.h"
+
+#define DRIVER_NAME	"starfive"
+#define DRIVER_DESC	"starfive Soc DRM"
+#define DRIVER_DATE	"20210519"
+#define DRIVER_MAJOR	1
+#define DRIVER_MINOR	0
+
+static struct drm_framebuffer *
+starfive_drm_mode_fb_create(struct drm_device *dev, struct drm_file *file,
+			    const struct drm_mode_fb_cmd2 *mode_cmd)
+{
+	return drm_gem_fb_create(dev, file, mode_cmd);
+}
+
+static const struct drm_mode_config_funcs starfive_drm_mode_config_funcs = {
+	.fb_create = starfive_drm_mode_fb_create,
+	.atomic_check = drm_atomic_helper_check,
+	.atomic_commit = drm_atomic_helper_commit,
+};
+
+static const struct drm_mode_config_helper_funcs starfive_drm_mode_config_helpers = {
+	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+static const struct file_operations starfive_drm_driver_fops = {
+	.owner = THIS_MODULE,
+	.open = drm_open,
+	.mmap = starfive_drm_gem_mmap,
+	.poll = drm_poll,
+	.read = drm_read,
+	.unlocked_ioctl = drm_ioctl,
+	.compat_ioctl = drm_compat_ioctl,
+	.release = drm_release,
+};
+
+static struct drm_driver starfive_drm_driver = {
+	.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
+	.dumb_create = starfive_drm_gem_dumb_create,
+	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+	.gem_prime_import_sg_table = starfive_drm_gem_prime_import_sg_table,
+	.gem_prime_mmap = starfive_drm_gem_mmap_buf,
+	.fops = &starfive_drm_driver_fops,
+	.name = DRIVER_NAME,
+	.desc = DRIVER_DESC,
+	.date = DRIVER_DATE,
+	.major = DRIVER_MAJOR,
+	.minor = DRIVER_MINOR,
+};
+
+static int compare_dev(struct device *dev, void *data)
+{
+	return dev == (struct device *)data;
+}
+
+static void starfive_drm_match_add(struct device *dev,
+				   struct component_match **match,
+				   struct platform_driver *const *drivers,
+				   int count)
+{
+	int i;
+
+	for (i = 0; i < count; i++) {
+		struct device_driver *drv = &drivers[i]->driver;
+		struct device *p = NULL, *d;
+
+		while ((d = platform_find_device_by_driver(p, drv))) {
+			put_device(p);
+			component_match_add(dev, match, compare_dev, d);
+			p = d;
+		}
+		put_device(p);
+	}
+}
+
+static void starfive_cleanup(struct drm_device *ddev)
+{
+	struct starfive_drm_private *private = ddev->dev_private;
+
+	drm_kms_helper_poll_fini(ddev);
+	drm_atomic_helper_shutdown(ddev);
+	drm_mode_config_cleanup(ddev);
+	component_unbind_all(ddev->dev, ddev);
+	kfree(private);
+	ddev->dev_private = NULL;
+}
+
+static int starfive_drm_bind(struct device *dev)
+{
+	struct drm_device *drm_dev;
+	struct starfive_drm_private *private;
+	int ret;
+
+	drm_dev = drm_dev_alloc(&starfive_drm_driver, dev);
+	if (IS_ERR(drm_dev))
+		return PTR_ERR(drm_dev);
+
+	dev_set_drvdata(dev, drm_dev);
+
+	private = devm_kzalloc(drm_dev->dev, sizeof(*private), GFP_KERNEL);
+	if (!private) {
+		ret = -ENOMEM;
+		goto err_free;
+	}
+
+	drm_dev->dev_private = private;
+
+	/*
+	ret = starfive_drm_init_iommu(drm_dev);
+	if (ret)
+		goto err_free;
+	*/
+
+	ret = drmm_mode_config_init(drm_dev);
+	if (ret)
+		goto err_free;
+
+	drm_dev->mode_config.min_width = 64;
+	drm_dev->mode_config.min_height = 64;
+
+	/*
+	 * set max width and height as default value(4096x4096).
+	 * this value would be used to check framebuffer size limitation
+	 * at drm_mode_addfb().
+	 */
+	drm_dev->mode_config.max_width = 4096;
+	drm_dev->mode_config.max_height = 4096;
+	drm_dev->mode_config.funcs = &starfive_drm_mode_config_funcs;
+	drm_dev->mode_config.helper_private = &starfive_drm_mode_config_helpers;
+	drm_dev->mode_config.async_page_flip = 1;
+
+	ret = component_bind_all(dev, drm_dev);
+	if (ret)
+		goto err_free;
+
+	ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc);
+	if (ret)
+		goto err_cleanup;
+
+	drm_mode_config_reset(drm_dev);
+
+	/* init kms poll for handling hpd */
+	drm_kms_helper_poll_init(drm_dev);
+
+	ret = drm_dev_register(drm_dev, 0);
+	if (ret)
+		goto err_cleanup;
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+	drm_fbdev_generic_setup(drm_dev, 16);
+#endif
+	return 0;
+
+err_cleanup:
+	starfive_cleanup(drm_dev);
+err_free:
+	drm_dev_put(drm_dev);
+	return ret;
+}
+
+static void starfive_drm_unbind(struct device *dev)
+{
+	struct drm_device *drm_dev = dev_get_drvdata(dev);
+
+	drm_dev_unregister(drm_dev);
+}
+
+static const struct component_master_ops starfive_drm_ops = {
+	.bind = starfive_drm_bind,
+	.unbind = starfive_drm_unbind,
+};
+
+static struct platform_driver * const starfive_component_drivers[] = {
+	&starfive_crtc_driver,
+#ifdef CONFIG_DRM_STARFIVE_MIPI_DSI
+	&starfive_dsi_platform_driver,
+#endif
+	&starfive_encoder_driver,
+};
+
+static int starfive_drm_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct component_match *match = NULL;
+
+	starfive_drm_match_add(dev, &match,
+			       starfive_component_drivers,
+			       ARRAY_SIZE(starfive_component_drivers));
+	if (IS_ERR(match))
+		return PTR_ERR(match);
+
+	return component_master_add_with_match(dev, &starfive_drm_ops, match);
+}
+
+static int starfive_drm_remove(struct platform_device *pdev)
+{
+	component_master_del(&pdev->dev, &starfive_drm_ops);
+	return 0;
+}
+
+static const struct of_device_id starfive_drm_dt_ids[] = {
+	{ .compatible = "starfive,display-subsystem" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, starfive_drm_dt_ids);
+
+static struct platform_driver starfive_drm_platform_driver = {
+	.probe	= starfive_drm_probe,
+	.remove	= starfive_drm_remove,
+	.driver	= {
+		.name		= "starfive-drm",
+		.of_match_table	= starfive_drm_dt_ids,
+		//.pm     = &starfive_drm_pm_ops,
+	},
+};
+
+static int __init starfive_drm_init(void)
+{
+	int ret;
+
+	ret = platform_register_drivers(starfive_component_drivers,
+					ARRAY_SIZE(starfive_component_drivers));
+	if (ret)
+		return ret;
+
+	return platform_driver_register(&starfive_drm_platform_driver);
+}
+
+static void __exit starfive_drm_exit(void)
+{
+	platform_unregister_drivers(starfive_component_drivers,
+				    ARRAY_SIZE(starfive_component_drivers));
+	platform_driver_unregister(&starfive_drm_platform_driver);
+}
+
+module_init(starfive_drm_init);
+module_exit(starfive_drm_exit);
+
+MODULE_AUTHOR("StarFive <StarFive@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive SoC DRM driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/starfive/starfive_drm_drv.h b/drivers/gpu/drm/starfive/starfive_drm_drv.h
new file mode 100644
index 000000000000..b965fa5f7252
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_drv.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef _STARFIVE_DRM_DRV_H
+#define _STARFIVE_DRM_DRV_H
+
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_gem.h>
+#include <linux/module.h>
+#include <linux/component.h>
+
+struct starfive_drm_private {
+	struct drm_fb_helper fbdev_helper;
+	struct drm_gem_object *fbdev_bo;
+	struct mutex mm_lock;
+	struct drm_mm mm;
+};
+
+extern struct platform_driver starfive_crtc_driver;
+extern struct platform_driver starfive_encoder_driver;
+extern struct platform_driver starfive_dsi_platform_driver;
+
+#endif /* _STARFIVE_DRM_DRV_H_ */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_encoder.c b/drivers/gpu/drm/starfive/starfive_drm_encoder.c
new file mode 100644
index 000000000000..56c7f10239bc
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_encoder.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic_uapi.h>
+#include <drm/drm_fb_dma_helper.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+#include <drm/drm_of.h>
+#include "starfive_drm_drv.h"
+#include "starfive_drm_encoder.h"
+
+static void starfive_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+	kfree(encoder);
+}
+
+static const struct drm_encoder_funcs starfive_encoder_funcs = {
+	.destroy = starfive_encoder_destroy,
+};
+
+static int starfive_encoder_bind(struct device *dev, struct device *master, void *data)
+{
+	struct drm_device *drm_dev = data;
+	struct device_node *np = dev->of_node;
+	struct starfive_encoder *encoderp;
+	int ret;
+	struct drm_panel *tmp_panel;
+	struct drm_bridge *tmp_bridge;
+	u32 crtcs = 0;
+
+	encoderp = devm_kzalloc(dev, sizeof(*encoderp), GFP_KERNEL);
+	if (!encoderp)
+		return -ENOMEM;
+
+	encoderp->dev = dev;
+	encoderp->drm_dev = drm_dev;
+	dev_set_drvdata(dev, encoderp);
+
+	if (dev->of_node) {
+		crtcs = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
+
+		if (of_property_read_u32(np, "encoder-type", &encoderp->encoder_type)) {
+			DRM_ERROR("Missing encoder-type property in the DT.\n");
+			encoderp->encoder_type = DRM_MODE_ENCODER_TMDS;
+		}
+	}
+
+	/* If no CRTCs were found, fall back to our old behaviour */
+	if (crtcs == 0) {
+		dev_warn(dev, "Falling back to first CRTC\n");
+		crtcs = 1 << 0;
+	}
+
+	encoderp->encoder.possible_crtcs = crtcs;
+
+	ret = drm_encoder_init(drm_dev, &encoderp->encoder,
+			       &starfive_encoder_funcs,
+			       encoderp->encoder_type, NULL);
+	if (ret)
+		return dev_err_probe(dev, ret, "error initializing encoder\n");
+
+	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
+					  &tmp_panel, &tmp_bridge);
+	if (ret) {
+		dev_err_probe(dev, ret, "endpoint returns %d\n", ret);
+		goto err_bridge;
+	}
+
+	if (tmp_panel)
+		DRM_INFO("found panel on endpoint\n");
+	if (tmp_bridge)
+		DRM_INFO("found bridge on endpoint\n");
+
+	ret = drm_bridge_attach(&encoderp->encoder, tmp_bridge, NULL, 0);
+	if (ret)
+		goto err_bridge;
+
+	return 0;
+
+err_bridge:
+	drm_encoder_cleanup(&encoderp->encoder);
+	return ret;
+}
+
+static void starfive_encoder_unbind(struct device *dev, struct device *master, void *data)
+{
+	struct starfive_encoder *encoderp = dev_get_drvdata(dev);
+
+	starfive_encoder_destroy(&encoderp->encoder);
+}
+
+static const struct component_ops starfive_encoder_component_ops = {
+	.bind   = starfive_encoder_bind,
+	.unbind = starfive_encoder_unbind,
+};
+
+static const struct of_device_id starfive_encoder_driver_dt_match[] = {
+	{ .compatible = "starfive,display-encoder" },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, starfive_encoder_driver_dt_match);
+
+static int starfive_encoder_probe(struct platform_device *pdev)
+{
+	return component_add(&pdev->dev, &starfive_encoder_component_ops);
+}
+
+static int starfive_encoder_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &starfive_encoder_component_ops);
+	return 0;
+}
+
+struct platform_driver starfive_encoder_driver = {
+	.probe = starfive_encoder_probe,
+	.remove = starfive_encoder_remove,
+	.driver = {
+		.name = "display-encoder",
+		.of_match_table = of_match_ptr(starfive_encoder_driver_dt_match),
+	},
+};
diff --git a/drivers/gpu/drm/starfive/starfive_drm_encoder.h b/drivers/gpu/drm/starfive/starfive_drm_encoder.h
new file mode 100644
index 000000000000..5ea21441e502
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_encoder.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef _STARFIVE_DRM_ENCODER_H
+#define _STARFIVE_DRM_ENCODER_H
+
+struct starfive_encoder {
+	struct drm_encoder	encoder;
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	bool			is_enabled;
+	int			encoder_type;
+};
+
+#define to_starfive_encoder(x) container_of(x, struct starfive_encoder, encoder)
+
+#endif /* _STARFIVE_DRM_CRTC_H */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_gem.c b/drivers/gpu/drm/starfive/starfive_drm_gem.c
new file mode 100644
index 000000000000..59342832cec0
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_gem.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/dma-buf.h>
+#include <linux/iommu.h>
+#include <linux/vmalloc.h>
+#include <drm/drm.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_prime.h>
+#include <drm/drm_vma_manager.h>
+#include <drm/drm_gem_dma_helper.h>
+#include "starfive_drm_drv.h"
+#include "starfive_drm_gem.h"
+
+static const struct drm_gem_object_funcs starfive_gem_object_funcs;
+static const struct vm_operations_struct mmap_mem_ops = {
+#ifdef CONFIG_HAVE_IOREMAP_PROT
+	.access = generic_access_phys
+#endif
+};
+
+static int starfive_drm_gem_object_mmap_dma(struct drm_gem_object *obj,
+					    struct vm_area_struct *vma)
+{
+	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
+	struct drm_device *drm = obj->dev;
+
+	return dma_mmap_attrs(drm->dev, vma, starfive_obj->kvaddr,
+			starfive_obj->dma_addr, obj->size, starfive_obj->dma_attrs);
+}
+
+static int starfive_drm_gem_object_mmap(struct drm_gem_object *obj,
+					struct vm_area_struct *vma)
+{
+	int ret;
+
+	/*
+	 * We allocated a struct page table for rk_obj, so clear
+	 * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap().
+	 */
+	vm_flags_clear(vma, VM_PFNMAP);
+	ret = starfive_drm_gem_object_mmap_dma(obj, vma);
+	if (ret)
+		drm_gem_vm_close(vma);
+
+	return ret;
+}
+
+int starfive_drm_gem_mmap_buf(struct drm_gem_object *obj,
+			      struct vm_area_struct *vma)
+{
+	int ret = drm_gem_mmap_obj(obj, obj->size, vma);
+
+	if (ret)
+		return ret;
+
+	return starfive_drm_gem_object_mmap(obj, vma);
+}
+
+int starfive_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	struct drm_gem_object *obj;
+	int ret;
+
+	ret = drm_gem_mmap(filp, vma);
+	if (ret)
+		return ret;
+
+	obj = vma->vm_private_data;
+
+	/*
+	 * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the
+	 * whole buffer from the start.
+	 */
+	vma->vm_pgoff = 0;
+
+	return starfive_drm_gem_object_mmap(obj, vma);
+}
+
+void starfive_drm_gem_free_object(struct drm_gem_object *obj)
+{
+	struct starfive_drm_gem_obj *starfive_gem = to_starfive_gem_obj(obj);
+	struct drm_device *drm_dev = obj->dev;
+
+	if (starfive_gem->sg)
+		drm_prime_gem_destroy(obj, starfive_gem->sg);
+	else
+		dma_free_attrs(drm_dev->dev, obj->size, starfive_gem->kvaddr,
+			       starfive_gem->dma_addr, starfive_gem->dma_attrs);
+
+	/* release file pointer to gem object. */
+	drm_gem_object_release(obj);
+
+	kfree(starfive_gem);
+}
+
+static struct starfive_drm_gem_obj *
+starfive_drm_gem_alloc_object(struct drm_device *drm, unsigned int size)
+{
+	struct starfive_drm_gem_obj *starfive_obj;
+	struct drm_gem_object *obj;
+	int ret;
+
+	starfive_obj = kzalloc(sizeof(*starfive_obj), GFP_KERNEL);
+	if (!starfive_obj)
+		return ERR_PTR(-ENOMEM);
+
+	obj = &starfive_obj->base;
+	ret = drm_gem_object_init(drm, obj, round_up(size, PAGE_SIZE));
+	if (ret)
+		return ERR_PTR(ret);
+
+	return starfive_obj;
+}
+
+static int starfive_drm_gem_alloc_dma(struct starfive_drm_gem_obj *starfive_obj,
+				      bool alloc_kmap)
+{
+	struct drm_gem_object *obj = &starfive_obj->base;
+	struct drm_device *drm = obj->dev;
+
+	starfive_obj->dma_attrs = DMA_ATTR_WRITE_COMBINE;
+	if (!alloc_kmap)
+		starfive_obj->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
+
+	starfive_obj->kvaddr = dma_alloc_attrs(drm->dev, obj->size,
+					       &starfive_obj->dma_addr, GFP_KERNEL,
+					       starfive_obj->dma_attrs);
+
+	DRM_INFO("kvaddr = 0x%px\n", starfive_obj->kvaddr);
+	DRM_INFO("dma_addr = 0x%llx, size = %lu\n", starfive_obj->dma_addr, obj->size);
+	if (!starfive_obj->kvaddr) {
+		DRM_ERROR("failed to allocate %zu byte dma buffer", obj->size);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int starfive_drm_gem_alloc_buf(struct starfive_drm_gem_obj *starfive_obj,
+				      bool alloc_kmap)
+{
+	return starfive_drm_gem_alloc_dma(starfive_obj, alloc_kmap);
+}
+
+static void starfive_drm_gem_release_object(struct starfive_drm_gem_obj *starfive_obj)
+{
+	drm_gem_object_release(&starfive_obj->base);
+	kfree(starfive_obj);
+}
+
+static struct starfive_drm_gem_obj *
+starfive_drm_gem_create_object(struct drm_device *drm, unsigned int size,
+			       bool alloc_kmap)
+{
+	struct starfive_drm_gem_obj *starfive_obj;
+	int ret;
+
+	starfive_obj = starfive_drm_gem_alloc_object(drm, size);
+	if (IS_ERR(starfive_obj))
+		return starfive_obj;
+
+	ret = starfive_drm_gem_alloc_buf(starfive_obj, alloc_kmap);
+	if (ret)
+		goto err_free_obj;
+
+	starfive_obj->base.funcs = &starfive_gem_object_funcs;
+
+	return starfive_obj;
+
+err_free_obj:
+	starfive_drm_gem_release_object(starfive_obj);
+	return ERR_PTR(ret);
+}
+
+static struct starfive_drm_gem_obj *
+starfive_drm_gem_create_with_handle(struct drm_file *file_priv,
+				    struct drm_device *drm,
+				    unsigned int size,
+				    unsigned int *handle)
+{
+	struct starfive_drm_gem_obj *starfive_gem;
+	struct drm_gem_object *gem;
+	int ret;
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+	//config true, for console display
+	starfive_gem = starfive_drm_gem_create_object(drm, size, true);
+#else
+	starfive_gem = starfive_drm_gem_create_object(drm, size, false);
+#endif
+	if (IS_ERR(starfive_gem))
+		return ERR_CAST(starfive_gem);
+
+	gem = &starfive_gem->base;
+
+	/*
+	 * allocate a id of idr table where the obj is registered
+	 * and handle has the id what user can see.
+	 */
+	ret = drm_gem_handle_create(file_priv, gem, handle);
+	if (ret)
+		goto err_handle_create;
+
+	/* drop reference from allocate - handle holds it now. */
+	drm_gem_object_put(gem);
+
+	return starfive_gem;
+
+err_handle_create:
+	starfive_drm_gem_free_object(gem);
+
+	return ERR_PTR(ret);
+}
+
+int starfive_drm_gem_dumb_create(struct drm_file *file_priv,
+				 struct drm_device *dev,
+				 struct drm_mode_create_dumb *args)
+{
+	struct starfive_drm_gem_obj *starfive_gem;
+
+	args->pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
+	args->size = args->pitch * args->height;
+
+	starfive_gem = starfive_drm_gem_create_with_handle(file_priv, dev,
+							   args->size,
+							   &args->handle);
+
+	return PTR_ERR_OR_ZERO(starfive_gem);
+}
+
+struct sg_table *starfive_drm_gem_prime_get_sg_table(struct drm_gem_object *obj)
+{
+	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
+	struct drm_device *drm = obj->dev;
+	struct sg_table *sgt;
+	int ret;
+
+	if (starfive_obj->pages)
+		return drm_prime_pages_to_sg(obj->dev, starfive_obj->pages,
+					     starfive_obj->num_pages);
+
+	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt)
+		return ERR_PTR(-ENOMEM);
+
+	ret = dma_get_sgtable_attrs(drm->dev, sgt, starfive_obj->kvaddr,
+				    starfive_obj->dma_addr, obj->size,
+				    starfive_obj->dma_attrs);
+	if (ret) {
+		DRM_ERROR("failed to allocate sgt, %d\n", ret);
+		kfree(sgt);
+		return ERR_PTR(ret);
+	}
+
+	return sgt;
+}
+
+static int
+starfive_drm_gem_dma_map_sg(struct drm_device *drm,
+			    struct dma_buf_attachment *attach,
+			    struct sg_table *sg,
+			    struct starfive_drm_gem_obj *starfive_obj)
+{
+	int err;
+
+	err = dma_map_sgtable(drm->dev, sg, DMA_BIDIRECTIONAL, 0);
+	if (err)
+		return err;
+
+	if (drm_prime_get_contiguous_size(sg) < attach->dmabuf->size) {
+		DRM_ERROR("failed to map sg_table to contiguous linear address.\n");
+		dma_unmap_sgtable(drm->dev, sg, DMA_BIDIRECTIONAL, 0);
+		return -EINVAL;
+	}
+
+	starfive_obj->dma_addr = sg_dma_address(sg->sgl);
+	starfive_obj->sg = sg;
+
+	return 0;
+}
+
+struct drm_gem_object *
+starfive_drm_gem_prime_import_sg_table(struct drm_device *drm,
+				       struct dma_buf_attachment *attach,
+				       struct sg_table *sg)
+{
+	struct starfive_drm_gem_obj *starfive_obj;
+	int ret;
+
+	starfive_obj = starfive_drm_gem_alloc_object(drm, attach->dmabuf->size);
+	if (IS_ERR(starfive_obj))
+		return ERR_CAST(starfive_obj);
+
+	ret = starfive_drm_gem_dma_map_sg(drm, attach, sg, starfive_obj);
+	if (ret < 0) {
+		DRM_ERROR("failed to import sg table: %d\n", ret);
+		goto err_free_obj;
+	}
+
+	return &starfive_obj->base;
+
+err_free_obj:
+	starfive_drm_gem_release_object(starfive_obj);
+	return ERR_PTR(ret);
+}
+
+int starfive_drm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map)
+{
+	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
+
+	if (starfive_obj->pages) {
+		void *vaddr = vmap(starfive_obj->pages, starfive_obj->num_pages, VM_MAP,
+						pgprot_writecombine(PAGE_KERNEL));
+		if (!vaddr)
+			return -ENOMEM;
+		iosys_map_set_vaddr(map, vaddr);
+		return 0;
+	}
+
+	if (starfive_obj->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING)
+		return -ENOMEM;
+
+	iosys_map_set_vaddr(map, starfive_obj->kvaddr);
+
+	return 0;
+}
+
+void starfive_drm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map)
+{
+	struct starfive_drm_gem_obj *starfive_obj = to_starfive_gem_obj(obj);
+
+	if (starfive_obj->pages) {
+		vunmap(map->vaddr);
+		return;
+	}
+	/* Nothing to do if allocated by DMA mapping API. */
+}
+
+static const struct drm_gem_object_funcs starfive_gem_object_funcs = {
+	.free		= starfive_drm_gem_free_object,
+	.get_sg_table	= starfive_drm_gem_prime_get_sg_table,
+	.vmap		= starfive_drm_gem_prime_vmap,
+	.vunmap		= starfive_drm_gem_prime_vunmap,
+	.vm_ops		= &drm_gem_dma_vm_ops,
+};
diff --git a/drivers/gpu/drm/starfive/starfive_drm_gem.h b/drivers/gpu/drm/starfive/starfive_drm_gem.h
new file mode 100644
index 000000000000..13a222a26e17
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_gem.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef _STARFIVE_DRM_GEM_H
+#define _STARFIVE_DRM_GEM_H
+
+#include <drm/drm_gem.h>
+
+struct starfive_drm_gem_obj {
+	struct drm_gem_object	base;
+	//void			*cookie; //mtk
+	void			*kvaddr;
+	dma_addr_t		dma_addr;
+	unsigned long		dma_attrs;
+
+	/* Used when IOMMU is enabled */
+	unsigned long		num_pages;
+	struct sg_table		*sg;
+	struct page		**pages;
+};
+
+#define to_starfive_gem_obj(x)	container_of(x, struct starfive_drm_gem_obj, base)
+
+void starfive_drm_gem_free_object(struct drm_gem_object *obj);
+int starfive_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
+int starfive_drm_gem_mmap_buf(struct drm_gem_object *obj,
+			      struct vm_area_struct *vma);
+int starfive_drm_gem_dumb_create(struct drm_file *file_priv,
+				 struct drm_device *dev,
+				 struct drm_mode_create_dumb *args);
+struct sg_table *starfive_drm_gem_prime_get_sg_table(struct drm_gem_object *obj);
+struct drm_gem_object *
+starfive_drm_gem_prime_import_sg_table(struct drm_device *dev,
+				       struct dma_buf_attachment *attach,
+				       struct sg_table *sg);
+int starfive_drm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map);
+void starfive_drm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map);
+
+#endif /* _STARFIVE_DRM_GEM_H */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_lcdc.c b/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
new file mode 100644
index 000000000000..7e9bcbde3092
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_lcdc.c
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/units.h>
+#include <drm/drm_crtc.h>
+#include "starfive_drm_lcdc.h"
+#include "starfive_drm_vpp.h"
+
+static u32 sf_fb_clkread32(struct starfive_crtc *sf_crtc, u32 reg)
+{
+	return ioread32(sf_crtc->base_clk + reg);
+}
+
+static void sf_fb_clkwrite32(struct starfive_crtc *sf_crtc, u32 reg, u32 val)
+{
+	iowrite32(val, sf_crtc->base_clk + reg);
+}
+
+static u32 sf_fb_lcdcread32(struct starfive_crtc *sf_crtc, u32 reg)
+{
+	return ioread32(sf_crtc->base_lcdc + reg);
+}
+
+static void sf_fb_lcdcwrite32(struct starfive_crtc *sf_crtc, u32 reg, u32 val)
+{
+	iowrite32(val, sf_crtc->base_lcdc + reg);
+}
+
+static u32 starfive_lcdc_rstread32(struct starfive_crtc *sf_crtc, u32 reg)
+{
+	return ioread32(sf_crtc->base_rst + reg);
+}
+
+static void starfive_lcdc_rstwrite32(struct starfive_crtc *sf_crtc, u32 reg, u32 val)
+{
+	iowrite32(val, sf_crtc->base_rst + reg);
+}
+
+static void lcdc_mode_cfg(struct starfive_crtc *sf_crtc, u32 work_mode, int dot_edge,
+			  int sync_edge, int r2y_bypass, int src_sel, int int_src, int int_freq)
+{
+	u32 lcdc_en = 0x1;
+	u32 cfg = lcdc_en |
+		work_mode << LCDC_WORK_MODE |
+		dot_edge << LCDC_DOTCLK_P |
+		sync_edge << LCDC_HSYNC_P |
+		sync_edge << LCDC_VSYNC_P |
+		0x0 << LCDC_DITHER_EN |
+		r2y_bypass << LCDC_R2Y_BPS |
+		src_sel << LCDC_TV_LCD_PATHSEL |
+		int_src << LCDC_INT_SEL |
+		int_freq << LCDC_INT_FREQ;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_GCTRL, cfg);
+	dev_dbg(sf_crtc->dev, "LCDC WorkMode: 0x%x, LCDC Path: %d\n", work_mode, src_sel);
+}
+
+static void lcdc_timing_cfg(struct starfive_crtc *sf_crtc,
+			    struct drm_crtc_state *state, int vunit)
+{
+	int hpw, hbk, hfp, vpw, vbk, vfp;
+	u32 htiming, vtiming, hvwid;
+
+	//h-sync
+	int hsync_len = state->adjusted_mode.crtc_hsync_end -
+		state->adjusted_mode.crtc_hsync_start;
+	//h-bp
+	int left_margin = state->adjusted_mode.crtc_htotal -
+		state->adjusted_mode.crtc_hsync_end;
+	//h-fp
+	int right_margin = state->adjusted_mode.crtc_hsync_start -
+		state->adjusted_mode.crtc_hdisplay;
+	//v-sync
+	int vsync_len = state->adjusted_mode.crtc_vsync_end -
+		state->adjusted_mode.crtc_vsync_start;
+	//v-bp
+	int upper_margin = state->adjusted_mode.crtc_vtotal -
+		state->adjusted_mode.crtc_vsync_end;
+	//v-fp
+	int lower_margin = state->adjusted_mode.crtc_vsync_start -
+		state->adjusted_mode.crtc_vdisplay;
+
+	hpw = hsync_len - 1;
+	hbk = hsync_len + left_margin;
+	hfp = right_margin;
+	vpw = vsync_len - 1;
+	vbk = vsync_len + upper_margin;
+	vfp = lower_margin;
+
+	dev_dbg(sf_crtc->dev, "%s: h-sync = %d, h-bp = %d, h-fp = %d", __func__,
+		hsync_len, left_margin, right_margin);
+	dev_dbg(sf_crtc->dev, "%s: v-sync = %d, v-bp = %d, v-fp = %d", __func__,
+		vsync_len, upper_margin, lower_margin);
+
+	htiming = hbk | hfp << LCDC_RGB_HFP;
+	vtiming = vbk | vfp << LCDC_RGB_VFP;
+	hvwid = hpw | vpw << LCDC_RGB_VPW | vunit << LCDC_RGB_UNIT;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_H_TMG, htiming);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_V_TMG, vtiming);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_W_TMG, hvwid);
+	dev_dbg(sf_crtc->dev, "LCDC HPW: %d, HBK: %d, HFP: %d\n", hpw, hbk, hfp);
+	dev_dbg(sf_crtc->dev, "LCDC VPW: %d, VBK: %d, VFP: %d\n", vpw, vbk, vfp);
+	dev_dbg(sf_crtc->dev, "LCDC V-Unit: %d, 0-HSYNC and 1-dotClk period\n", vunit);
+}
+
+//? background size
+//lcdc_desize_cfg(sf_dev, sf_dev->display_info.xres-1, sf_dev->display_info.yres-1);
+static void lcdc_desize_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
+{
+	int hsize = state->adjusted_mode.crtc_hdisplay - 1;
+	int vsize = state->adjusted_mode.crtc_vdisplay - 1;
+	u32 sizecfg = hsize | vsize << LCDC_BG_VSIZE;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_BACKGROUND, sizecfg);
+	dev_dbg(sf_crtc->dev, "LCDC Dest H-Size: %d, V-Size: %d\n", hsize, vsize);
+}
+
+static void lcdc_rgb_dclk_cfg(struct starfive_crtc *sf_crtc, int dot_clk_sel)
+{
+	u32 cfg = dot_clk_sel << 16;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_RGB_DCLK, cfg);
+	dev_dbg(sf_crtc->dev, "LCDC Dot_clock_output_sel: 0x%x\n", cfg);
+}
+
+// color table
+//win0, no lock transfer
+//win3, no src_sel and addr_mode, 0 assigned to them
+//lcdc_win_cfgA(sf_dev, win_num, sf_dev->display_info.xres-1, sf_dev->display_info.yres-1,
+//		0x1, 0x0, 0x0, 0x1, 0x0, 0x0);
+static void lcdc_win_cfgA(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state,
+			  int win_num, int lay_en, int clor_tab,
+			  int color_en, int addr_mode, int lock)
+{
+	int hsize = state->adjusted_mode.crtc_hdisplay - 1;
+	int vsize = state->adjusted_mode.crtc_vdisplay - 1;
+	int src_sel_v = 1;
+	u32 cfg;
+
+	if (sf_crtc->pp_conn_lcdc < 0)
+		src_sel_v = 0;
+
+	cfg = hsize | vsize << LCDC_WIN_VSIZE | lay_en << LCDC_WIN_EN |
+		clor_tab << LCDC_CC_EN | color_en << LCDC_CK_EN |
+		src_sel_v << LCDC_WIN_ISSEL | addr_mode << LCDC_WIN_PM |
+		lock << LCDC_WIN_CLK;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_A + win_num * 0xC, cfg);
+	dev_dbg(sf_crtc->dev,
+		"LCDC Win%d H-Size: %d, V-Size: %d, lay_en: %d, Src: %d, AddrMode: %d\n",
+		win_num, hsize, vsize, lay_en, src_sel_v, addr_mode);
+}
+
+static void lcdc_win_cfgB(struct starfive_crtc *sf_crtc,
+			  int win_num, int xpos, int ypos, int argb_ord)
+{
+	int win_format = sf_crtc->lcdcfmt;
+	u32 cfg;
+
+#ifdef CONFIG_DRM_STARFIVE_MIPI_DSI
+	argb_ord = 0;
+#else
+	argb_ord = 1;
+#endif
+
+	cfg = xpos |
+		ypos << LCDC_WIN_VPOS |
+		win_format << LCDC_WIN_FMT |
+		argb_ord << LCDC_WIN_ARGB_ORDER;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_B + win_num * 0xC, cfg);
+	dev_dbg(sf_crtc->dev,
+		"LCDC Win%d Xpos: %d, Ypos: %d, win_format: 0x%x, ARGB Order: 0x%x\n",
+		win_num, xpos, ypos, win_format, argb_ord);
+}
+
+//? Color key
+static void lcdc_win_cfgC(struct starfive_crtc *sf_crtc, int win_num, int color_key)
+{
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0_CFG_C + win_num * 0xC, color_key);
+	dev_dbg(sf_crtc->dev, "LCDC Win%d Color Key: 0x%6x\n", win_num, color_key);
+}
+
+//? hsize
+//lcdc_win_src_size(sf_dev, win_num, sf_dev->display_info.xres-1);
+static void lcdc_win_src_size(struct starfive_crtc *sf_crtc,
+			      struct drm_crtc_state *state, int win_num)
+{
+	int addr, off, winsize, pre_cfg, cfg;
+	int hsize = state->adjusted_mode.crtc_hdisplay - 1;
+
+	switch (win_num) {
+	case 0:
+		addr = LCDC_WIN01_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
+	case 1:
+		addr = LCDC_WIN01_HSIZE;
+		off = 0xff000fff;
+		winsize = hsize << LCDC_IMG_HSIZE;
+		break;
+	case 2:
+		addr = LCDC_WIN23_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
+	case 3:
+		addr = LCDC_WIN23_HSIZE;
+		off = 0xff000fff;
+		winsize = hsize << LCDC_IMG_HSIZE;
+		break;
+	case 4:
+		addr = LCDC_WIN45_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
+	case 5:
+		addr = LCDC_WIN45_HSIZE;
+		off = 0xff000fff;
+		winsize = hsize << LCDC_IMG_HSIZE;
+		break;
+	case 6:
+		addr = LCDC_WIN67_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
+	case 7:
+		addr = LCDC_WIN67_HSIZE;
+		off = 0xff000fff;
+		winsize = hsize << LCDC_IMG_HSIZE;
+		break;
+	default:
+		addr = LCDC_WIN01_HSIZE;
+		off = 0xfffff000;
+		winsize = hsize;
+		break;
+	}
+	pre_cfg = sf_fb_lcdcread32(sf_crtc, addr) & off;
+	cfg = winsize | pre_cfg;
+	sf_fb_lcdcwrite32(sf_crtc, addr, cfg);
+	dev_dbg(sf_crtc->dev, "LCDC Win%d Src Hsize: %d\n", win_num, hsize);
+}
+
+static void lcdc_alpha_val_cfg(struct starfive_crtc *sf_crtc,
+			       int val1, int val2, int val3, int val4, int sel)
+{
+	u32 val = val1 |
+		val2 << LCDC_ALPHA2 |
+		val3 << LCDC_ALPHA3 |
+		val4 << LCDC_ALPHA4 |
+		sel << LCDC_01_ALPHA_SEL;
+	u32 pre_val = sf_fb_lcdcread32(sf_crtc, LCDC_ALPHA_VALUE) & 0xfffb0000U;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_ALPHA_VALUE, pre_val | val);
+	dev_dbg(sf_crtc->dev, "LCDC Alpha 1: %x, 2: %x, 3: %x, 4: %x\n", val1, val2, val3, val4);
+}
+
+static void lcdc_panel_cfg(struct starfive_crtc *sf_crtc,
+			   int buswid, int depth, int txcycle, int pixpcycle,
+			   int rgb565sel, int rgb888sel)
+{
+	u32 cfg = buswid |
+		depth << LCDC_COLOR_DEP |
+		txcycle << LCDC_TCYCLES |
+		pixpcycle << LCDC_PIXELS |
+		rgb565sel << LCDC_565RGB_SEL |
+		rgb888sel << LCDC_888RGB_SEL;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_PANELDATAFMT, cfg);
+	dev_dbg(sf_crtc->dev, "LCDC bus bit: :%d, pixDep: 0x%x, txCyle: %d, %dpix/cycle, RGB565 2cycle_%d, RGB888 3cycle_%d\n",
+		buswid, depth, txcycle, pixpcycle, rgb565sel, rgb888sel);
+}
+
+//win_num: 0-2
+static void lcdc_win02_addr_cfg(struct starfive_crtc *sf_crtc, int addr0, int addr1)
+{
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR0 + sf_crtc->win_num * 0x8, addr0);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_WIN0STARTADDR1 + sf_crtc->win_num * 0x8, addr1);
+	dev_dbg(sf_crtc->dev, "LCDC Win%d Start Addr0: 0x%8x, Addr1: 0x%8x\n",
+		sf_crtc->win_num, addr0, addr1);
+}
+
+void starfive_set_win_addr(struct starfive_crtc *sf_crtc, int addr)
+{
+	lcdc_win02_addr_cfg(sf_crtc, addr, 0x0);
+}
+
+void lcdc_enable_intr(struct starfive_crtc *sf_crtc)
+{
+	u32 cfg = ~(1U << LCDC_OUT_FRAME_END);
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, cfg);
+}
+
+void lcdc_disable_intr(struct starfive_crtc *sf_crtc)
+{
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, 0xff);
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_CLR, 0xff);
+}
+
+int lcdc_win_sel(struct starfive_crtc *sf_crtc, enum lcdc_in_mode sel)
+{
+	int win_num;
+
+	switch (sel) {
+	case LCDC_IN_LCD_AXI:
+		win_num = LCDC_WIN_0;
+		break;
+	case LCDC_IN_VPP2:
+		win_num = LCDC_WIN_0;
+		break;
+	case LCDC_IN_VPP1:
+		win_num = LCDC_WIN_2;
+		break;
+	case LCDC_IN_VPP0:
+		win_num = LCDC_WIN_1;
+		//mapconv_pp0_sel(sf_dev, 0x0);
+		break;
+	case LCDC_IN_MAPCONVERT:
+		win_num = LCDC_WIN_1;
+		//mapconv_pp0_sel(sf_dev, 0x1);
+		break;
+	default:
+		win_num = 2;
+	}
+
+	return win_num;
+}
+
+void lcdc_dsi_sel(struct starfive_crtc *sf_crtc)
+{
+	int temp;
+	u32 lcdc_en = 0x1;
+	u32 work_mode = 0x1;
+	u32 cfg = lcdc_en | work_mode << LCDC_WORK_MODE;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_GCTRL, cfg);
+	temp = starfive_lcdc_rstread32(sf_crtc, SRST_ASSERT0);
+	temp &= ~(0x1 << BIT_RST_DSI_DPI_PIX);
+	starfive_lcdc_rstwrite32(sf_crtc, SRST_ASSERT0, temp);
+}
+
+irqreturn_t lcdc_isr_handler(int this_irq, void *dev_id)
+{
+	struct starfive_crtc *sf_crtc = dev_id;
+	//u32 intr_status = sf_fb_lcdcread32(sf_crtc, LCDC_INT_STATUS);
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_CLR, 0xffffffff);
+
+	return IRQ_HANDLED;
+}
+
+void lcdc_int_cfg(struct starfive_crtc *sf_crtc, int mask)
+{
+	u32 cfg;
+
+	if (mask == 0x1)
+		cfg = 0xffffffff;
+	else
+		cfg = ~(1U << LCDC_OUT_FRAME_END); //only frame end interrupt mask
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_INT_MSK, cfg);
+}
+
+void lcdc_config(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state, int win_num)
+{
+	lcdc_mode_cfg(sf_crtc, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0);
+	lcdc_timing_cfg(sf_crtc, state, 0);
+	lcdc_desize_cfg(sf_crtc, state);
+	lcdc_rgb_dclk_cfg(sf_crtc, 0x1);
+
+	if (sf_crtc->pp_conn_lcdc < 0) //ddr->lcdc
+		lcdc_win02_addr_cfg(sf_crtc, sf_crtc->dma_addr, 0x0);
+
+	lcdc_win_cfgA(sf_crtc, state, win_num, 0x1, 0x0, 0x0, 0x0, 0x0);
+	lcdc_win_cfgB(sf_crtc, win_num, 0x0, 0x0, 0x0);
+	lcdc_win_cfgC(sf_crtc, win_num, 0xffffff);
+
+	lcdc_win_src_size(sf_crtc, state, win_num);
+	lcdc_alpha_val_cfg(sf_crtc, 0xf, 0xf, 0xf, 0xf, 0x0);
+	lcdc_panel_cfg(sf_crtc, 0x3, 0x4, 0x0, 0x0, 0x0, 0x1);  //rgb888sel?
+}
+
+void lcdc_run(struct starfive_crtc *sf_crtc, u32 win_mode, u32 lcd_trig)
+{
+	u32 runcfg = win_mode << LCDC_EN_CFG_MODE | lcd_trig;
+
+	sf_fb_lcdcwrite32(sf_crtc, LCDC_SWITCH, runcfg);
+	dev_dbg(sf_crtc->dev, "Start run LCDC\n");
+}
+
+static int sf_fb_lcdc_clk_cfg(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
+{
+	u32 reg_val = clk_get_rate(sf_crtc->clk_vout_src) / (state->mode.clock * HZ_PER_KHZ);
+	u32 tmp_val;
+
+	dev_dbg(sf_crtc->dev, "%s: reg_val = %u\n", __func__, reg_val);
+
+	switch (state->adjusted_mode.crtc_hdisplay) {
+	case 640:
+		tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
+		tmp_val &= ~(0x3F);
+		tmp_val |= (59 & 0x3F);
+		sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
+		break;
+	case 840:
+		tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
+		tmp_val &= ~(0x3F);
+		tmp_val |= (54 & 0x3F);
+		sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
+		break;
+	case 1024:
+		tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
+		tmp_val &= ~(0x3F);
+		tmp_val |= (30 & 0x3F);
+		sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
+		break;
+	case 1280:
+		tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
+		tmp_val &= ~(0x3F);
+		tmp_val |= (30 & 0x3F);
+		sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
+		break;
+	case 1440:
+		tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
+		tmp_val &= ~(0x3F);
+		tmp_val |= (30 & 0x3F);
+		sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
+		break;
+	case 1680:
+		tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
+		tmp_val &= ~(0x3F);
+		tmp_val |= (24 & 0x3F);	//24 30MHZ
+		sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
+		break;
+	case 1920:
+		tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
+		tmp_val &= ~(0x3F);
+		tmp_val |= (10 & 0x3F); //20 30MHz , 15  40Mhz, 10 60Mhz
+		sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
+		break;
+	case 2048:
+		tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
+		tmp_val &= ~(0x3F);
+		tmp_val |= (10 & 0x3F);
+		sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
+		break;
+	default:
+		tmp_val = sf_fb_clkread32(sf_crtc, CLK_LCDC_OCLK_CTRL);
+		tmp_val &= ~(0x3F);
+		tmp_val |= (reg_val & 0x3F);
+		sf_fb_clkwrite32(sf_crtc, CLK_LCDC_OCLK_CTRL, tmp_val);
+	}
+
+	return 0;
+}
+
+static int sf_fb_lcdc_init(struct starfive_crtc *sf_crtc, struct drm_crtc_state *state)
+{
+	int pp_id;
+	int lcd_in_pp;
+	int win_num;
+
+	pp_id = sf_crtc->pp_conn_lcdc;
+	if (pp_id < 0) {
+		dev_dbg(sf_crtc->dev, "DDR to LCDC\n");
+		lcd_in_pp = LCDC_IN_LCD_AXI;
+		win_num = lcdc_win_sel(sf_crtc, lcd_in_pp);
+		sf_crtc->win_num = win_num;
+		lcdc_config(sf_crtc, state, win_num);
+	} else {
+		dev_dbg(sf_crtc->dev, "DDR to VPP to LCDC\n");
+		lcd_in_pp = (pp_id == 0) ? LCDC_IN_VPP0 :
+			((pp_id == 1) ? LCDC_IN_VPP1 : LCDC_IN_VPP2);
+		win_num = lcdc_win_sel(sf_crtc, lcd_in_pp);
+		sf_crtc->win_num = win_num;
+		lcdc_config(sf_crtc, state, win_num);
+	}
+
+	return 0;
+}
+
+int starfive_lcdc_enable(struct starfive_crtc *sf_crtc)
+{
+	struct drm_crtc_state *state = sf_crtc->crtc.state;
+
+	lcdc_disable_intr(sf_crtc);
+
+	if (sf_fb_lcdc_clk_cfg(sf_crtc, state)) {
+		dev_err(sf_crtc->dev, "lcdc clock configure fail\n");
+		return -EINVAL;
+	}
+
+	if (sf_fb_lcdc_init(sf_crtc, state)) {
+		dev_err(sf_crtc->dev, "lcdc init fail\n");
+		return -EINVAL;
+	}
+
+	lcdc_run(sf_crtc, sf_crtc->win_num, LCDC_RUN);
+	lcdc_enable_intr(sf_crtc);
+
+	return 0;
+}
+
+MODULE_AUTHOR("StarFive Technology Co., Ltd.");
+MODULE_DESCRIPTION("loadable LCDC driver for StarFive");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/starfive/starfive_drm_lcdc.h b/drivers/gpu/drm/starfive/starfive_drm_lcdc.h
new file mode 100644
index 000000000000..6d03ef82debe
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_lcdc.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef __SF_FB_LCDC_H__
+#define __SF_FB_LCDC_H__
+
+#include "starfive_drm_crtc.h"
+
+enum lcdc_in_mode {
+	LCDC_IN_LCD_AXI = 0,
+	LCDC_IN_VPP2,
+	LCDC_IN_VPP1,
+	LCDC_IN_VPP0,
+	LCDC_IN_MAPCONVERT,
+};
+
+enum lcdc_win_num {
+	LCDC_WIN_0 = 0,
+	LCDC_WIN_1,
+	LCDC_WIN_2,
+	LCDC_WIN_3,
+	LCDC_WIN_4,
+	LCDC_WIN_5,
+};
+
+enum WIN_FMT {
+	WIN_FMT_RGB565 = 4,
+	WIN_FMT_XRGB1555,
+	WIN_FMT_XRGB4444,
+	WIN_FMT_XRGB8888,
+};
+
+#define LCDC_STOP	0
+#define LCDC_RUN	1
+
+//lcdc registers
+#define LCDC_SWITCH		0x0000
+#define LCDC_GCTRL		0x0004
+#define LCDC_INT_STATUS		0x0008
+#define LCDC_INT_MSK		0x000C
+#define LCDC_INT_CLR		0x0010
+#define LCDC_RGB_H_TMG		0x0014
+#define LCDC_RGB_V_TMG		0x0018
+#define LCDC_RGB_W_TMG		0x001C
+#define LCDC_RGB_DCLK		0x0020
+#define LCDC_M_CS_CTRL		0x0024
+#define LCDC_DeltaRGB_CFG	0x0028
+#define LCDC_BACKGROUND		0x002C
+#define LCDC_WIN0_CFG_A		0x0030
+#define LCDC_WIN0_CFG_B		0x0034
+#define LCDC_WIN0_CFG_C		0x0038
+#define LCDC_WIN1_CFG_A		0x003C
+#define LCDC_WIN1_CFG_B		0x0040
+#define LCDC_WIN1_CFG_C		0x0044
+#define LCDC_WIN2_CFG_A		0x0048
+#define LCDC_WIN2_CFG_B		0x004C
+#define LCDC_WIN2_CFG_C		0x0050
+#define LCDC_WIN3_CFG_A		0x0054
+#define LCDC_WIN3_CFG_B		0x0058
+#define LCDC_WIN3_CFG_C		0x005C
+#define LCDC_WIN01_HSIZE	0x0090
+#define LCDC_WIN23_HSIZE	0x0094
+#define LCDC_WIN45_HSIZE	0x0098
+#define LCDC_WIN67_HSIZE	0x009C
+#define LCDC_ALPHA_VALUE	0x00A0
+#define LCDC_PANELDATAFMT	0x00A4
+#define LCDC_WIN0STARTADDR0	0x00B8
+#define LCDC_WIN0STARTADDR1	0x00BC
+
+/* Definition controller bit for LCDC registers */
+//for LCDC_SWITCH
+#define LCDC_DTRANS_SWITCH		0
+#define LCDC_MPU_START			1
+#define LCDC_EN_CFG_MODE		2
+//for LCDC_GCTRL
+#define LCDC_EN				0
+#define LCDC_WORK_MODE			1
+#define LCDC_A0_P			4
+#define LCDC_ENABLE_P			5
+#define LCDC_DOTCLK_P			6
+#define LCDC_HSYNC_P			7
+#define LCDC_VSYNC_P			8
+#define LCDC_DITHER_EN			9
+#define LCDC_R2Y_BPS			10
+#define LCDC_MS_SEL			11
+#define LCDC_TV_LCD_PATHSEL		12
+#define LCDC_INTERLACE			13
+#define LCDC_CBCR_ORDER			14
+#define LCDC_INT_SEL			15
+#define LCDC_INT_FREQ			24
+//for LCDC_INT_MSK
+#define LCDC_OUT_FRAME_END		5
+//for RGB_H_TMG,RGB_V_TMG,RGB_W_TMG
+#define LCDC_RGB_HBK			0
+#define LCDC_RGB_HFP			16
+#define LCDC_RGB_VBK			0
+#define LCDC_RGB_VFP			16
+#define LCDC_RGB_HPW			0
+#define LCDC_RGB_VPW			8
+#define LCDC_RGB_UNIT			16
+//for BACKGROUND
+#define LCDC_BG_HSIZE			0
+#define LCDC_BG_VSIZE			12
+//for WINx_CFG_A/B/C
+#define LCDC_WIN_HSIZE			0
+#define LCDC_WIN_VSIZE			12
+#define LCDC_WIN_EN			24
+#define LCDC_CC_EN			25
+#define LCDC_CK_EN			26
+#define LCDC_WIN_ISSEL			27
+#define LCDC_WIN_PM			28
+#define LCDC_WIN_CLK			30
+#define LCDC_WIN_HPOS			0
+#define LCDC_WIN_VPOS			12
+#define LCDC_WIN_FMT			24
+#define LCDC_WIN_ARGB_ORDER		27
+#define LCDC_WIN_CC			0
+//for WINxx_HSIZE
+#define LCDC_IMG_HSIZE			12
+//for LCDC_ALPHA_VALUE
+#define LCDC_ALPHA1			0
+#define LCDC_ALPHA2			4
+#define LCDC_ALPHA3			8
+#define LCDC_ALPHA4			12
+#define LCDC_A_GLBL_ALPHA		16
+#define LCDC_B_GLBL_ALPHA		17
+#define LCDC_01_ALPHA_SEL		18
+//for LCDC_PANELDATAFMT
+#define LCDC_BUS_W			0
+#define LCDC_TCYCLES			2
+#define LCDC_COLOR_DEP			4
+#define LCDC_PIXELS			7
+#define LCDC_332RGB_SEL			8
+#define LCDC_444RGB_SEL			9
+#define LCDC_666RGB_SEL			12
+#define LCDC_565RGB_SEL			16
+#define LCDC_888RGB_SEL			18
+
+//sysrst registers
+#define SRST_ASSERT0		0x00
+#define SRST_STATUS0		0x04
+/* Definition controller bit for syd rst registers */
+#define BIT_RST_DSI_DPI_PIX	17
+
+void lcdc_enable_intr(struct starfive_crtc *sf_crtc);
+void lcdc_disable_intr(struct starfive_crtc *sf_crtc);
+irqreturn_t lcdc_isr_handler(int this_irq, void *dev_id);
+void lcdc_int_cfg(struct starfive_crtc *sf_crtc, int mask);
+void lcdc_config(struct starfive_crtc *sf_crtc,
+		 struct drm_crtc_state *old_state,
+		 int win_num);
+int lcdc_win_sel(struct starfive_crtc *sf_crtc, enum lcdc_in_mode sel);
+void lcdc_dsi_sel(struct starfive_crtc *sf_crtc);
+void lcdc_run(struct starfive_crtc *sf_crtc,
+	      u32 win_mode, u32 lcd_trig);
+void starfive_set_win_addr(struct starfive_crtc *sf_crtc, int addr);
+int starfive_lcdc_enable(struct starfive_crtc *sf_crtc);
+
+#endif
diff --git a/drivers/gpu/drm/starfive/starfive_drm_plane.c b/drivers/gpu/drm/starfive/starfive_drm_plane.c
new file mode 100644
index 000000000000..119a9fe32769
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_plane.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <drm/drm.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_atomic_uapi.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_gem_atomic_helper.h>
+#include "starfive_drm_crtc.h"
+#include "starfive_drm_plane.h"
+#include "starfive_drm_gem.h"
+#include "starfive_drm_lcdc.h"
+#include "starfive_drm_vpp.h"
+
+static const u32 formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+
+	DRM_FORMAT_YUV420,
+	DRM_FORMAT_NV21,
+	DRM_FORMAT_NV12,
+
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+};
+
+static void starfive_plane_destroy(struct drm_plane *plane)
+{
+	drm_plane_cleanup(plane);
+}
+
+static const struct drm_plane_funcs starfive_plane_funcs = {
+	.update_plane = drm_atomic_helper_update_plane,
+	.disable_plane = drm_atomic_helper_disable_plane,
+	.destroy = starfive_plane_destroy,
+	.set_property = NULL,
+	.reset = drm_atomic_helper_plane_reset,
+	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static void starfive_plane_atomic_disable(struct drm_plane *plane,
+					  struct drm_atomic_state *old_state)
+{
+}
+
+static int starfive_plane_atomic_check(struct drm_plane *plane,
+				       struct drm_atomic_state *state)
+{
+	struct drm_plane_state *new_plane_state =
+		drm_atomic_get_new_plane_state(state, plane);
+	struct drm_framebuffer *fb = new_plane_state->fb;
+	struct drm_crtc_state *crtc_state;
+
+	if (!fb)
+		return 0;
+
+	if (WARN_ON(!new_plane_state->crtc))
+		return 0;
+
+	/*
+	ret = starfive_drm_plane_check(state->crtc, plane,
+				       to_starfive_plane_state(state));
+	if (ret)
+		return ret;
+	*/
+
+	//crtc_state = drm_atomic_get_crtc_state(new_plane_state->state, new_plane_state->crtc);
+	crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);
+	if (IS_ERR(crtc_state))
+		return PTR_ERR(crtc_state);
+
+	return drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+				DRM_PLANE_NO_SCALING,
+				DRM_PLANE_NO_SCALING,
+				true, true);
+}
+
+static void starfive_plane_atomic_update(struct drm_plane *plane,
+					 struct drm_atomic_state *old_state)
+{
+	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(old_state,
+										plane);
+	struct drm_crtc *crtc = new_state->crtc;
+	struct drm_framebuffer *fb = new_state->fb;
+	//struct drm_plane_state *state = plane->state;
+	//struct drm_crtc *crtc = state->crtc;
+	//struct drm_framebuffer *fb = state->fb;
+
+	dma_addr_t dma_addr;
+	struct drm_gem_object *obj;
+	struct starfive_drm_gem_obj *starfive_obj;
+	unsigned int pitch, format;
+
+	struct starfive_crtc *sf_crtc = to_starfive_crtc(crtc);
+
+	if (!crtc || WARN_ON(!fb))
+		return;
+
+	//if (!plane->state->visible) {
+	if (!new_state->visible) {
+		starfive_plane_atomic_disable(plane, old_state);
+		return;
+	}
+
+	obj = fb->obj[0];
+	starfive_obj = to_starfive_gem_obj(obj);
+	dma_addr = starfive_obj->dma_addr;
+	pitch = fb->pitches[0];
+	format = fb->format->format;
+
+	//dma_addr += (plane->state->src.x1 >> 16) * fb->format->cpp[0];
+	//dma_addr += (plane->state->src.y1 >> 16) * pitch;
+	dma_addr += (new_state->src.x1 >> 16) * fb->format->cpp[0];
+	dma_addr += (new_state->src.y1 >> 16) * pitch;
+	if (sf_crtc->ddr_format != format) {
+		sf_crtc->ddr_format = format;
+		sf_crtc->ddr_format_change = true;
+	} else {
+		sf_crtc->ddr_format_change = false;
+	}
+
+	if (sf_crtc->dma_addr != dma_addr) {
+		sf_crtc->dma_addr = dma_addr;
+		sf_crtc->dma_addr_change = true;
+	} else {
+		sf_crtc->dma_addr_change = false;
+	}
+	sf_crtc->size = obj->size;
+}
+
+static int starfive_plane_atomic_async_check(struct drm_plane *plane,
+					     struct drm_atomic_state *state)
+{
+	struct drm_crtc_state *crtc_state;
+	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
+										 plane);
+
+	if (plane != new_plane_state->crtc->cursor)
+		return -EINVAL;
+
+	if (!plane->state)
+		return -EINVAL;
+
+	if (!plane->state->fb)
+		return -EINVAL;
+
+	//if (new_plane_state->state)
+	//   crtc_state = drm_atomic_get_existing_crtc_state(new_plane_state->state,
+	//						   new_plane_state->crtc);
+	//else /* Special case for asynchronous cursor updates. */
+	//  crtc_state = new_plane_state->crtc->state;
+
+	if (state)
+		crtc_state = drm_atomic_get_existing_crtc_state(state,
+								new_plane_state->crtc);
+	else /* Special case for asynchronous cursor updates. */
+		//crtc_state = plane->crtc->state;
+		crtc_state = new_plane_state->crtc->state;
+
+	return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
+				DRM_PLANE_NO_SCALING,
+				DRM_PLANE_NO_SCALING,
+				true, true);
+}
+
+static void starfive_plane_atomic_async_update(struct drm_plane *plane,
+					       struct drm_atomic_state *new_state)
+{
+	struct drm_plane_state *new_plane_state =
+		drm_atomic_get_new_plane_state(new_state, plane);
+	struct starfive_crtc *crtcp = to_starfive_crtc(plane->state->crtc);
+
+	plane->state->crtc_x = new_plane_state->crtc_x;
+	plane->state->crtc_y = new_plane_state->crtc_y;
+	plane->state->crtc_h = new_plane_state->crtc_h;
+	plane->state->crtc_w = new_plane_state->crtc_w;
+	plane->state->src_x = new_plane_state->src_x;
+	plane->state->src_y = new_plane_state->src_y;
+	plane->state->src_h = new_plane_state->src_h;
+	plane->state->src_w = new_plane_state->src_w;
+	swap(plane->state->fb, new_plane_state->fb);
+
+	if (crtcp->is_enabled) {
+		starfive_plane_atomic_update(plane, new_state);
+		spin_lock(&crtcp->reg_lock);
+		starfive_crtc_hw_config_simple(crtcp);
+		spin_unlock(&crtcp->reg_lock);
+	}
+}
+
+static const struct drm_plane_helper_funcs starfive_plane_helper_funcs = {
+	.atomic_check = starfive_plane_atomic_check,
+	.atomic_update = starfive_plane_atomic_update,
+	//.prepare_fb = drm_gem_fb_prepare_fb,
+	.prepare_fb = drm_gem_plane_helper_prepare_fb,
+	.atomic_disable = starfive_plane_atomic_disable,
+	.atomic_async_check = starfive_plane_atomic_async_check,
+	.atomic_async_update = starfive_plane_atomic_async_update,
+};
+
+int starfive_plane_init(struct drm_device *dev,
+			struct starfive_crtc *starfive_crtc,
+			enum drm_plane_type type)
+{
+	int ret;
+
+	ret = drm_universal_plane_init(dev, starfive_crtc->planes, 0,
+				       &starfive_plane_funcs, formats,
+				       ARRAY_SIZE(formats), NULL, type, NULL);
+	if (ret) {
+		dev_err(dev->dev, "failed to initialize plane\n");
+		return ret;
+	}
+
+	drm_plane_helper_add(starfive_crtc->planes, &starfive_plane_helper_funcs);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/starfive/starfive_drm_plane.h b/drivers/gpu/drm/starfive/starfive_drm_plane.h
new file mode 100644
index 000000000000..04c3637d4fa6
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_plane.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef _STARFIVE_DRM_PLANE_H
+#define _STARFIVE_DRM_PLANE_H
+
+int starfive_plane_init(struct drm_device *dev,
+			struct starfive_crtc *starfive_crtc,
+			enum drm_plane_type type);
+
+#endif /* _STARFIVE_DRM_PLANE_H */
diff --git a/drivers/gpu/drm/starfive/starfive_drm_vpp.c b/drivers/gpu/drm/starfive/starfive_drm_vpp.c
new file mode 100644
index 000000000000..5cada21d2651
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.c
@@ -0,0 +1,806 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/reset.h>
+#include <linux/delay.h>
+#include "starfive_drm_vpp.h"
+#include "starfive_drm_crtc.h"
+#include <soc/sifive/sifive_ccache.h>
+
+static inline void sf_set_clear(void __iomem *addr, u32 reg, u32 set, u32 clear)
+{
+	u32 value = ioread32(addr + reg);
+
+	value &= ~clear;
+	value |= set;
+	iowrite32(value, addr + reg);
+}
+
+static u32 sf_fb_sysread32(struct starfive_crtc *sf_crtc, u32 reg)
+{
+	return ioread32(sf_crtc->base_syscfg + reg);
+}
+
+static void sf_fb_syswrite32(struct starfive_crtc *sf_crtc, u32 reg, u32 val)
+{
+	iowrite32(val, sf_crtc->base_syscfg + reg);
+}
+
+static u32 sf_fb_vppread32(struct starfive_crtc *sf_crtc, int pp_num, u32 reg)
+{
+	void __iomem *base_vpp;
+
+	switch (pp_num) {
+	case 0:
+		base_vpp = sf_crtc->base_vpp0;
+		break;
+	case 1:
+		base_vpp = sf_crtc->base_vpp1;
+		break;
+	case 2:
+		base_vpp = sf_crtc->base_vpp2;
+		break;
+	default:
+		dev_err(sf_crtc->dev, "Err：invalid vpp Number!\n");
+		return 0;
+	}
+
+	return ioread32(base_vpp + reg);
+}
+
+static void sf_fb_vppwrite32(struct starfive_crtc *sf_crtc, int pp_num, u32 reg, u32 val)
+{
+	void __iomem *base_vpp;
+
+	switch (pp_num) {
+	case 0:
+		base_vpp = sf_crtc->base_vpp0;
+		break;
+	case 1:
+		base_vpp = sf_crtc->base_vpp1;
+		break;
+	case 2:
+		base_vpp = sf_crtc->base_vpp2;
+		break;
+	default:
+		dev_err(sf_crtc->dev, "Err：invalid vpp Number!\n");
+		return;
+	}
+	iowrite32(val, base_vpp + reg);
+}
+
+void mapconv_pp0_sel(struct starfive_crtc *sf_crtc, int sel)
+{
+	u32 temp;
+
+	temp = sf_fb_sysread32(sf_crtc, SYS_MAP_CONV);
+	temp &= ~(0x1);
+	temp |= (sel & 0x1);
+	sf_fb_syswrite32(sf_crtc, SYS_MAP_CONV, temp);
+}
+
+static void pp_output_cfg(struct starfive_crtc *sf_crtc,
+			  int pp_num, int out_sel, int prog_inter, int desformat,
+			  int pt_mode)
+{
+	int cfg = out_sel | prog_inter << PP_INTERLACE |
+		desformat << PP_DES_FORMAT |
+		pt_mode << PP_POINTER_MODE;
+	int pre_cfg = sf_fb_vppread32(sf_crtc, pp_num, PP_CTRL1) & 0xffff8f0U;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_CTRL1, cfg | pre_cfg);
+	dev_dbg(sf_crtc->dev, "PP%d out_sel: %d, outFormat: 0x%x, Out Interlace: %d, pt_mode: %d\n",
+		pp_num, out_sel, desformat, prog_inter, pt_mode);
+}
+
+static void pp_srcfmt_cfg(struct starfive_crtc *sf_crtc, int pp_num, int srcformat,
+			  int yuv420_inter, int yuv422_mode, int yuv420_mode, int argb_ord)
+{
+	int cfg = srcformat << PP_SRC_FORMAT_N |
+		yuv420_inter << PP_420_ITLC |
+		yuv422_mode << PP_SRC_422_YUV_POS |
+		yuv420_mode << PP_SRC_420_YUV_POS |
+		argb_ord << PP_SRC_ARGB_ORDER;
+	int pre_cfg = sf_fb_vppread32(sf_crtc, pp_num, PP_CTRL1) & 0x83ffff0fU;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_CTRL1, cfg | pre_cfg);
+	dev_dbg(sf_crtc->dev, "PP%d Src Format: 0x%x, YUV420 Interlace: %d, YUV422: %d, YUV420: %d, ARGB Order: %d\n",
+		pp_num, srcformat, yuv420_inter, yuv422_mode, yuv420_mode, argb_ord);
+}
+
+static void pp_r2yscal_bypass(struct starfive_crtc *sf_crtc,
+			      int pp_num, int r2y_byp, int scal_byp, int y2r_byp)
+{
+	int bypass = (r2y_byp | scal_byp << 1 | y2r_byp << 2) << PP_R2Y_BPS;
+	int pre_cfg = sf_fb_vppread32(sf_crtc, pp_num, PP_CTRL1) & 0xffff8fffU;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_CTRL1, bypass | pre_cfg);
+	dev_dbg(sf_crtc->dev, "PP%d Bypass R2Y: %d, Y2R: %d, MainSacle: %d\n",
+		pp_num, r2y_byp, y2r_byp, scal_byp);
+}
+
+static void pp_argb_alpha(struct starfive_crtc *sf_crtc, int pp_num, int alpha)
+{
+	int pre_cfg = sf_fb_vppread32(sf_crtc, pp_num, PP_CTRL1) & 0xff00ffffU;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_CTRL1, alpha << PP_ARGB_ALPHA | pre_cfg);
+	dev_dbg(sf_crtc->dev, "PP%d Alpha: 0x%4x\n", pp_num, alpha);
+}
+
+//rgbNum: 1-3
+static void pp_r2y_coeff(struct starfive_crtc *sf_crtc,
+			 int pp_num, int coef_num, int rcoef, int gcoef, int bcoef, int off)
+{
+	int rgcoeff = rcoef | gcoef << PP_COEF_G1;
+	int bcoefoff = bcoef | off << PP_OFFSET_1;
+	u32 addr1 = (coef_num - 1) * 0x8 + PP_R2Y_COEF1;
+	u32 addr2 = (coef_num - 1) * 0x8 + PP_R2Y_COEF2;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, addr1, rgcoeff);
+	sf_fb_vppwrite32(sf_crtc, pp_num, addr2, bcoefoff);
+	dev_dbg(sf_crtc->dev, "PP%d coef_num: %d, rCoef: 0x%4x, gCoef: 0x%4x, bCoef: 0x%4x, off: 0x%4x\n",
+		pp_num, coef_num, rcoef, gcoef, bcoef, off);
+}
+
+static void pp_output_fmt_cfg(struct starfive_crtc *sf_crtc,
+			      int pp_num, int yuv420_inter, int yuv422_mode)
+{
+	int pre_cfg = sf_fb_vppread32(sf_crtc, pp_num, PP_CTRL2) & 0xfffffffeU;
+
+	pre_cfg = pre_cfg |
+		yuv420_inter << PP_DES_420_ORDER |
+		yuv422_mode << PP_DES_422_ORDER;
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_CTRL2, pre_cfg);
+	dev_dbg(sf_crtc->dev, "PP%d Lock Transfer: %d\n", pp_num, yuv422_mode);
+}
+
+static void pp_lock_trans_cfg(struct starfive_crtc *sf_crtc, int pp_num, int lock_trans)
+{
+	int pre_cfg = sf_fb_vppread32(sf_crtc, pp_num, PP_CTRL2) & 0xfffffffeU;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_CTRL2, lock_trans | pre_cfg);
+	dev_dbg(sf_crtc->dev, "PP%d Lock Transfer: %d\n", pp_num, lock_trans);
+}
+
+static void pp_int_interval_cfg(struct starfive_crtc *sf_crtc, int pp_num, int interval)
+{
+	int pre_cfg = sf_fb_vppread32(sf_crtc, pp_num, PP_CTRL2) & 0xffff00ffU;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_CTRL2, interval << PP_INT_INTERVAL | pre_cfg);
+	dev_dbg(sf_crtc->dev, "PP%d Frame Interrupt interval: %d Frames\n", pp_num, interval);
+}
+
+static void pp_src_size_cfg(struct starfive_crtc *sf_crtc, int pp_num, int hsize, int vsize)
+{
+	int size = hsize | vsize << PP_SRC_VSIZE;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_SRC_SIZE, size);
+	dev_dbg(sf_crtc->dev, "PP%d HSize: %d, VSize: %d\n", pp_num, hsize, vsize);
+}
+
+//0-no drop, 1-1/2, 2-1/4, down to 1/32
+static void pp_drop_cfg(struct starfive_crtc *sf_crtc, int pp_num, int hdrop, int vdrop)
+{
+	int drop = hdrop | vdrop << PP_DROP_VRATION;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_DROP_CTRL, drop);
+	dev_dbg(sf_crtc->dev, "PP%d HDrop: %d, VDrop: %d\n", pp_num, hdrop, vdrop);
+}
+
+static void pp_des_size_cfg(struct starfive_crtc *sf_crtc, int pp_num, int hsize, int vsize)
+{
+	int size = hsize | vsize << PP_DES_VSIZE;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_DES_SIZE, size);
+	dev_dbg(sf_crtc->dev, "PP%d HSize: %d, VSize: %d\n", pp_num, hsize, vsize);
+}
+
+static void pp_des_addr_cfg(struct starfive_crtc *sf_crtc,
+			    int pp_num, int yaddr, int uaddr, int vaddr)
+{
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_DES_Y_SA, yaddr);
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_DES_U_SA, uaddr);
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_DES_V_SA, vaddr);
+	dev_dbg(sf_crtc->dev, "PP%d des-Addr Y: 0x%8x, U: 0x%8x, V: 0x%8x\n",
+		pp_num, yaddr, uaddr, vaddr);
+}
+
+static void pp_des_offset_cfg(struct starfive_crtc *sf_crtc,
+			      int pp_num, int yoff, int uoff, int voff)
+{
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_DES_Y_OFS, yoff);
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_DES_U_OFS, uoff);
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_DES_V_OFS, voff);
+	dev_dbg(sf_crtc->dev, "PP%d des-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n",
+		pp_num, yoff, uoff, voff);
+}
+
+void pp_intcfg(struct starfive_crtc *sf_crtc, int pp_num, int int_mask)
+{
+	int intcfg = ~(0x1 << 0);
+
+	if (int_mask)
+		intcfg = 0xf;
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_INT_MASK, intcfg);
+}
+
+//next source frame Y/RGB start address, ?
+void pp_src_addr_next(struct starfive_crtc *sf_crtc, int pp_num, int ysa, int usa, int vsa)
+{
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_SRC_Y_SA_NXT, ysa);
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_SRC_U_SA_NXT, usa);
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_SRC_V_SA_NXT, vsa);
+	dev_dbg(sf_crtc->dev,
+		"PP%d next Y startAddr: 0x%8x, U startAddr: 0x%8x, V startAddr: 0x%8x\n",
+		pp_num, ysa, usa, vsa);
+}
+
+void pp_src_offset_cfg(struct starfive_crtc *sf_crtc, int pp_num, int yoff, int uoff, int voff)
+{
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_SRC_Y_OFS, yoff);
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_SRC_U_OFS, uoff);
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_SRC_V_OFS, voff);
+	dev_dbg(sf_crtc->dev, "PP%d src-Offset Y: 0x%4x, U: 0x%4x, V: 0x%4x\n",
+		pp_num, yoff, uoff, voff);
+}
+
+void pp_nxt_addr_load(struct starfive_crtc *sf_crtc, int pp_num, int nxt_par, int nxt_pos)
+{
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_LOAD_NXT_PAR, nxt_par | nxt_pos);
+	dev_dbg(sf_crtc->dev, "PP%d next addrPointer: %d, %d set Regs\n", pp_num, nxt_par, nxt_pos);
+}
+
+void pp_run(struct starfive_crtc *sf_crtc, int pp_num, int start)
+{
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_SWITCH, start);
+	//if (start)
+	//	dev_dbg(sf_crtc->dev, "Now start the PP%d\n\n", pp_num);
+}
+
+void pp1_enable_intr(struct starfive_crtc *sf_crtc)
+{
+	sf_fb_vppwrite32(sf_crtc, 1, PP_INT_MASK, 0x0);
+}
+
+void pp_enable_intr(struct starfive_crtc *sf_crtc, int pp_num)
+{
+	u32 cfg = 0xfffe;
+
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_INT_MASK, cfg);
+}
+
+void pp_disable_intr(struct starfive_crtc *sf_crtc, int pp_num)
+{
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_INT_MASK, 0xf);
+	sf_fb_vppwrite32(sf_crtc, pp_num, PP_INT_CLR, 0xf);
+}
+
+static void pp_srcfmt_set(struct starfive_crtc *sf_crtc, int pp_num, struct pp_video_mode *src)
+{
+	switch (src->format) {
+	case COLOR_YUV422_YVYU:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_YUV422, 0x0, COLOR_YUV422_YVYU, 0x0, 0x0);
+		break;
+	case COLOR_YUV422_VYUY:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_YUV422, 0x0, COLOR_YUV422_VYUY, 0x0, 0x0);
+		break;
+	case COLOR_YUV422_YUYV:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_YUV422, 0x0, COLOR_YUV422_YUYV, 0x0, 0x0);
+		break;
+	case COLOR_YUV422_UYVY:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_YUV422, 0x0, COLOR_YUV422_UYVY, 0x0, 0x0);
+		break;
+	case COLOR_YUV420P:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_YUV420P, 0x0, 0, 0x0, 0x0);
+		break;
+	case COLOR_YUV420_NV21:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_YUV420I, 0x1, 0,
+			      COLOR_YUV420_NV21 - COLOR_YUV420_NV21, 0x0);
+		break;
+	case COLOR_YUV420_NV12:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_YUV420I, 0x1, 0,
+			      COLOR_YUV420_NV12 - COLOR_YUV420_NV21, 0x0);
+		break;
+	case COLOR_RGB888_ARGB:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_GRB888, 0x0, 0x0,
+			      0x0, COLOR_RGB888_ARGB - COLOR_RGB888_ARGB);
+		break;
+	case COLOR_RGB888_ABGR:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_GRB888, 0x0, 0x0,
+			      0x0, COLOR_RGB888_ABGR - COLOR_RGB888_ARGB);
+		break;
+	case COLOR_RGB888_RGBA:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_GRB888, 0x0, 0x0,
+			      0x0, COLOR_RGB888_RGBA - COLOR_RGB888_ARGB);
+		break;
+	case COLOR_RGB888_BGRA:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_GRB888, 0x0, 0x0,
+			      0x0, COLOR_RGB888_BGRA - COLOR_RGB888_ARGB);
+		break;
+	case COLOR_RGB565:
+		pp_srcfmt_cfg(sf_crtc, pp_num, PP_SRC_RGB565, 0x0, 0x0, 0x0, 0x0);
+		break;
+	}
+}
+
+static void pp_dstfmt_set(struct starfive_crtc *sf_crtc, int pp_num, struct pp_video_mode *dst)
+{
+	unsigned int outsel = 1;
+
+	if (dst->addr)
+		outsel = 0;
+
+	switch (dst->format) {
+	case COLOR_YUV422_YVYU:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_YUV422, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
+		break;
+	case COLOR_YUV422_VYUY:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_YUV422, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, 0, COLOR_YUV422_UYVY - COLOR_YUV422_VYUY);
+		break;
+	case COLOR_YUV422_YUYV:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_YUV422, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YUYV);
+		break;
+	case COLOR_YUV422_UYVY:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_YUV422, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, 0, COLOR_YUV422_UYVY - COLOR_YUV422_YVYU);
+		break;
+	case COLOR_YUV420P:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_YUV420P, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, 0, 0);
+		break;
+	case COLOR_YUV420_NV21:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_YUV420I, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, COLOR_YUV420_NV21 - COLOR_YUV420_NV21, 0);
+		break;
+	case COLOR_YUV420_NV12:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_YUV420I, 0x0);///0x2, 0x0);
+		//pp_output_fmt_cfg(pp_num, COLOR_YUV420_NV12 - COLOR_YUV420_NV21, 0);
+		break;
+	case COLOR_RGB888_ARGB:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_ARGB888, 0x0);
+		//pp_output_fmt_cfg(pp_num, 0, 0);
+		break;
+	case COLOR_RGB888_ABGR:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_ABGR888, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, 0, 0);
+		break;
+	case COLOR_RGB888_RGBA:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_RGBA888, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, 0, 0);
+		break;
+	case COLOR_RGB888_BGRA:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_BGRA888, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, 0, 0);
+		break;
+	case COLOR_RGB565:
+		pp_output_cfg(sf_crtc, pp_num, outsel, 0x0, PP_DST_RGB565, 0x0);
+		pp_output_fmt_cfg(sf_crtc, pp_num, 0, 0);
+		break;
+	}
+}
+
+static void pp_format_set(struct starfive_crtc *sf_crtc, int pp_num,
+			  struct pp_video_mode *src, struct pp_video_mode *dst)
+{
+	/* 1:bypass, 0:not bypass */
+	unsigned int scale_byp = 1;
+
+	pp_srcfmt_set(sf_crtc, pp_num, src);
+	pp_dstfmt_set(sf_crtc, pp_num, dst);
+
+	if (src->height != dst->height || src->width != dst->width)
+		scale_byp = 0;
+
+	if (src->format >= COLOR_RGB888_ARGB && dst->format <= COLOR_YUV420_NV12) {
+		/* rgb -> yuv-420 */
+		pp_r2yscal_bypass(sf_crtc, pp_num, NOT_BYPASS, scale_byp, BYPASS);
+		pp_r2y_coeff(sf_crtc, pp_num, 1, R2Y_COEF_R1, R2Y_COEF_G1,
+			     R2Y_COEF_B1, R2Y_OFFSET1);
+		pp_r2y_coeff(sf_crtc, pp_num, 2, R2Y_COEF_R2, R2Y_COEF_G2,
+			     R2Y_COEF_B2, R2Y_OFFSET2);
+		pp_r2y_coeff(sf_crtc, pp_num, 3, R2Y_COEF_R3, R2Y_COEF_G3,
+			     R2Y_COEF_B3, R2Y_OFFSET3);
+	} else if (src->format <= COLOR_YUV420_NV12 && dst->format >= COLOR_RGB888_ARGB) {
+		/* yuv-420 -> rgb */
+		pp_r2yscal_bypass(sf_crtc, pp_num, BYPASS, scale_byp, NOT_BYPASS);
+	} else if (src->format <= COLOR_YUV422_YVYU && dst->format <= COLOR_YUV420_NV12) {
+		/* yuv422 -> yuv420 */
+		pp_r2yscal_bypass(sf_crtc, pp_num, BYPASS, scale_byp, BYPASS);
+	} else {
+		/* rgb565->argb888 */
+		pp_r2yscal_bypass(sf_crtc, pp_num, BYPASS, scale_byp, BYPASS);
+	} //else if ((src->format >= COLOR_RGB888_ARGB) && (dst->format >= COLOR_RGB888_ARGB)) {
+		/* rgb -> rgb */
+		// pp_r2yscal_bypass(pp_num, BYPASS, scale_byp, BYPASS);
+	//}
+	pp_argb_alpha(sf_crtc, pp_num, 0xff);
+
+	if (dst->addr)
+		pp_lock_trans_cfg(sf_crtc, pp_num, SYS_BUS_OUTPUT);
+	else
+		pp_lock_trans_cfg(sf_crtc, pp_num, FIFO_OUTPUT);
+
+	pp_int_interval_cfg(sf_crtc, pp_num, 0x1);
+}
+
+static void pp_size_set(struct starfive_crtc *sf_crtc, int pp_num,
+			struct pp_video_mode *src, struct pp_video_mode *dst)
+{
+	u32 src_addr, dstaddr;
+	unsigned int size, y_rgb_ofst, uofst;
+	unsigned int v_uvofst = 0, next_y_rgb_addr = 0, next_u_addr = 0, next_v_addr = 0;
+	unsigned int i = 0;
+
+	pp_src_size_cfg(sf_crtc, pp_num, src->width - 1, src->height - 1);
+	pp_drop_cfg(sf_crtc, pp_num, 0x0, 0x0);///0:no drop
+	pp_des_size_cfg(sf_crtc, pp_num, dst->width - 1, dst->height - 1);
+
+	src_addr = src->addr + (i << 30); //PP_SRC_BASE_ADDR + (i << 30);
+	size = src->width * src->height;
+
+	if (src->format >= COLOR_RGB888_ARGB) {
+		next_y_rgb_addr = src_addr;
+		next_u_addr = 0;
+		next_v_addr = 0;
+
+		y_rgb_ofst = 0;
+		uofst = 0;
+		v_uvofst = 0;
+		//pp_src_addr_next(pp_num, src_addr, 0, 0);
+		//pp_src_offset_cfg(pp_num, 0x0, 0x0, 0x0);
+	} else {
+		if (src->format == COLOR_YUV420_NV21) {    //ok
+			next_y_rgb_addr = src_addr;
+			next_u_addr = src_addr + size + 1;
+			next_v_addr = src_addr + size;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = size;
+		} else if (src->format == COLOR_YUV420_NV12) {
+			next_y_rgb_addr = src_addr;
+			next_u_addr = src_addr + size;
+			next_v_addr = src_addr + size + 1;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = size;
+		} else if (src->format == COLOR_YUV420P) {
+			next_y_rgb_addr = src_addr;
+			next_u_addr = src_addr + size;
+			next_v_addr = src_addr + size * 5 / 4;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else if (src->format == COLOR_YUV422_YVYU) {   //ok
+			next_y_rgb_addr = src_addr;
+			next_u_addr = src_addr + 1;
+			next_v_addr = src_addr + 3;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else if (src->format == COLOR_YUV422_VYUY) {   //ok
+			next_y_rgb_addr = src_addr + 1;
+			next_u_addr = src_addr + 2;
+			next_v_addr = src_addr;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else if (src->format == COLOR_YUV422_YUYV) {   //ok
+			next_y_rgb_addr = src_addr;
+			next_u_addr = src_addr + 1;
+			next_v_addr = src_addr + 2;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else if (src->format == COLOR_YUV422_UYVY) {  //ok
+			next_y_rgb_addr = src_addr + 1;
+			next_u_addr = src_addr;
+			next_v_addr = src_addr + 2;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		}
+	}
+	pp_src_addr_next(sf_crtc, pp_num, next_y_rgb_addr, next_u_addr, next_v_addr);
+	pp_src_offset_cfg(sf_crtc, pp_num, y_rgb_ofst, uofst, v_uvofst);
+	/* source addr not change */
+	pp_nxt_addr_load(sf_crtc, pp_num, 0x1, (i & 0x1));
+
+	if (dst->addr) {
+		dstaddr = dst->addr;
+		size = dst->height * dst->width;
+		if (dst->format >= COLOR_RGB888_ARGB) {
+			next_y_rgb_addr = dstaddr;
+			next_u_addr = 0;
+			next_v_addr = 0;
+			y_rgb_ofst = 0;
+			uofst = 0;
+			v_uvofst = 0;
+		} else {
+			if (dst->format == COLOR_YUV420_NV21) {
+				/* yyyyvuvuvu */
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + size;
+				next_v_addr = 0;//dstaddr + size;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV420_NV12) {
+				/* yyyyuvuvuv */
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + size;
+				next_v_addr = dstaddr + size + 1;
+				y_rgb_ofst = 0;
+				uofst = size;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV420P) {
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + size;
+				next_v_addr = dstaddr + size * 5 / 4;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV422_YVYU) {
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + 1;
+				next_v_addr = dstaddr + 3;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV422_VYUY) {
+				next_y_rgb_addr = dstaddr + 1;
+				next_u_addr = dstaddr + 2;
+				next_v_addr = dstaddr;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV422_YUYV) {
+				next_y_rgb_addr = dstaddr;
+				next_u_addr = dstaddr + 1;
+				next_v_addr = dstaddr + 2;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			} else if (dst->format == COLOR_YUV422_UYVY) {
+				next_y_rgb_addr = dstaddr + 1;
+				next_u_addr = dstaddr;
+				next_v_addr = dstaddr + 2;
+				y_rgb_ofst = 0;
+				uofst = 0;
+				v_uvofst = 0;
+			}
+		}
+		pp_des_addr_cfg(sf_crtc, pp_num, next_y_rgb_addr, next_u_addr, next_v_addr);
+		pp_des_offset_cfg(sf_crtc, pp_num, y_rgb_ofst, uofst, v_uvofst);
+	}
+}
+
+static void pp_config(struct starfive_crtc *sf_crtc, int pp_num,
+		      struct pp_video_mode *src, struct pp_video_mode *dst)
+{
+	//pp_disable_intr(sf_dev, pp_num);
+	pp_format_set(sf_crtc, pp_num, src, dst);
+	pp_size_set(sf_crtc, pp_num, src, dst);
+}
+
+irqreturn_t vpp1_isr_handler(int this_irq, void *dev_id)
+{
+	struct starfive_crtc *sf_crtc = dev_id;
+
+	sf_fb_vppread32(sf_crtc, 1, PP_INT_STATUS);
+	sf_fb_vppwrite32(sf_crtc, 1, PP_INT_CLR, 0xf);
+	sifive_ccache_flush_range(sf_crtc->dma_addr, sf_crtc->size);
+
+	return IRQ_HANDLED;
+}
+
+static void starfive_pp_enable_intr(struct starfive_crtc *sf_crtc, int enable)
+{
+	int pp_id;
+
+	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
+		if (sf_crtc->pp[pp_id].inited == 1) {
+			if (enable)
+				pp_enable_intr(sf_crtc, pp_id);
+			else
+				pp_disable_intr(sf_crtc, pp_id);
+		}
+	}
+}
+
+static int starfive_pp_video_mode_init(struct starfive_crtc *sf_crtc,
+				       struct pp_video_mode *src,
+				       struct pp_video_mode *dst,
+				       int pp_id)
+{
+	if (!src || !dst) {
+		dev_err(sf_crtc->dev, "Invalid argument!\n");
+		return -EINVAL;
+	}
+
+	if (pp_id < PP_NUM && pp_id >= 0) {
+		src->format = sf_crtc->vpp_format;
+		src->width = sf_crtc->crtc.state->adjusted_mode.hdisplay;
+		src->height = sf_crtc->crtc.state->adjusted_mode.vdisplay;
+		src->addr = sf_crtc->dma_addr;
+		//src->addr = 0xa0000000;
+		dst->format = sf_crtc->pp[pp_id].dst.format;
+		dst->width = sf_crtc->crtc.state->adjusted_mode.hdisplay;
+		dst->height = sf_crtc->crtc.state->adjusted_mode.vdisplay;
+		if (sf_crtc->pp[pp_id].bus_out) /*out to ddr*/
+			dst->addr = 0xfc000000;
+		else if (sf_crtc->pp[pp_id].fifo_out) /*out to lcdc*/
+			dst->addr = 0;
+	} else {
+		dev_err(sf_crtc->dev, "pp_id %d is not support\n", pp_id);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int starfive_pp_init(struct starfive_crtc *sf_crtc)
+{
+	int pp_id;
+	int ret = 0;
+	struct pp_video_mode src, dst;
+
+	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
+		if (sf_crtc->pp[pp_id].inited == 1) {
+			ret = starfive_pp_video_mode_init(sf_crtc, &src, &dst, pp_id);
+			if (!ret)
+				pp_config(sf_crtc, pp_id, &src, &dst);
+		}
+	}
+
+	return ret;
+}
+
+static int starfive_pp_run(struct starfive_crtc *sf_crtc)
+{
+	int pp_id;
+	int ret = 0;
+
+	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
+		if (sf_crtc->pp[pp_id].inited == 1)
+			pp_run(sf_crtc, pp_id, PP_RUN);
+	}
+
+	return ret;
+}
+
+int starfive_pp_enable(struct starfive_crtc *sf_crtc)
+{
+	starfive_pp_enable_intr(sf_crtc, PP_INTR_DISABLE);
+
+	if (starfive_pp_init(sf_crtc))
+		return -ENODEV;
+
+	starfive_pp_run(sf_crtc);
+	starfive_pp_enable_intr(sf_crtc, PP_INTR_ENABLE);
+
+	return 0;
+}
+
+int starfive_pp_update(struct starfive_crtc *sf_crtc)
+{
+	int pp_id;
+	int ret = 0;
+	struct pp_video_mode src, dst;
+
+	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
+		if (sf_crtc->pp[pp_id].inited == 1) {
+			ret = starfive_pp_video_mode_init(sf_crtc, &src, &dst, pp_id);
+			if (!ret) {
+				if (sf_crtc->ddr_format_change)
+					pp_format_set(sf_crtc, pp_id, &src, &dst);
+
+				if (sf_crtc->dma_addr_change)
+					pp_size_set(sf_crtc, pp_id, &src, &dst);
+			}
+		}
+	}
+
+	return 0;
+}
+
+int starfive_pp_get_2lcdc_id(struct starfive_crtc *sf_crtc)
+{
+	int pp_id;
+
+	for (pp_id = 0; pp_id < PP_NUM; pp_id++) {
+		if (sf_crtc->pp[pp_id].inited == 1) {
+			if (sf_crtc->pp[pp_id].fifo_out == 1 && !sf_crtc->pp[pp_id].bus_out)
+				return pp_id;
+		}
+	}
+
+	if (pp_id == PP_NUM - 1)
+		dev_warn(sf_crtc->dev, "NO pp connect to LCDC\n");
+
+	return -ENODEV;
+}
+
+void dsitx_vout_init(struct starfive_crtc *sf_crtc)
+{
+	u32 temp;
+
+	reset_control_assert(sf_crtc->rst_vout_src);
+	reset_control_assert(sf_crtc->rst_disp_axi);
+	clk_prepare_enable(sf_crtc->clk_disp_axi);
+	clk_prepare_enable(sf_crtc->clk_vout_src);
+	reset_control_deassert(sf_crtc->rst_vout_src);
+	reset_control_deassert(sf_crtc->rst_disp_axi);
+
+	sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, BIT(31), BIT(31));
+
+	sf_set_clear(sf_crtc->base_rst, vout_rstgen_assert0_REG, ~0x1981ec, 0x1981ec);
+
+	do {
+		temp = ioread32(sf_crtc->base_rst + vout_rstgen_status0_REG);
+		temp &= 0x1981ec;
+	} while (temp != 0x1981ec);
+}
+
+void vout_reset(struct starfive_crtc *sf_crtc)
+{
+	u32 temp;
+
+	iowrite32(0xFFFFFFFF, sf_crtc->base_rst);
+
+	clk_prepare_enable(sf_crtc->clk_disp_axi);
+	clk_prepare_enable(sf_crtc->clk_vout_src);
+	reset_control_deassert(sf_crtc->rst_vout_src);
+	reset_control_deassert(sf_crtc->rst_disp_axi);
+
+	sf_set_clear(sf_crtc->base_clk, clk_disp0_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_disp1_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_oclk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_lcdc_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp0_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp1_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_vpp2_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_mapconv_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_mapconv_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_pixrawout_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_pixrawout_axi_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_csi2tx_strm0_pixclk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_ppi_tx_esc_clk_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_apb_ctrl_REG, BIT(31), BIT(31));
+	sf_set_clear(sf_crtc->base_clk, clk_dsi_sys_clk_ctrl_REG, BIT(31), BIT(31));
+
+	sf_set_clear(sf_crtc->base_rst, vout_rstgen_assert0_REG, ~0x19bfff, 0x19bfff);
+	do {
+		temp = ioread32(sf_crtc->base_rst + vout_rstgen_status0_REG);
+		temp &= 0x19bfff;
+	} while (temp != 0x19bfff);
+}
+
+void vout_disable(struct starfive_crtc *sf_crtc)
+{
+	iowrite32(0xFFFFFFFF, sf_crtc->base_rst);
+
+	clk_disable_unprepare(sf_crtc->clk_disp_axi);
+	clk_disable_unprepare(sf_crtc->clk_vout_src);
+	reset_control_assert(sf_crtc->rst_vout_src);
+	reset_control_assert(sf_crtc->rst_disp_axi);
+}
+
+MODULE_AUTHOR("StarFive Technology Co., Ltd.");
+MODULE_DESCRIPTION("loadable VPP driver for StarFive");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/starfive/starfive_drm_vpp.h b/drivers/gpu/drm/starfive/starfive_drm_vpp.h
new file mode 100644
index 000000000000..12a1928987c3
--- /dev/null
+++ b/drivers/gpu/drm/starfive/starfive_drm_vpp.h
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ */
+#ifndef __SF_FB_VPP_H__
+#define __SF_FB_VPP_H__
+
+#include "starfive_drm_crtc.h"
+
+#define PP_ID_0	0
+#define PP_ID_1	1
+#define PP_ID_2	2
+
+#define PP_NUM	3
+
+#define PP_STOP	0
+#define PP_RUN	1
+
+#define PP_INTR_ENABLE	1
+#define PP_INTR_DISABLE	0
+//PP coefficients
+#define R2Y_COEF_R1	77
+#define R2Y_COEF_G1	150
+#define R2Y_COEF_B1	29
+#define R2Y_OFFSET1	0
+#define R2Y_COEF_R2	(0x400 | 43)
+#define R2Y_COEF_G2	(0x400 | 85)
+#define R2Y_COEF_B2	128
+#define R2Y_OFFSET2	128
+#define R2Y_COEF_R3	128
+#define R2Y_COEF_G3	(0x400 | 107)
+#define R2Y_COEF_B3	(0x400 | 21)
+#define R2Y_OFFSET3	128
+
+//sys registers
+#define SYS_CONF_LCDC		0x00
+#define SYS_CONF_PP		0x04
+#define SYS_MAP_CONV		0x08
+
+//vout clk registers
+#define CLK_LCDC_OCLK_CTRL	0x14
+
+enum PP_LCD_PATH {
+	SYS_BUS_OUTPUT = 0,
+	FIFO_OUTPUT = 1,
+};
+
+enum PP_COLOR_CONVERT_SCALE {
+	NOT_BYPASS = 0,
+	BYPASS,
+};
+
+enum PP_SRC_FORMAT {
+	PP_SRC_YUV420P = 0,
+	PP_SRC_YUV422,
+	PP_SRC_YUV420I,
+	PP_RESERVED,
+	PP_SRC_GRB888,
+	PP_SRC_RGB565,
+};
+
+enum PP_DST_FORMAT {
+	PP_DST_YUV420P = 0,
+	PP_DST_YUV422,
+	PP_DST_YUV420I,
+	PP_DST_RGBA888,
+	PP_DST_ARGB888,
+	PP_DST_RGB565,
+	PP_DST_ABGR888,
+	PP_DST_BGRA888,
+};
+
+struct pp_video_mode {
+	enum COLOR_FORMAT format;
+	unsigned int height;
+	unsigned int width;
+	unsigned int addr;
+};
+
+struct pp_mode {
+	char pp_id;
+	bool bus_out;	/*out to ddr*/
+	bool fifo_out;	/*out to lcdc*/
+	bool inited;
+	struct pp_video_mode src;
+	struct pp_video_mode dst;
+};
+
+//vpp registers
+#define PP_SWITCH		0x0000
+#define PP_CTRL1		0x0004
+#define PP_CTRL2		0x0008
+#define PP_SRC_SIZE		0x000C
+#define PP_DROP_CTRL		0x0010
+#define PP_DES_SIZE		0x0014
+#define PP_Scale_Hratio		0x0018
+#define PP_Scale_Vratio		0x001C
+#define PP_Scale_limit		0x0020
+#define PP_SRC_Y_SA_NXT		0x0024
+#define PP_SRC_U_SA_NXT		0x0028
+#define PP_SRC_V_SA_NXT		0x002c
+#define PP_LOAD_NXT_PAR		0x0030
+#define PP_SRC_Y_SA0		0x0034
+#define PP_SRC_U_SA0		0x0038
+#define PP_SRC_V_SA0		0x003c
+#define PP_SRC_Y_OFS		0x0040
+#define PP_SRC_U_OFS		0x0044
+#define PP_SRC_V_OFS		0x0048
+#define PP_SRC_Y_SA1		0x004C
+#define PP_SRC_U_SA1		0x0050
+#define PP_SRC_V_SA1		0x0054
+#define PP_DES_Y_SA		0x0058
+#define PP_DES_U_SA		0x005C
+#define PP_DES_V_SA		0x0060
+#define PP_DES_Y_OFS		0x0064
+#define PP_DES_U_OFS		0x0068
+#define PP_DES_V_OFS		0x006C
+#define PP_INT_STATUS		0x0070
+#define PP_INT_MASK		0x0074
+#define PP_INT_CLR		0x0078
+#define PP_R2Y_COEF1		0x007C
+#define PP_R2Y_COEF2		0x0080
+
+/* Definition controller bit for LCDC registers */
+//for PP_SWITCH
+#define PP_TRIG			0
+//for PP_CTRL1
+#define PP_LCDPATH_EN		0
+#define PP_INTERLACE		1
+#define PP_POINTER_MODE		2
+#define PP_SRC_FORMAT_N		4
+#define PP_420_ITLC		7
+#define PP_DES_FORMAT		8
+#define PP_R2Y_BPS		12
+#define PP_MSCALE_BPS		13
+#define PP_Y2R_BPS		14
+#define PP_ARGB_ALPHA		16
+#define PP_UV_IN_ADD_128	24
+#define PP_UV_OUT_ADD_128	25
+#define PP_SRC_422_YUV_POS	26
+#define PP_SRC_420_YUV_POS	28
+#define PP_SRC_ARGB_ORDER	29
+//for PP_CTRL2
+#define PP_LOCK_EN		0
+#define PP_INT_INTERVAL		8
+#define PP_DES_422_ORDER	16
+#define PP_DES_420_ORDER	18
+//for PP_SRC_SIZE
+#define PP_SRC_HSIZE		0
+#define PP_SRC_VSIZE		16
+//for PP_DROP_CTRL
+#define PP_DROP_HRATION		0
+#define PP_DROP_VRATION		4
+//for PP_DES_SIZE
+#define PP_DES_HSIZE		0
+#define PP_DES_VSIZE		16
+//for PP_R2Y_COEF1
+#define PP_COEF_R1		0
+#define PP_COEF_G1		16
+//for PP_R2Y_COEF2
+#define PP_COEF_B1		0
+#define PP_OFFSET_1		16
+
+#define vout_rstgen_assert0_REG			0x0
+#define vout_rstgen_status0_REG			0x4
+#define clk_vout_apb_ctrl_REG			0x0
+#define clk_mapconv_apb_ctrl_REG		0x4
+#define clk_mapconv_axi_ctrl_REG		0x8
+#define clk_disp0_axi_ctrl_REG			0xC
+#define clk_disp1_axi_ctrl_REG			0x10
+#define clk_lcdc_oclk_ctrl_REG			0x14
+#define clk_lcdc_axi_ctrl_REG			0x18
+#define clk_vpp0_axi_ctrl_REG			0x1C
+#define clk_vpp1_axi_ctrl_REG			0x20
+#define clk_vpp2_axi_ctrl_REG			0x24
+#define clk_pixrawout_apb_ctrl_REG		0x28
+#define clk_pixrawout_axi_ctrl_REG		0x2C
+#define clk_csi2tx_strm0_pixclk_ctrl_REG	0x30
+#define clk_csi2tx_strm0_apb_ctrl_REG		0x34
+#define clk_dsi_sys_clk_ctrl_REG		0x38
+#define clk_dsi_apb_ctrl_REG			0x3C
+#define clk_ppi_tx_esc_clk_ctrl_REG		0x40
+
+void mapconv_pp0_sel(struct starfive_crtc *sf_crtc, int sel);
+void pp_src_addr_next(struct starfive_crtc *sf_crtc, int pp_num, int ysa, int usa, int vsa);
+void pp_src_offset_cfg(struct starfive_crtc *sf_crtc, int pp_num, int yoff, int uoff, int voff);
+void pp_nxt_addr_load(struct starfive_crtc *sf_crtc, int pp_num, int nxt_par, int nxt_pos);
+void pp_intcfg(struct starfive_crtc *sf_crtc, int pp_num, int int_mask);
+irqreturn_t vpp1_isr_handler(int this_irq, void *dev_id);
+void pp1_enable_intr(struct starfive_crtc *sf_crtc);
+void pp_enable_intr(struct starfive_crtc *sf_crtc, int pp_num);
+void pp_disable_intr(struct starfive_crtc *sf_crtc, int pp_num);
+void pp_run(struct starfive_crtc *sf_crtc, int pp_num, int start);
+int starfive_pp_enable(struct starfive_crtc *sf_crtc);
+int starfive_pp_get_2lcdc_id(struct starfive_crtc *sf_crtc);
+int starfive_pp_update(struct starfive_crtc *sf_crtc);
+void vout_disable(struct starfive_crtc *sf_crtc);
+void vout_reset(struct starfive_crtc *sf_crtc);
+void dsitx_vout_init(struct starfive_crtc *sf_crtc);
+
+#endif
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 0c609fc1334a..d0584562f1e1 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -153,6 +153,12 @@ static void ccache_flush_range(phys_addr_t start, unsigned long len)
 	}
 }
 
+void sifive_ccache_flush_range(phys_addr_t start, size_t len)
+{
+	ccache_flush_range(start, len);
+}
+EXPORT_SYMBOL_GPL(sifive_ccache_flush_range);
+
 static const struct __initdata riscv_cache_ops ccache_mgmt_ops = {
 	.wback = &ccache_flush_range,
 	.inv = &ccache_flush_range,
diff --git a/include/soc/sifive/sifive_ccache.h b/include/soc/sifive/sifive_ccache.h
index 4d4ed49388a0..e34d5060eb99 100644
--- a/include/soc/sifive/sifive_ccache.h
+++ b/include/soc/sifive/sifive_ccache.h
@@ -13,4 +13,6 @@ extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb);
 #define SIFIVE_CCACHE_ERR_TYPE_CE 0
 #define SIFIVE_CCACHE_ERR_TYPE_UE 1
 
+void sifive_ccache_flush_range(phys_addr_t start, size_t len);
+
 #endif /* __SOC_SIFIVE_CCACHE_H */
-- 
2.41.0


From ff0a4632636fb08604d27d815fbc432d05a0281b Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Wed, 22 Sep 2021 16:35:15 +0200
Subject: [PATCH 69/72] [WIP] drm/starfive: Support DRM_FORMAT_XRGB8888

When creating dumb buffers with 32bpp and 24bit colour depth this is
default mode return by drm_mode_legacy_fb_format. So we need to support
this for common dumb buffers to just work.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/gpu/drm/starfive/starfive_drm_crtc.c  | 1 +
 drivers/gpu/drm/starfive/starfive_drm_plane.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/starfive/starfive_drm_crtc.c b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
index 5ba973377059..e31ace35b382 100644
--- a/drivers/gpu/drm/starfive/starfive_drm_crtc.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_crtc.c
@@ -64,6 +64,7 @@ static int ddrfmt_to_ppfmt(struct starfive_crtc *sf_crtc)
 	case DRM_FORMAT_NV12:
 		sf_crtc->vpp_format = COLOR_YUV420_NV12;
 		break;
+	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_ARGB8888:
 		sf_crtc->vpp_format = COLOR_RGB888_ARGB;
 		break;
diff --git a/drivers/gpu/drm/starfive/starfive_drm_plane.c b/drivers/gpu/drm/starfive/starfive_drm_plane.c
index 119a9fe32769..7ee1d3576211 100644
--- a/drivers/gpu/drm/starfive/starfive_drm_plane.c
+++ b/drivers/gpu/drm/starfive/starfive_drm_plane.c
@@ -28,6 +28,7 @@ static const u32 formats[] = {
 	DRM_FORMAT_NV21,
 	DRM_FORMAT_NV12,
 
+	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_ARGB8888,
 	DRM_FORMAT_ABGR8888,
 };
-- 
2.41.0


From 0f96ea3448d745dda40a32a7cbf0ca30615f7f3a Mon Sep 17 00:00:00 2001
From: "sw.multimedia" <sw.multimedia@starfivetech.com>
Date: Tue, 31 Aug 2021 16:48:57 +0800
Subject: [PATCH 70/72] drm/i2c/tda998x: Hardcode register values for Starlight

A proper solution to this hack should be found.

Signed-off-by: jack.zhu <jack.zhu@starfivetech.com>
Signed-off-by: keith.zhao <keith.zhao@starfivetech.com>
---
 drivers/gpu/drm/i2c/tda998x_drv.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c
index d8d7de18dd65..2a612b901572 100644
--- a/drivers/gpu/drm/i2c/tda998x_drv.c
+++ b/drivers/gpu/drm/i2c/tda998x_drv.c
@@ -1606,7 +1606,9 @@ static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
 		reg |= VIP_CNTRL_3_H_TGL;
 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 		reg |= VIP_CNTRL_3_V_TGL;
-	reg_write(priv, REG_VIP_CNTRL_3, reg);
+	//reg_write(priv, REG_VIP_CNTRL_3, reg);
+	reg_write(priv, REG_VIP_CNTRL_3, 0x26);
+	reg_write(priv, REG_VIDFORMAT, 0x06);
 
 	reg_write(priv, REG_VIDFORMAT, 0x00);
 	reg_write16(priv, REG_REFPIX_MSB, ref_pix);
@@ -1644,7 +1646,8 @@ static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
 		reg |= TBG_CNTRL_1_H_TGL;
 	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 		reg |= TBG_CNTRL_1_V_TGL;
-	reg_write(priv, REG_TBG_CNTRL_1, reg);
+	//reg_write(priv, REG_TBG_CNTRL_1, reg);
+	reg_write(priv, REG_TBG_CNTRL_1, 0x46);
 
 	/* must be last register set: */
 	reg_write(priv, REG_TBG_CNTRL_0, 0);
-- 
2.41.0


From 37881fa31d9774180ab62ba2550a691ad4b14e4b Mon Sep 17 00:00:00 2001
From: Farzad Farshchi <farzadfr@gmail.com>
Date: Thu, 20 Sep 2018 19:08:27 -0500
Subject: [PATCH 71/72] nvdla: add NVDLA driver

Additional update from Prashant Gaikwad <pgaikwad@nvidia.com>
Adapted for Linux 5.13 and the BeagleV Starlight board by
<cybergaszcz@gmail.com>

kernel test robot: fix platform_no_drv_owner.cocci warnings
Geert: Use div_u64() in dla_get_time_us()

Signed-off-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20220119060057.GA1143@7f39e361da8f
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Link: https://lore.kernel.org/r/alpine.DEB.2.22.394.2203090905560.780932@ramsan.of.borg
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---
 drivers/Kconfig                         |     2 +
 drivers/Makefile                        |     1 +
 drivers/nvdla/Kconfig                   |     4 +
 drivers/nvdla/Makefile                  |    21 +
 drivers/nvdla/bdma.c                    |   280 +
 drivers/nvdla/cache.c                   |   253 +
 drivers/nvdla/cdp.c                     |   384 +
 drivers/nvdla/common.c                  |   324 +
 drivers/nvdla/common.h                  |    47 +
 drivers/nvdla/conv.c                    |   779 +
 drivers/nvdla/dla_engine_internal.h     |   361 +
 drivers/nvdla/engine.c                  |   266 +
 drivers/nvdla/engine_data.c             |   303 +
 drivers/nvdla/engine_debug.c            |   551 +
 drivers/nvdla/engine_debug.h            |   129 +
 drivers/nvdla/engine_isr.c              |   136 +
 drivers/nvdla/include/dla_debug.h       |    94 +
 drivers/nvdla/include/dla_engine.h      |    94 +
 drivers/nvdla/include/dla_err.h         |    50 +
 drivers/nvdla/include/dla_interface.h   |   886 ++
 drivers/nvdla/include/dla_sched.h       |    74 +
 drivers/nvdla/include/nvdla_interface.h |   327 +
 drivers/nvdla/include/nvdla_ioctl.h     |   138 +
 drivers/nvdla/include/nvdla_linux.h     |   153 +
 drivers/nvdla/include/opendla.h         |    40 +
 drivers/nvdla/include/opendla_initial.h | 16743 ++++++++++++++++++++++
 drivers/nvdla/include/opendla_small.h   |  6433 +++++++++
 drivers/nvdla/nvdla_core_callbacks.c    |   443 +
 drivers/nvdla/nvdla_gem.c               |   475 +
 drivers/nvdla/pdp.c                     |   528 +
 drivers/nvdla/rubik.c                   |   292 +
 drivers/nvdla/scheduler.c               |  1160 ++
 drivers/nvdla/sdp.c                     |   817 ++
 kernel/dma/coherent.c                   |     1 +
 34 files changed, 32589 insertions(+)
 create mode 100644 drivers/nvdla/Kconfig
 create mode 100644 drivers/nvdla/Makefile
 create mode 100644 drivers/nvdla/bdma.c
 create mode 100644 drivers/nvdla/cache.c
 create mode 100644 drivers/nvdla/cdp.c
 create mode 100644 drivers/nvdla/common.c
 create mode 100644 drivers/nvdla/common.h
 create mode 100644 drivers/nvdla/conv.c
 create mode 100644 drivers/nvdla/dla_engine_internal.h
 create mode 100644 drivers/nvdla/engine.c
 create mode 100644 drivers/nvdla/engine_data.c
 create mode 100644 drivers/nvdla/engine_debug.c
 create mode 100644 drivers/nvdla/engine_debug.h
 create mode 100644 drivers/nvdla/engine_isr.c
 create mode 100644 drivers/nvdla/include/dla_debug.h
 create mode 100644 drivers/nvdla/include/dla_engine.h
 create mode 100644 drivers/nvdla/include/dla_err.h
 create mode 100644 drivers/nvdla/include/dla_interface.h
 create mode 100644 drivers/nvdla/include/dla_sched.h
 create mode 100644 drivers/nvdla/include/nvdla_interface.h
 create mode 100644 drivers/nvdla/include/nvdla_ioctl.h
 create mode 100644 drivers/nvdla/include/nvdla_linux.h
 create mode 100644 drivers/nvdla/include/opendla.h
 create mode 100644 drivers/nvdla/include/opendla_initial.h
 create mode 100644 drivers/nvdla/include/opendla_small.h
 create mode 100644 drivers/nvdla/nvdla_core_callbacks.c
 create mode 100644 drivers/nvdla/nvdla_gem.c
 create mode 100644 drivers/nvdla/pdp.c
 create mode 100644 drivers/nvdla/rubik.c
 create mode 100644 drivers/nvdla/scheduler.c
 create mode 100644 drivers/nvdla/sdp.c

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 2ae1b6707c2c..528b74d0dff7 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -245,4 +245,6 @@ source "drivers/hte/Kconfig"
 
 source "drivers/cdx/Kconfig"
 
+source "drivers/nvdla/Kconfig"
+
 endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 23eb201fe18a..8801ab271535 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -196,3 +196,4 @@ obj-$(CONFIG_PECI)		+= peci/
 obj-$(CONFIG_HTE)		+= hte/
 obj-$(CONFIG_DRM_ACCEL)		+= accel/
 obj-$(CONFIG_CDX_BUS)		+= cdx/
+obj-$(CONFIG_NVDLA)		+= nvdla/
diff --git a/drivers/nvdla/Kconfig b/drivers/nvdla/Kconfig
new file mode 100644
index 000000000000..fdbb82bcc702
--- /dev/null
+++ b/drivers/nvdla/Kconfig
@@ -0,0 +1,4 @@
+config NVDLA
+	tristate "The NVIDIA Deep Learning Accelerator"
+	depends on DRM
+	select DRM_GEM_DMA_HELPER
diff --git a/drivers/nvdla/Makefile b/drivers/nvdla/Makefile
new file mode 100644
index 000000000000..4ba437a0af8e
--- /dev/null
+++ b/drivers/nvdla/Makefile
@@ -0,0 +1,21 @@
+
+ccflags-y += -I$(srctree)/$(src)
+ccflags-y += -I$(srctree)/$(src)/include
+
+nvdla-y := scheduler.o \
+	   engine.o \
+	   bdma.o \
+	   conv.o \
+	   sdp.o \
+	   cdp.o \
+	   pdp.o \
+	   rubik.o \
+	   cache.o \
+	   common.o \
+	   engine_data.o \
+	   engine_isr.o \
+	   engine_debug.o \
+	   nvdla_core_callbacks.o \
+	   nvdla_gem.o
+
+obj-$(CONFIG_NVDLA) += nvdla.o
diff --git a/drivers/nvdla/bdma.c b/drivers/nvdla/bdma.c
new file mode 100644
index 000000000000..8822c2c23dd3
--- /dev/null
+++ b/drivers/nvdla/bdma.c
@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+static const uint8_t map_mem[] = {
+	FIELD_ENUM(BDMA_CFG_CMD_0, SRC_RAM_TYPE, MC),
+	FIELD_ENUM(BDMA_CFG_CMD_0, SRC_RAM_TYPE, CVSRAM),
+};
+
+#if STAT_ENABLE
+void
+dla_bdma_stat_data(struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	uint64_t end_time = 0;
+	struct dla_bdma_stat_desc *bdma_stat;
+
+	bdma_stat = &processor->stat_data_desc->bdma_stat;
+
+	end_time = dla_get_time_us();
+
+	if (group->id == (uint32_t)0) {
+		bdma_stat->read_stall = bdma_reg_read(STATUS_GRP0_READ_STALL);
+		bdma_stat->write_stall = bdma_reg_read(STATUS_GRP0_WRITE_STALL);
+	} else {
+		bdma_stat->read_stall = bdma_reg_read(STATUS_GRP1_READ_STALL);
+		bdma_stat->write_stall = bdma_reg_read(STATUS_GRP1_WRITE_STALL);
+	}
+	bdma_stat->runtime = (uint32_t)(end_time - group->start_time);
+}
+
+void
+dla_bdma_dump_stat(struct dla_processor *processor)
+{
+	struct dla_bdma_stat_desc *bdma_stat;
+
+	bdma_stat = &processor->stat_data_desc->bdma_stat;
+
+	dla_debug_bdma_stats(bdma_stat);
+}
+#endif /* STAT_ENABLE */
+
+void
+dla_bdma_set_producer(int32_t group_id, int32_t rdma_group_id)
+{
+	/*
+	 * There is no producer bit for BDMA operation,
+	 * interrupt pointer decides which outstanding request
+	 * to use for this BDMA operation
+	 */
+}
+
+int
+dla_bdma_enable(struct dla_processor_group *group)
+{
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	if (group->surface_desc->bdma_surface.num_transfers == (uint16_t)0) {
+		group->events |= ((uint8_t)1 << DLA_EVENT_OP_COMPLETED);
+		goto exit;
+	}
+
+	if (engine->stat_enable == (uint32_t)1) {
+		bdma_reg_write(CFG_STATUS, FIELD_ENUM(BDMA_CFG_STATUS_0,
+							STALL_COUNT_EN, YES));
+		group->start_time = dla_get_time_us();
+	}
+
+	/*
+	 * Launch BDMA transfer
+	 */
+	if (group->id == 0)
+		bdma_reg_write(CFG_LAUNCH0, FIELD_ENUM(BDMA_CFG_LAUNCH0_0,
+							GRP0_LAUNCH, YES));
+	else
+		bdma_reg_write(CFG_LAUNCH1, FIELD_ENUM(BDMA_CFG_LAUNCH1_0,
+							GRP1_LAUNCH, YES));
+
+exit:
+	dla_debug("Exit: %s\n", __func__);
+	return 0;
+}
+
+void
+dla_bdma_rdma_check(struct dla_processor_group *group)
+{
+	group->is_rdma_needed = 0;
+}
+
+/*
+ * Program BDMA slot for transfer
+ */
+static int32_t
+processor_bdma_program_slot(struct dla_bdma_surface_desc *bdma_surface,
+				struct dla_bdma_transfer_desc *transfer)
+{
+	int32_t ret = 0;
+	uint64_t source_addr = 0;
+	uint64_t destination_addr = 0;
+	uint32_t high, low, reg;
+	uint8_t  bdma_free_slots = 0;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	/* make sure there're enough free slots */
+	if (bdma_free_slots <= 0) {
+		do {
+			reg = bdma_reg_read(STATUS);
+			reg = (reg & MASK(BDMA_STATUS_0, FREE_SLOT)) >>
+					SHIFT(BDMA_STATUS_0, FREE_SLOT);
+		} while (reg == 0);
+		bdma_free_slots = (uint8_t)reg;
+	}
+
+	dla_get_dma_address(engine->driver_context, engine->task->task_data,
+						transfer->source_address,
+						(void *)&source_addr,
+						DESTINATION_DMA);
+	dla_get_dma_address(engine->driver_context, engine->task->task_data,
+						transfer->destination_address,
+						(void *)&destination_addr,
+						DESTINATION_DMA);
+
+	ASSERT_GOTO((transfer->line_repeat <= 8192),
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO((transfer->surface_repeat <= 8192),
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO((transfer->line_size % 32) == 0,
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO(transfer->source_line >= transfer->line_size,
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO(transfer->destination_line >= transfer->line_size,
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO(transfer->source_surface >=
+			(transfer->source_line * transfer->line_repeat),
+				ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO(transfer->destination_surface >=
+			(transfer->destination_line * transfer->line_repeat),
+				ret, ERR(INVALID_INPUT), exit);
+
+	/* config registers */
+	high = HIGH32BITS(source_addr);
+	low = LOW32BITS(source_addr);
+	bdma_reg_write(CFG_SRC_ADDR_LOW, low);
+	bdma_reg_write(CFG_SRC_ADDR_HIGH, high);
+	high = HIGH32BITS(destination_addr);
+	low = LOW32BITS(destination_addr);
+	bdma_reg_write(CFG_DST_ADDR_LOW, low);
+	bdma_reg_write(CFG_DST_ADDR_HIGH, high);
+	bdma_reg_write(CFG_LINE, (transfer->line_size >> 5) - 1);
+	reg = (map_mem[bdma_surface->source_type] <<
+				SHIFT(BDMA_CFG_CMD_0, SRC_RAM_TYPE)) |
+		(map_mem[bdma_surface->destination_type] <<
+				SHIFT(BDMA_CFG_CMD_0, DST_RAM_TYPE));
+	bdma_reg_write(CFG_CMD, reg);
+	bdma_reg_write(CFG_LINE_REPEAT, transfer->line_repeat - 1);
+	bdma_reg_write(CFG_SRC_LINE, transfer->source_line);
+	bdma_reg_write(CFG_DST_LINE, transfer->destination_line);
+	bdma_reg_write(CFG_SURF_REPEAT, transfer->surface_repeat - 1);
+	bdma_reg_write(CFG_SRC_SURF, transfer->source_surface);
+	bdma_reg_write(CFG_DST_SURF, transfer->destination_surface);
+	bdma_reg_write(CFG_OP, FIELD_ENUM(BDMA_CFG_OP_0, EN, ENABLE));
+
+	dla_debug("Exit: %s\n", __func__);
+
+exit:
+	RETURN(ret);
+}
+
+int
+dla_bdma_is_ready(struct dla_processor *processor,
+			    struct dla_processor_group *group)
+{
+	struct dla_processor_group *next_group;
+
+	next_group = &processor->groups[!group->id];
+
+	/*
+	 * If another group is already programmed but not active then
+	 * do not program this operation as BDMA does not really
+	 * have shadow copies for groups. It will end programming
+	 * same group. Wait for another group to get enabled.
+	 */
+	if ((processor->group_status & (1 << next_group->id)) &&
+						!next_group->active)
+		return 0;
+
+	return 1;
+}
+
+void
+dla_bdma_dump_config(struct dla_processor_group *group)
+{
+	struct dla_bdma_op_desc *bdma_op;
+	struct dla_bdma_surface_desc *bdma_surface;
+
+	bdma_surface = &group->surface_desc->bdma_surface;
+	bdma_op = &group->operation_desc->bdma_op;
+
+	dla_debug_bdma_surface_desc(bdma_surface, group->roi_index);
+	dla_debug_bdma_op_desc(bdma_op, group->roi_index);
+}
+
+int
+dla_bdma_program(struct dla_processor_group *group)
+{
+	int32_t i;
+	int32_t ret = 0;
+	struct dla_bdma_surface_desc *bdma_surface;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	if (!engine->config_data->bdma_enable) {
+		dla_error("BDMA is not supported for this configuration\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	bdma_surface = &group->surface_desc->bdma_surface;
+
+	dla_debug("Num of transfers %u\n", bdma_surface->num_transfers);
+	if (bdma_surface->num_transfers == (uint16_t)0)
+		goto exit;
+
+	if (bdma_surface->num_transfers > NUM_MAX_BDMA_OPS) {
+		dla_error("Invalid number of transfers\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	for (i = 0; i < bdma_surface->num_transfers; i++) {
+		ret = processor_bdma_program_slot(bdma_surface,
+					&bdma_surface->transfers[i]);
+		if (ret)
+			goto exit;
+	}
+
+	dla_enable_intr(MASK(GLB_S_INTR_MASK_0, BDMA_DONE_MASK1) |
+			MASK(GLB_S_INTR_MASK_0, BDMA_DONE_MASK0));
+
+exit:
+	dla_debug("Exit: %s\n", __func__);
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/cache.c b/drivers/nvdla/cache.c
new file mode 100644
index 000000000000..c9ba1431dde4
--- /dev/null
+++ b/drivers/nvdla/cache.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_engine.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+
+#define DLA_OP_CACHE_SIZE (DLA_NUM_GROUPS * ((DLA_OP_NUM + 2) * 2))
+
+static struct dla_common_op_desc desc_cache[DLA_OP_NUM][DLA_OP_CACHE_SIZE];
+static int32_t desc_refcount[DLA_OP_NUM][DLA_OP_CACHE_SIZE];
+
+void
+dla_get_refcount(struct dla_common_op_desc *op_desc)
+{
+	int32_t i;
+	struct dla_common_op_desc *desc = NULL;
+
+	if (op_desc == NULL)
+		return;
+
+	if (op_desc->index == -1)
+		return;
+
+	desc = &desc_cache[op_desc->op_type][0];
+
+	for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
+		if (desc->index == op_desc->index &&
+				desc->roi_index == op_desc->roi_index) {
+			desc_refcount[op_desc->op_type][i]++;
+			return;
+		}
+	}
+}
+
+struct dla_common_op_desc *
+dla_get_op_desc(struct dla_task *task, int16_t index,
+			uint8_t op_type, uint8_t roi_index)
+{
+	int32_t i;
+	int32_t ret;
+	uint64_t op_base;
+	uint64_t dep_graph_addr;
+	struct dla_common_op_desc *desc = NULL;
+	struct dla_engine *engine = dla_get_engine();
+
+	if (index == -1) {
+		dla_debug("no desc get due to index==-1\n");
+		goto exit;
+	}
+
+	dep_graph_addr = (sizeof(struct dla_common_op_desc) *
+				engine->network->num_operations * roi_index);
+
+	desc = &desc_cache[op_type][0];
+
+	for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
+		if (desc->index == index && desc->roi_index == roi_index) {
+			if (desc->op_type != op_type) {
+				dla_error("op_cache[op=%u] contains incorrect "
+						"entry of op[%u]\n", op_type,
+						desc->op_type);
+				continue;
+			}
+			desc_refcount[op_type][i]++;
+			goto exit;
+		}
+	}
+
+	desc = &desc_cache[op_type][0];
+
+	for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
+		if (desc->index == -1) {
+			op_base = dep_graph_addr +
+					(sizeof(struct dla_common_op_desc) *
+					(uint64_t)index);
+			ret = dla_data_read(engine->driver_context,
+					task->task_data,
+					task->dependency_graph_addr,
+					(void *)(desc),
+					sizeof(struct dla_common_op_desc),
+					op_base);
+			if (ret) {
+				desc = NULL;
+				goto exit;
+			}
+
+			if (op_type != desc->op_type) {
+				/*
+				 * op_type of entry read from DRAM should not
+				 * mismatch with given op_type. If they
+				 * mismatches, then wrong entry is fetched, so
+				 * report this issue by throwing error.
+				 */
+				dla_error("Fetched [op_type=%u] from DRAM doesn't "
+					"match with op_type[%u]\n",
+					desc->op_type,
+					op_type);
+				desc->op_type = op_type;
+				desc->index = -1;
+				desc->roi_index = -1;
+				desc = NULL;
+				goto exit;
+			}
+
+			desc->index = index;
+			desc->roi_index = roi_index;
+
+			/**
+			 * Refcount must be 0 if we are reading it first time
+			 * from DRAM
+			 */
+			assert(desc_refcount[op_type][i] == 0);
+
+			desc_refcount[op_type][i]++;
+			goto exit;
+		}
+	}
+
+exit:
+	return desc;
+}
+
+static void
+dla_free_op_desc(struct dla_common_op_desc *op_desc)
+{
+	uint64_t op_base;
+	uint64_t dep_graph_addr;
+	struct dla_task *task;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s op desc index %u ROI %d\n", __func__,
+				op_desc->index, op_desc->roi_index);
+
+	task = engine->task;
+	dep_graph_addr = (sizeof(struct dla_common_op_desc) *
+				engine->network->num_operations *
+				op_desc->roi_index);
+
+	if (op_desc->index == -1)
+		goto exit;
+
+	if (op_desc == NULL)
+		goto exit;
+
+	/**
+	 * TODO: keeping the depth value hardcoded as 0 for now,
+	 * need to replace it once corresponding implementation is done.
+	 */
+	op_base = (dep_graph_addr +
+			(sizeof(struct dla_common_op_desc) *
+			(uint64_t)op_desc->index));
+
+	/**
+	 * Flush descriptor to DRAM
+	 */
+	dla_data_write(engine->driver_context,
+			task->task_data,
+			(void *)op_desc,
+			task->dependency_graph_addr,
+			sizeof(struct dla_common_op_desc),
+			op_base);
+
+	/**
+	 * Release it
+	 */
+	op_desc->index = -1;
+	op_desc->roi_index = -1;
+exit:
+	dla_debug("Exit: %s\n", __func__);
+}
+
+void
+dla_put_op_desc(struct dla_common_op_desc *op_desc)
+{
+	int32_t i;
+	struct dla_common_op_desc *desc;
+
+	if (op_desc == NULL)
+		return;
+
+	if (op_desc->index == -1)
+		return;
+
+	desc = &desc_cache[op_desc->op_type][0];
+
+	for (i = 0; i < DLA_OP_CACHE_SIZE; i++, desc++) {
+		if (desc->index == op_desc->index &&
+				desc->roi_index == op_desc->roi_index) {
+			/**
+			 * Refcount can't be 0 when we are trying to free it
+			 */
+			assert(desc_refcount[op_desc->op_type][i] > 0);
+
+			desc_refcount[op_desc->op_type][i]--;
+
+			/**
+			 * Free desc if refcount is 0
+			 */
+			if (desc_refcount[op_desc->op_type][i] == 0)
+				dla_free_op_desc(op_desc);
+
+			return;
+		}
+	}
+}
+
+void
+dla_init_op_cache(struct dla_engine *engine)
+{
+	int32_t i, j;
+	struct dla_common_op_desc *desc = &desc_cache[0][0];
+
+	dla_memset((uint8_t *)&desc_cache[0][0], 0, sizeof(desc_cache));
+	dla_memset((uint8_t *)&desc_refcount[0][0], 0, sizeof(desc_refcount));
+
+	for (i = 0; i < DLA_OP_NUM; i++) {
+		for (j = 0; j < DLA_OP_CACHE_SIZE; j++) {
+			desc->index = -1;
+			desc->roi_index = -1;
+			desc->op_type = (uint8_t)i;
+			desc++;
+		}
+	}
+}
diff --git a/drivers/nvdla/cdp.c b/drivers/nvdla/cdp.c
new file mode 100644
index 000000000000..e83967698127
--- /dev/null
+++ b/drivers/nvdla/cdp.c
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "common.h"
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+static const uint8_t map_ram[] = {
+	FIELD_ENUM(CDP_RDMA_D_SRC_DMA_CFG_0, SRC_RAM_TYPE, MC),
+	FIELD_ENUM(CDP_RDMA_D_SRC_DMA_CFG_0, SRC_RAM_TYPE, CV),
+};
+
+static const uint8_t map_precision[] = {
+	FIELD_ENUM(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA, INT8),
+	FIELD_ENUM(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA, INT16),
+	FIELD_ENUM(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA, FP16),
+};
+
+static const uint8_t map_perf_dma[] = {
+	FIELD_ENUM(CDP_D_PERF_ENABLE_0, DMA_EN, DISABLE),
+	FIELD_ENUM(CDP_D_PERF_ENABLE_0, DMA_EN, ENABLE),
+};
+
+static const uint8_t map_perf_lut[] = {
+	FIELD_ENUM(CDP_D_PERF_ENABLE_0, LUT_EN, DISABLE),
+	FIELD_ENUM(CDP_D_PERF_ENABLE_0, LUT_EN, ENABLE),
+};
+
+#if STAT_ENABLE
+void
+dla_cdp_stat_data(struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	uint64_t end_time = 0;
+	struct dla_cdp_stat_desc *cdp_stat;
+
+	cdp_stat = &processor->stat_data_desc->cdp_stat;
+
+	end_time = dla_get_time_us();
+
+	cdp_stat->write_stall = cdp_reg_read(D_PERF_WRITE_STALL);
+	cdp_stat->lut_uflow = cdp_reg_read(D_PERF_LUT_UFLOW);
+	cdp_stat->lut_oflow = cdp_reg_read(D_PERF_LUT_OFLOW);
+	cdp_stat->lut_hybrid = cdp_reg_read(D_PERF_LUT_HYBRID);
+	cdp_stat->lut_le_hit = cdp_reg_read(D_PERF_LUT_LE_HIT);
+	cdp_stat->lut_lo_hit = cdp_reg_read(D_PERF_LUT_LO_HIT);
+	cdp_stat->runtime = (uint32_t)(end_time - group->start_time);
+}
+
+void
+dla_cdp_dump_stat(struct dla_processor *processor)
+{
+	struct dla_cdp_stat_desc *cdp_stat;
+
+	cdp_stat = &processor->stat_data_desc->cdp_stat;
+
+	dla_debug_cdp_stats(cdp_stat);
+}
+#endif /* STAT_ENABLE */
+
+static uint32_t
+map_local_size(uint8_t local_size)
+{
+	return ((local_size-1)/2)-1;
+}
+
+void
+dla_cdp_set_producer(int32_t group_id, int32_t rdma_group_id)
+{
+	uint32_t reg;
+
+	/**
+	 * set producer pointer for all sub-modules
+	 */
+	reg = group_id << SHIFT(CDP_S_POINTER_0, PRODUCER);
+	cdp_reg_write(S_POINTER, reg);
+	reg = group_id << SHIFT(CDP_RDMA_S_POINTER_0, PRODUCER);
+	cdp_rdma_reg_write(S_POINTER, reg);
+}
+
+int
+dla_cdp_enable(struct dla_processor_group *group)
+{
+	uint32_t reg;
+	uint8_t perf_reg;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	if (engine->stat_enable == (uint32_t)1) {
+		perf_reg = (map_perf_dma[1] <<
+				SHIFT(CDP_D_PERF_ENABLE_0, DMA_EN)) |
+			(map_perf_lut[1] <<
+				SHIFT(CDP_D_PERF_ENABLE_0, LUT_EN));
+
+		cdp_reg_write(D_PERF_ENABLE, perf_reg);
+		group->start_time = dla_get_time_us();
+	}
+
+	/**
+	 * enable all sub-modules
+	 */
+	reg = FIELD_ENUM(CDP_RDMA_D_OP_ENABLE_0, OP_EN, ENABLE);
+	cdp_rdma_reg_write(D_OP_ENABLE, reg);
+	reg = FIELD_ENUM(CDP_D_OP_ENABLE_0, OP_EN, ENABLE);
+	cdp_reg_write(D_OP_ENABLE, reg);
+
+	dla_debug("Exit: %s\n", __func__);
+
+	RETURN(0);
+}
+
+void
+dla_cdp_rdma_check(struct dla_processor_group *group)
+{
+	group->is_rdma_needed = 1;
+}
+
+static int32_t
+processor_cdp_program(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	uint32_t reg, high, low;
+	uint64_t input_address = 0;
+	uint64_t output_address = 0;
+	struct dla_lut_param lut;
+	struct dla_engine *engine = dla_get_engine();
+	struct dla_cdp_op_desc *cdp_op;
+	struct dla_cdp_surface_desc *cdp_surface;
+
+	dla_debug("Enter: %s\n", __func__);
+
+	cdp_op = &group->operation_desc->cdp_op;
+	cdp_surface = &group->surface_desc->cdp_surface;
+
+	/* Argument check */
+	if (cdp_surface->src_data.type == DLA_MEM_HW) {
+		dla_error("Invalid source memory type\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+	if (cdp_surface->dst_data.type == DLA_MEM_HW) {
+		dla_error("Invalid destination memory type\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (cdp_op->in_precision != cdp_op->out_precision) {
+		dla_error("CDP does not support precision conversion\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	/* get the addresses from task descriptor */
+	ret = dla_read_input_address(&cdp_surface->src_data,
+						&input_address,
+						group->op_desc->index,
+						group->roi_index,
+						1);
+	if (ret)
+		goto exit;
+
+	dla_get_dma_cube_address(engine->driver_context,
+				engine->task->task_data,
+				cdp_surface->dst_data.address,
+				cdp_surface->dst_data.offset,
+				(void *)&output_address,
+				DESTINATION_DMA);
+	if (cdp_op->lut_index >= 0) {
+		group->lut_index = cdp_op->lut_index;
+		dla_read_lut(engine, cdp_op->lut_index, (void *)&lut);
+		dla_debug_lut_params(&lut);
+	}
+
+	/* config CDP RDMA registers */
+	reg = ((cdp_surface->src_data.width - 1)
+		<< SHIFT(CDP_RDMA_D_DATA_CUBE_WIDTH_0, WIDTH));
+	cdp_rdma_reg_write(D_DATA_CUBE_WIDTH, reg);
+
+	reg = ((cdp_surface->src_data.height - 1)
+		<< SHIFT(CDP_RDMA_D_DATA_CUBE_HEIGHT_0, HEIGHT));
+	cdp_rdma_reg_write(D_DATA_CUBE_HEIGHT, reg);
+
+	reg = ((cdp_surface->src_data.channel - 1)
+		<< SHIFT(CDP_RDMA_D_DATA_CUBE_CHANNEL_0, CHANNEL));
+	cdp_rdma_reg_write(D_DATA_CUBE_CHANNEL, reg);
+
+	high = HIGH32BITS(input_address);
+	low = LOW32BITS(input_address);
+	cdp_rdma_reg_write(D_SRC_BASE_ADDR_LOW, low);
+	cdp_rdma_reg_write(D_SRC_BASE_ADDR_HIGH, high);
+
+	cdp_rdma_reg_write(D_SRC_LINE_STRIDE,
+			cdp_surface->src_data.line_stride);
+	cdp_rdma_reg_write(D_SRC_SURFACE_STRIDE,
+			cdp_surface->src_data.surf_stride);
+
+	reg = (map_ram[cdp_surface->src_data.type]
+		<< SHIFT(CDP_RDMA_D_SRC_DMA_CFG_0, SRC_RAM_TYPE));
+	cdp_rdma_reg_write(D_SRC_DMA_CFG, reg);
+
+	reg = (map_precision[cdp_op->in_precision]
+		<< SHIFT(CDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA));
+	cdp_rdma_reg_write(D_DATA_FORMAT, reg);
+
+	/* config CDP */
+	if (cdp_op->lut_index >= 0)
+		update_lut(CDP_S_LUT_ACCESS_CFG_0, &lut, cdp_op->in_precision);
+
+	high = HIGH32BITS(output_address);
+	low = LOW32BITS(output_address);
+	cdp_reg_write(D_DST_BASE_ADDR_LOW, low);
+	cdp_reg_write(D_DST_BASE_ADDR_HIGH, high);
+
+	cdp_reg_write(D_DST_LINE_STRIDE, cdp_surface->dst_data.line_stride);
+	cdp_reg_write(D_DST_SURFACE_STRIDE, cdp_surface->dst_data.surf_stride);
+
+	reg = (map_ram[cdp_surface->dst_data.type]
+		<< SHIFT(CDP_D_DST_DMA_CFG_0, DST_RAM_TYPE));
+	cdp_reg_write(D_DST_DMA_CFG, reg);
+
+	reg = (map_precision[cdp_op->in_precision]
+		<< SHIFT(CDP_D_DATA_FORMAT_0, INPUT_DATA_TYPE));
+	cdp_reg_write(D_DATA_FORMAT, reg);
+
+	reg = (map_local_size(cdp_op->local_size)
+		<< SHIFT(CDP_D_LRN_CFG_0, NORMALZ_LEN));
+	cdp_reg_write(D_LRN_CFG, reg);
+
+	reg = (cdp_op->in_cvt.offset
+		<< SHIFT(CDP_D_DATIN_OFFSET_0, DATIN_OFFSET));
+	cdp_reg_write(D_DATIN_OFFSET, reg);
+
+	reg = (cdp_op->in_cvt.scale
+		<< SHIFT(CDP_D_DATIN_SCALE_0, DATIN_SCALE));
+	cdp_reg_write(D_DATIN_SCALE, reg);
+
+	reg = (cdp_op->in_cvt.truncate
+		<< SHIFT(CDP_D_DATIN_SHIFTER_0, DATIN_SHIFTER));
+	cdp_reg_write(D_DATIN_SHIFTER, reg);
+
+	reg = (cdp_op->out_cvt.offset
+		<< SHIFT(CDP_D_DATOUT_OFFSET_0, DATOUT_OFFSET));
+	cdp_reg_write(D_DATOUT_OFFSET, reg);
+
+	reg = (cdp_op->out_cvt.scale
+		<< SHIFT(CDP_D_DATOUT_SCALE_0, DATOUT_SCALE));
+	cdp_reg_write(D_DATOUT_SCALE, reg);
+
+	reg = (cdp_op->out_cvt.truncate
+		<< SHIFT(CDP_D_DATOUT_SHIFTER_0, DATOUT_SHIFTER));
+	cdp_reg_write(D_DATOUT_SHIFTER, reg);
+
+	reg = ((cdp_op->bypass_sqsum ?
+		FIELD_ENUM(CDP_D_FUNC_BYPASS_0, SQSUM_BYPASS, ENABLE) :
+		FIELD_ENUM(CDP_D_FUNC_BYPASS_0, SQSUM_BYPASS, DISABLE)) <<
+		SHIFT(CDP_D_FUNC_BYPASS_0, SQSUM_BYPASS)) |
+		((cdp_op->bypass_out_mul ?
+		FIELD_ENUM(CDP_D_FUNC_BYPASS_0, MUL_BYPASS, ENABLE) :
+		FIELD_ENUM(CDP_D_FUNC_BYPASS_0, MUL_BYPASS, DISABLE)) <<
+		SHIFT(CDP_D_FUNC_BYPASS_0, MUL_BYPASS));
+	cdp_reg_write(D_FUNC_BYPASS, reg);
+
+exit:
+	dla_debug("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+int
+dla_cdp_is_ready(struct dla_processor *processor,
+		 struct dla_processor_group *group)
+{
+	struct dla_processor_group *next_group;
+	struct dla_cdp_op_desc *cdp_op;
+
+	cdp_op = &group->operation_desc->cdp_op;
+	next_group = &processor->groups[!group->id];
+
+	/**
+	 * Single LUT is shared between two CDP groups, need to make
+	 * sure that usage does not conflict. Also, LUT write
+	 * access is locked when CDP sub-engine is active, so delay
+	 * writing LUT when another group is active.
+	 */
+
+	/**
+	 * if no LUT required for current group then it can be programmed
+	 * without further checks
+	 */
+	if (cdp_op->lut_index == -1)
+		return 1;
+
+	/**
+	 * if same LUT is used for both groups then it can be programmed
+	 * without more checks. Even if another group is active and LUT
+	 * is locked, it would have been programmed by another group.
+	 */
+	if (next_group->lut_index == cdp_op->lut_index)
+		return 1;
+
+	/**
+	 * if LUT index of another group is not -1 means some LUT is programmed,
+	 * then do not program current LUT as we already know current LUT is not
+	 * -1 and neither same as another group.
+	 */
+	if (next_group->lut_index != -1)
+		return 0;
+
+	/**
+	 * if current group needs LUT different than another group and that
+	 * group is not active then program it.
+	 */
+	if (!next_group->active)
+		return 1;
+
+	/**
+	 * if control is here it means current group is using LUT different than
+	 * another group and that group is active. Wait for another group to
+	 * become idle.
+	 */
+
+	return 0;
+}
+
+void
+dla_cdp_dump_config(struct dla_processor_group *group)
+{
+	struct dla_cdp_op_desc *cdp_op;
+	struct dla_cdp_surface_desc *cdp_surface;
+
+	cdp_surface = &group->surface_desc->cdp_surface;
+	cdp_op = &group->operation_desc->cdp_op;
+
+	dla_debug_cdp_surface_desc(cdp_surface, group->roi_index);
+	dla_debug_cdp_op_desc(cdp_op, group->roi_index);
+}
+
+int
+dla_cdp_program(struct dla_processor_group *group)
+{
+	int32_t ret;
+
+	dla_debug("Enter: %s", __func__);
+	dla_enable_intr(MASK(GLB_S_INTR_MASK_0, CDP_DONE_MASK1) |
+			MASK(GLB_S_INTR_MASK_0, CDP_DONE_MASK0));
+
+	ret = processor_cdp_program(group);
+	if (ret)
+		goto exit;
+
+exit:
+	dla_debug("Exit: %s", __func__);
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/common.c b/drivers/nvdla/common.c
new file mode 100644
index 000000000000..c36c6ff3cc78
--- /dev/null
+++ b/drivers/nvdla/common.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "common.h"
+#include "dla_engine_internal.h"
+
+static const uint8_t map_lut_method[] = {
+	FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_LE_FUNCTION, EXPONENT),
+	FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_LE_FUNCTION, LINEAR)
+};
+static const uint8_t map_lut_out[] = {
+	FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_UFLOW_PRIORITY, LE),
+	FIELD_ENUM(CDP_S_LUT_CFG_0, LUT_UFLOW_PRIORITY, LO)
+};
+
+static const uint16_t access_data_offset[] = {
+	CDP_S_LUT_ACCESS_DATA_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_ACCESS_DATA_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lut_cfg_offset[] = {
+	CDP_S_LUT_CFG_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_CFG_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lut_info_offset[] = {
+	CDP_S_LUT_INFO_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_INFO_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t le_start_offset[] = {
+	CDP_S_LUT_LE_START_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LE_START_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t le_end_offset[] = {
+	CDP_S_LUT_LE_END_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LE_END_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lo_start_offset[] = {
+	CDP_S_LUT_LO_START_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LO_START_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lo_end_offset[] = {
+	CDP_S_LUT_LO_END_LOW_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LO_END_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t le_slope_scale_offset[] = {
+	CDP_S_LUT_LE_SLOPE_SCALE_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LE_SLOPE_SCALE_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t le_slope_shift_offset[] = {
+	CDP_S_LUT_LE_SLOPE_SHIFT_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LE_SLOPE_SHIFT_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lo_slope_scale_offset[] = {
+	CDP_S_LUT_LO_SLOPE_SCALE_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LO_SLOPE_SCALE_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+static const uint16_t lo_slope_shift_offset[] = {
+	CDP_S_LUT_LO_SLOPE_SHIFT_0 - CDP_S_LUT_ACCESS_CFG_0,
+	SDP_S_LUT_LO_SLOPE_SHIFT_0 - SDP_S_LUT_ACCESS_CFG_0,
+};
+
+void update_lut(uint32_t reg_base, struct dla_lut_param *lut,
+							uint8_t precision)
+{
+	int32_t i;
+	uint32_t reg;
+	uint32_t high, low;
+	int32_t is_sdp = reg_base == SDP_S_LUT_ACCESS_CFG_0;
+	struct dla_engine *engine = dla_get_engine();
+
+	/* program raw table */
+	reg = (FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID, LE)
+		<< SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID)) |
+		(FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE, WRITE)
+		<< SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE));
+	reg_write(reg_base, reg);
+
+	for (i = 0; i < (1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1; i++) {
+		dla_reg_write(engine->driver_context,
+				reg_base + access_data_offset[is_sdp],
+				lut->linear_exp_table[i]);
+	}
+
+	/* program density table */
+	reg = (FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID, LO)
+		<< SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_TABLE_ID)) |
+		(FIELD_ENUM(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE, WRITE)
+		<< SHIFT(CDP_S_LUT_ACCESS_CFG_0, LUT_ACCESS_TYPE));
+	dla_reg_write(engine->driver_context, reg_base, reg);
+
+	for (i = 0; i < (1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1; i++) {
+		dla_reg_write(engine->driver_context,
+				reg_base + access_data_offset[is_sdp],
+				lut->linear_only_table[i]);
+	}
+
+	/* program other configurations */
+	reg = (map_lut_method[lut->method] <<
+		SHIFT(CDP_S_LUT_CFG_0, LUT_LE_FUNCTION)) |
+		(map_lut_out[lut->hybrid_priority] <<
+		SHIFT(CDP_S_LUT_CFG_0, LUT_HYBRID_PRIORITY)) |
+		(map_lut_out[lut->underflow_priority] <<
+		SHIFT(CDP_S_LUT_CFG_0, LUT_UFLOW_PRIORITY)) |
+		(map_lut_out[lut->overflow_priority] <<
+		SHIFT(CDP_S_LUT_CFG_0, LUT_OFLOW_PRIORITY));
+	dla_reg_write(engine->driver_context,
+			reg_base + lut_cfg_offset[is_sdp], reg);
+
+	if (lut->method == FIELD_ENUM(CDP_S_LUT_CFG_0,
+					LUT_LE_FUNCTION, EXPONENT)) {
+		reg = ((((uint32_t)lut->linear_exp_offset.exp_offset) <<
+			SHIFT(CDP_S_LUT_INFO_0, LUT_LE_INDEX_OFFSET))&
+		MASK(CDP_S_LUT_INFO_0, LUT_LE_INDEX_OFFSET)) |
+			((((uint32_t)lut->linear_only_offset.frac_bits) <<
+			SHIFT(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT))&
+		MASK(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT));
+	} else {
+		reg = ((((uint32_t)lut->linear_exp_offset.frac_bits) <<
+			SHIFT(CDP_S_LUT_INFO_0, LUT_LE_INDEX_SELECT))&
+		MASK(CDP_S_LUT_INFO_0, LUT_LE_INDEX_SELECT)) |
+			((((uint32_t)lut->linear_only_offset.frac_bits) <<
+			SHIFT(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT))&
+		MASK(CDP_S_LUT_INFO_0, LUT_LO_INDEX_SELECT));
+	}
+	dla_reg_write(engine->driver_context,
+			reg_base + lut_info_offset[is_sdp], reg);
+	high = HIGH32BITS(lut->linear_exp_start);
+	low = LOW32BITS(lut->linear_exp_start);
+	dla_reg_write(engine->driver_context,
+			reg_base + le_start_offset[is_sdp], low);
+	if (!is_sdp)
+		dla_reg_write(engine->driver_context,
+				reg_base + le_start_offset[is_sdp] + 4, high);
+
+	high = HIGH32BITS(lut->linear_exp_end);
+	low = LOW32BITS(lut->linear_exp_end);
+	dla_reg_write(engine->driver_context,
+				reg_base + le_end_offset[is_sdp], low);
+	if (!is_sdp)
+		dla_reg_write(engine->driver_context,
+				reg_base + le_end_offset[is_sdp] + 4, high);
+
+	high = HIGH32BITS(lut->linear_only_start);
+	low = LOW32BITS(lut->linear_only_start);
+	dla_reg_write(engine->driver_context,
+				reg_base + lo_start_offset[is_sdp], low);
+	if (!is_sdp)
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_start_offset[is_sdp] + 4, high);
+
+	high = HIGH32BITS(lut->linear_only_end);
+	low = LOW32BITS(lut->linear_only_end);
+	dla_reg_write(engine->driver_context,
+				reg_base + lo_end_offset[is_sdp], low);
+	if (!is_sdp)
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_end_offset[is_sdp] + 4, high);
+
+	if (precision == PRECISION_FP16) {
+		reg = (lut->linear_exp_underflow_slope.data_f <<
+			SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_UFLOW_SCALE)) |
+			(lut->linear_exp_overflow_slope.data_f <<
+			SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_OFLOW_SCALE));
+		dla_reg_write(engine->driver_context,
+				reg_base + le_slope_scale_offset[is_sdp], reg);
+
+		reg = (lut->linear_only_underflow_slope.data_f <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_UFLOW_SCALE)) |
+			(lut->linear_only_overflow_slope.data_f <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_OFLOW_SCALE));
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_slope_scale_offset[is_sdp], reg);
+	} else {
+		union dla_slope *oslope;
+		union dla_slope *uslope;
+
+		uslope = &lut->linear_exp_underflow_slope;
+		oslope = &lut->linear_exp_overflow_slope;
+		reg = ((((uint32_t)uslope->data_i.scale)
+			<< SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_UFLOW_SCALE))&
+			MASK(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_UFLOW_SCALE)) |
+			((((uint32_t)oslope->data_i.scale)
+			<< SHIFT(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_OFLOW_SCALE))&
+			MASK(CDP_S_LUT_LE_SLOPE_SCALE_0,
+					LUT_LE_SLOPE_OFLOW_SCALE));
+		dla_reg_write(engine->driver_context,
+				reg_base + le_slope_scale_offset[is_sdp], reg);
+
+		reg = ((((uint32_t)uslope->data_i.shifter) <<
+			SHIFT(CDP_S_LUT_LE_SLOPE_SHIFT_0,
+					LUT_LE_SLOPE_UFLOW_SHIFT))&
+			MASK(CDP_S_LUT_LE_SLOPE_SHIFT_0,
+					LUT_LE_SLOPE_UFLOW_SHIFT)) |
+			((((uint32_t)oslope->data_i.shifter) <<
+			SHIFT(CDP_S_LUT_LE_SLOPE_SHIFT_0,
+					LUT_LE_SLOPE_OFLOW_SHIFT))&
+			MASK(CDP_S_LUT_LE_SLOPE_SHIFT_0,
+					LUT_LE_SLOPE_OFLOW_SHIFT));
+		dla_reg_write(engine->driver_context,
+				reg_base + le_slope_shift_offset[is_sdp], reg);
+
+		uslope = &lut->linear_only_underflow_slope;
+		oslope = &lut->linear_only_overflow_slope;
+		reg = ((((uint32_t)uslope->data_i.scale) <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_UFLOW_SCALE))&
+			MASK(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_UFLOW_SCALE)) |
+			((((uint32_t)oslope->data_i.scale) <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_OFLOW_SCALE))&
+			MASK(CDP_S_LUT_LO_SLOPE_SCALE_0,
+					LUT_LO_SLOPE_OFLOW_SCALE));
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_slope_scale_offset[is_sdp], reg);
+		reg = ((((uint32_t)uslope->data_i.shifter) <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SHIFT_0,
+					LUT_LO_SLOPE_UFLOW_SHIFT))&
+			MASK(CDP_S_LUT_LO_SLOPE_SHIFT_0,
+					LUT_LO_SLOPE_UFLOW_SHIFT)) |
+			((((uint32_t)oslope->data_i.shifter) <<
+			SHIFT(CDP_S_LUT_LO_SLOPE_SHIFT_0,
+					LUT_LO_SLOPE_OFLOW_SHIFT))&
+			MASK(CDP_S_LUT_LO_SLOPE_SHIFT_0,
+					LUT_LO_SLOPE_OFLOW_SHIFT));
+		dla_reg_write(engine->driver_context,
+				reg_base + lo_slope_shift_offset[is_sdp], reg);
+	}
+}
+
+int
+validate_data_cube(struct dla_data_cube src_data_cube,
+			struct dla_data_cube dst_data_cube,
+			uint8_t mem_type)
+{
+	int32_t ret = 0;
+
+	dla_trace("Enter: %s", __func__);
+
+	if ((src_data_cube.width > DCUBE_MAX_WIDTH) ||
+	    (src_data_cube.height > DCUBE_MAX_HEIGHT) ||
+	    (src_data_cube.channel > DCUBE_MAX_CHANNEL)) {
+		dla_error("Invalid SrcInput Cude[W: %u, H: %u, C: %u]",
+				src_data_cube.width, src_data_cube.height,
+				src_data_cube.channel);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if ((dst_data_cube.width > DCUBE_MAX_WIDTH) ||
+	    (dst_data_cube.height > DCUBE_MAX_HEIGHT) ||
+	    (dst_data_cube.channel > DCUBE_MAX_CHANNEL)) {
+		dla_error("Invalid DstInput Cude[W: %u, H: %u, C: %u]",
+				dst_data_cube.width, dst_data_cube.height,
+				dst_data_cube.channel);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (src_data_cube.type > mem_type) {
+		dla_error("Invalid src_data.mem_type: %u\n", src_data_cube.type);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (dst_data_cube.type > mem_type) {
+		dla_error("Invalid dst_data.mem_type: %u\n", dst_data_cube.type);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+int
+validate_precision(uint8_t precision, uint8_t map_precision)
+{
+	int32_t ret = 0;
+
+	if (precision >= map_precision) {
+		dla_error("Invalid precision: %u\n", precision);
+		ret = ERR(INVALID_INPUT);
+	}
+
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/common.h b/drivers/nvdla/common.h
new file mode 100644
index 000000000000..2605cfc6e8d8
--- /dev/null
+++ b/drivers/nvdla/common.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_COMMON_H_
+#define __FIRMWARE_COMMON_H_
+
+#include <dla_interface.h>
+
+#define DCUBE_MAX_WIDTH		8192
+#define DCUBE_MAX_HEIGHT	8192
+#define DCUBE_MAX_CHANNEL	8192
+
+void update_lut(uint32_t reg_base,
+		struct dla_lut_param *lut,
+		uint8_t precision);
+int32_t validate_data_cube(struct dla_data_cube src_data_cube,
+			struct dla_data_cube dst_data_cube,
+			uint8_t mem_type);
+int32_t validate_precision(uint8_t precision,
+			uint8_t map_precision);
+
+#endif /* __FIRMWARE_COMMON_H_ */
diff --git a/drivers/nvdla/conv.c b/drivers/nvdla/conv.c
new file mode 100644
index 000000000000..be62d65d9b57
--- /dev/null
+++ b/drivers/nvdla/conv.c
@@ -0,0 +1,779 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "common.h"
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+static const uint8_t map_precision[] = {
+	FIELD_ENUM(CDMA_D_MISC_CFG_0, IN_PRECISION, INT8),
+	FIELD_ENUM(CDMA_D_MISC_CFG_0, IN_PRECISION, INT16),
+	FIELD_ENUM(CDMA_D_MISC_CFG_0, IN_PRECISION, FP16),
+};
+
+static const uint8_t map_conv[] = {
+	FIELD_ENUM(CACC_D_MISC_CFG_0, CONV_MODE, DIRECT),
+	FIELD_ENUM(CACC_D_MISC_CFG_0, CONV_MODE, WINOGRAD),
+};
+
+static const uint8_t map_weight_fmt[] = {
+	FIELD_ENUM(CSC_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT, UNCOMPRESSED),
+	FIELD_ENUM(CSC_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT, COMPRESSED),
+};
+
+static const uint8_t map_img_fmt[][2] = {
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R8), 1},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R10), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R12), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R16), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R16_I), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R16_F), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A16B16G16R16), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_X16B16G16R16), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A16B16G16R16_F), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A16Y16U16V16), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_V16U16Y16A16), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A16Y16U16V16_F), 8},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A8B8G8R8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A8R8G8B8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_B8G8R8A8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R8G8B8A8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_X8B8G8R8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_X8R8G8B8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_B8G8R8X8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R8G8B8X8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A2B10G10R10), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A2R10G10B10), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_B10G10R10A2), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_R10G10B10A2), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A2Y10U10V10), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_V10U10Y10A2), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_A8Y8U8V8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_V8U8Y8A8), 4},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y8___U8V8_N444), 1},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y8___V8U8_N444), 1},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y10___U10V10_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y10___V10U10_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y12___U12V12_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y12___V12U12_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y16___U16V16_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			PIXEL_FORMAT, T_Y16___V16U16_N444), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			DATAIN_FORMAT, FEATURE), 2},
+	{FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+			DATAIN_FORMAT, PIXEL), 1},
+};
+
+static const uint8_t map_pixel[] = {
+	FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0, PIXEL_MAPPING, PITCH_LINEAR),
+};
+
+static const uint8_t map_ram[] = {
+	FIELD_ENUM(CDMA_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, MCIF),
+	FIELD_ENUM(CDMA_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, CVIF),
+};
+
+static const uint8_t map_mean[] = {
+	FIELD_ENUM(CDMA_D_MEAN_FORMAT_0, MEAN_FORMAT, DISABLE),
+	FIELD_ENUM(CDMA_D_MEAN_FORMAT_0, MEAN_FORMAT, ENABLE),
+};
+
+#if STAT_ENABLE
+void
+dla_conv_stat_data(struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	uint64_t end_time = 0;
+	struct dla_conv_stat_desc *conv_stat;
+
+	conv_stat = &processor->stat_data_desc->conv_stat;
+
+	end_time = dla_get_time_us();
+
+	conv_stat->data_read_stall = cdma_reg_read(D_PERF_DAT_READ_STALL);
+	conv_stat->weight_read_stall = cdma_reg_read(D_PERF_WT_READ_STALL);
+	conv_stat->data_read_latency = cdma_reg_read(D_PERF_DAT_READ_LATENCY);
+	conv_stat->weight_read_latency = cdma_reg_read(D_PERF_WT_READ_LATENCY);
+	conv_stat->nan_data_num = cdma_reg_read(D_NAN_INPUT_DATA_NUM);
+	conv_stat->nan_weight_num = cdma_reg_read(D_NAN_INPUT_WEIGHT_NUM);
+	conv_stat->inf_data_num = cdma_reg_read(D_INF_INPUT_DATA_NUM);
+	conv_stat->inf_weight_num = cdma_reg_read(D_INF_INPUT_WEIGHT_NUM);
+	conv_stat->saturation_count = cacc_reg_read(D_OUT_SATURATION);
+	conv_stat->runtime = (uint32_t)(end_time - group->start_time);
+}
+
+void
+dla_conv_dump_stat(struct dla_processor *processor)
+{
+	struct dla_conv_stat_desc *conv_stat;
+
+	conv_stat = &processor->stat_data_desc->conv_stat;
+
+	dla_debug_conv_stats(conv_stat);
+}
+#endif /* STAT_ENABLE */
+
+static uint32_t
+get_in_format(uint8_t format)
+{
+	uint32_t in_format = 0;
+
+	if (format >= FORMAT_T_R8 && format < FORMAT_FEATURE) {
+		in_format = FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+						DATAIN_FORMAT, PIXEL);
+	} else if (format == FORMAT_FEATURE) {
+		in_format = FIELD_ENUM(CDMA_D_DATAIN_FORMAT_0,
+						DATAIN_FORMAT, FEATURE);
+	} else {
+		assert(0);
+	}
+
+	return in_format;
+}
+
+void
+dla_conv_set_producer(int32_t group_id, int32_t rdma_group_id)
+{
+	uint32_t reg;
+
+	/* set producer pointer for all sub-modules */
+	reg = group_id << SHIFT(CACC_S_POINTER_0, PRODUCER);
+	cacc_reg_write(S_POINTER, reg);
+	cmac_a_reg_write(S_POINTER, reg);
+	cmac_b_reg_write(S_POINTER, reg);
+	csc_reg_write(S_POINTER, reg);
+	cdma_reg_write(S_POINTER, reg);
+}
+
+int
+dla_conv_enable(struct dla_processor_group *group)
+{
+	uint32_t reg;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_trace("Enter: %s", __func__);
+
+	do {
+		reg = cdma_reg_read(S_CBUF_FLUSH_STATUS);
+	} while (!(reg & MASK(CDMA_S_CBUF_FLUSH_STATUS_0, FLUSH_DONE)));
+
+	if (engine->stat_enable == (uint32_t)1) {
+		cdma_reg_write(D_PERF_ENABLE, 1);
+		group->start_time = dla_get_time_us();
+	}
+
+	/* enable all sub-modules */
+	reg = FIELD_ENUM(CACC_D_OP_ENABLE_0, OP_EN, ENABLE);
+	cacc_reg_write(D_OP_ENABLE, reg);
+	cmac_a_reg_write(D_OP_ENABLE, reg);
+	cmac_b_reg_write(D_OP_ENABLE, reg);
+	csc_reg_write(D_OP_ENABLE, reg);
+	cdma_reg_write(D_OP_ENABLE, reg);
+
+	dla_trace("Exit: %s", __func__);
+
+	RETURN(0);
+}
+
+void
+dla_conv_rdma_check(struct dla_processor_group *group)
+{
+	group->is_rdma_needed = 0;
+}
+
+static int32_t
+processor_conv_program(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	uint32_t reg, high, low, shift, mask;
+	uint32_t stride_x, stride_y, pad_x, pad_y;
+	uint64_t weight_address = 0;
+	uint64_t wmb_address = 0;
+	uint64_t wgs_address = 0;
+	uint64_t input_address = 0;
+	uint64_t output_address = 0;
+	uint32_t atom_size = 0;
+	bool weight_compress_support = false;
+	struct dla_engine *engine = dla_get_engine();
+	struct dla_conv_op_desc *conv_op;
+	struct dla_conv_surface_desc *conv_surface;
+
+	dla_trace("Enter: %s", __func__);
+
+	weight_compress_support = engine->config_data->weight_compress_support;
+	atom_size = engine->config_data->atom_size;
+	conv_op = &group->operation_desc->conv_op;
+	conv_surface = &group->surface_desc->conv_surface;
+
+	if (conv_op->weight_format == WEIGHT_FORMAT_COMPRESSED) {
+		ASSERT_GOTO((weight_compress_support), ret, ERR(INVALID_INPUT), exit);
+		ASSERT_GOTO((conv_surface->wmb_data.address != -1),
+			ret, ERR(INVALID_INPUT), exit);
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					conv_surface->wmb_data.address,
+					conv_surface->wmb_data.offset,
+					(void *)&wmb_address,
+					DESTINATION_DMA);
+		CHECK_ALIGN(wmb_address, atom_size);
+		CHECK_ALIGN(conv_surface->wmb_data.size, 128);
+
+		ASSERT_GOTO((conv_surface->wgs_data.address != -1),
+			ret, ERR(INVALID_INPUT), exit);
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					conv_surface->wgs_data.address,
+					conv_surface->wgs_data.offset,
+					(void *)&wgs_address,
+					DESTINATION_DMA);
+		CHECK_ALIGN(wgs_address, atom_size);
+		CHECK_ALIGN(conv_surface->wgs_data.size, 4);
+	}
+
+	if (conv_surface->weight_data.address != -1) {
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					conv_surface->weight_data.address,
+					conv_surface->weight_data.offset,
+					(void *)&weight_address,
+					DESTINATION_DMA);
+		CHECK_ALIGN(weight_address, atom_size);
+		CHECK_ALIGN(conv_surface->weight_data.size, 128);
+	}
+
+	if (conv_surface->dst_data.address != -1) {
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					conv_surface->dst_data.address,
+					conv_surface->dst_data.offset,
+					(void *)&output_address,
+					DESTINATION_DMA);
+		CHECK_ALIGN(output_address, atom_size);
+		CHECK_ALIGN(conv_surface->dst_data.size, atom_size);
+		CHECK_ALIGN(conv_surface->dst_data.line_stride, atom_size);
+		CHECK_ALIGN(conv_surface->dst_data.surf_stride, atom_size);
+	}
+
+	ret = dla_read_input_address(&conv_surface->src_data, &input_address,
+					group->op_desc->index,
+					group->roi_index,
+					map_img_fmt[conv_op->data_format][1]);
+	if (ret)
+		goto exit;
+
+	CHECK_ALIGN(input_address, atom_size);
+
+	ASSERT_GOTO((conv_op->out_cvt.scale  == 1),
+		ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO((conv_op->out_cvt.offset == 0),
+		ret, ERR(INVALID_INPUT), exit);
+
+	/* check if the register group is idle */
+	reg = cacc_reg_read(S_STATUS);
+	mask = group->id ? MASK(CACC_S_STATUS_0, STATUS_1) :
+		MASK(CACC_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CACC_S_STATUS_0, STATUS_1) :
+		SHIFT(CACC_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CACC_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	reg = cmac_a_reg_read(S_STATUS);
+	mask = group->id ? MASK(CMAC_A_S_STATUS_0, STATUS_1) :
+        MASK(CMAC_A_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CMAC_A_S_STATUS_0, STATUS_1) :
+		SHIFT(CMAC_A_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CMAC_A_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	reg = cmac_b_reg_read(S_STATUS);
+	mask = group->id ? MASK(CMAC_B_S_STATUS_0, STATUS_1) :
+		MASK(CMAC_B_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CMAC_B_S_STATUS_0, STATUS_1) :
+		SHIFT(CMAC_B_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CMAC_B_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	reg = csc_reg_read(S_STATUS);
+	mask = group->id ? MASK(CSC_S_STATUS_0, STATUS_1) :
+		MASK(CSC_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CSC_S_STATUS_0, STATUS_1) :
+		SHIFT(CSC_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CSC_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	reg = cdma_reg_read(S_STATUS);
+	mask = group->id ? MASK(CDMA_S_STATUS_0, STATUS_1) :
+		MASK(CDMA_S_STATUS_0, STATUS_0);
+	shift = group->id ? SHIFT(CDMA_S_STATUS_0, STATUS_1) :
+		SHIFT(CDMA_S_STATUS_0, STATUS_0);
+	reg = (reg & mask) >> shift;
+	ASSERT_GOTO((reg == FIELD_ENUM(CDMA_S_STATUS_0, STATUS_0, IDLE)),
+		ret, ERR(INVALID_INPUT), exit);
+
+	/* reverse config each sub-module in CC */
+
+	/* CACC */
+	reg = (map_conv[conv_op->conv_mode]
+		<< SHIFT(CACC_D_MISC_CFG_0, CONV_MODE)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CACC_D_MISC_CFG_0, PROC_PRECISION));
+	cacc_reg_write(D_MISC_CFG, reg);
+
+	reg = ((conv_surface->dst_data.width - 1)
+		<< SHIFT(CACC_D_DATAOUT_SIZE_0_0, DATAOUT_WIDTH)) |
+		((conv_surface->dst_data.height - 1)
+		<< SHIFT(CACC_D_DATAOUT_SIZE_0_0, DATAOUT_HEIGHT));
+	cacc_reg_write(D_DATAOUT_SIZE_0, reg);
+
+	reg = ((conv_surface->dst_data.channel - 1)
+		<< SHIFT(CACC_D_DATAOUT_SIZE_1_0, DATAOUT_CHANNEL));
+	cacc_reg_write(D_DATAOUT_SIZE_1, reg);
+
+	low = LOW32BITS(output_address);
+	cacc_reg_write(D_DATAOUT_ADDR, low);
+	cacc_reg_write(D_BATCH_NUMBER, conv_op->batch - 1);
+	cacc_reg_write(D_LINE_STRIDE, conv_surface->dst_data.line_stride);
+	cacc_reg_write(D_SURF_STRIDE, conv_surface->dst_data.surf_stride);
+
+	if (conv_surface->dst_data.width == 1 &&
+				conv_surface->dst_data.height == 1) {
+		ASSERT_GOTO((((uint32_t)conv_surface->dst_data.line_stride ==
+			(uint32_t)(conv_surface->dst_data.width * atom_size))),
+			ret, ERR(INVALID_INPUT), exit);
+		reg = (CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE <<
+				SHIFT(CACC_D_DATAOUT_MAP_0, LINE_PACKED));
+		reg |= (CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE <<
+				SHIFT(CACC_D_DATAOUT_MAP_0, SURF_PACKED));
+	} else {
+		reg = (FIELD_ENUM(CACC_D_DATAOUT_MAP_0, LINE_PACKED, FALSE) <<
+				SHIFT(CACC_D_DATAOUT_MAP_0, LINE_PACKED));
+		reg |= (FIELD_ENUM(CACC_D_DATAOUT_MAP_0, SURF_PACKED, FALSE) <<
+				SHIFT(CACC_D_DATAOUT_MAP_0, SURF_PACKED));
+	}
+	cacc_reg_write(D_DATAOUT_MAP, reg);
+
+	cacc_reg_write(D_CLIP_CFG, conv_op->out_cvt.truncate);
+
+	/* CMAC */
+	reg = (map_conv[conv_op->conv_mode]
+		<< SHIFT(CMAC_A_D_MISC_CFG_0, CONV_MODE)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CMAC_A_D_MISC_CFG_0, PROC_PRECISION));
+	cmac_a_reg_write(D_MISC_CFG, reg);
+	cmac_b_reg_write(D_MISC_CFG, reg);
+
+	/* CSC */
+	reg = (map_conv[conv_op->conv_mode]
+		<< SHIFT(CSC_D_MISC_CFG_0, CONV_MODE)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CSC_D_MISC_CFG_0, IN_PRECISION)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CSC_D_MISC_CFG_0, PROC_PRECISION)) |
+		(conv_op->data_reuse
+		<< SHIFT(CSC_D_MISC_CFG_0, DATA_REUSE)) |
+		(conv_op->weight_reuse
+		<< SHIFT(CSC_D_MISC_CFG_0, WEIGHT_REUSE)) |
+		(conv_op->skip_data_rls
+		<< SHIFT(CSC_D_MISC_CFG_0, SKIP_DATA_RLS)) |
+		(conv_op->skip_weight_rls
+		<< SHIFT(CSC_D_MISC_CFG_0, SKIP_WEIGHT_RLS));
+	csc_reg_write(D_MISC_CFG, reg);
+
+	reg = (get_in_format(conv_op->data_format) <<
+		SHIFT(CSC_D_DATAIN_FORMAT_0, DATAIN_FORMAT));
+	csc_reg_write(D_DATAIN_FORMAT, reg);
+
+	reg = ((conv_op->input_width_csc - 1)
+		<< SHIFT(CSC_D_DATAIN_SIZE_EXT_0_0, DATAIN_WIDTH_EXT)) |
+		((conv_op->input_height_csc - 1)
+		<< SHIFT(CSC_D_DATAIN_SIZE_EXT_0_0, DATAIN_HEIGHT_EXT));
+	csc_reg_write(D_DATAIN_SIZE_EXT_0, reg);
+
+	reg = ((conv_op->input_channel_csc - 1)
+		<< SHIFT(CSC_D_DATAIN_SIZE_EXT_1_0, DATAIN_CHANNEL_EXT));
+	csc_reg_write(D_DATAIN_SIZE_EXT_1, reg);
+
+	reg = ((conv_op->batch - 1)
+		<< SHIFT(CSC_D_BATCH_NUMBER_0, BATCHES));
+	csc_reg_write(D_BATCH_NUMBER, reg);
+	reg = ((conv_op->post_extension)
+		<< SHIFT(CSC_D_POST_Y_EXTENSION_0, Y_EXTENSION));
+	csc_reg_write(D_POST_Y_EXTENSION, reg);
+
+	reg = ((conv_op->entry_per_slice - 1)
+		<< SHIFT(CSC_D_ENTRY_PER_SLICE_0, ENTRIES));
+	csc_reg_write(D_ENTRY_PER_SLICE, reg);
+
+	reg = (map_weight_fmt[conv_op->weight_format]
+		<< SHIFT(CSC_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT));
+	csc_reg_write(D_WEIGHT_FORMAT, reg);
+
+	reg = ((conv_op->kernel_width_csc - 1)
+		<< SHIFT(CSC_D_WEIGHT_SIZE_EXT_0_0, WEIGHT_WIDTH_EXT)) |
+		((conv_op->kernel_height_csc - 1)
+		<< SHIFT(CSC_D_WEIGHT_SIZE_EXT_0_0, WEIGHT_HEIGHT_EXT));
+	csc_reg_write(D_WEIGHT_SIZE_EXT_0, reg);
+
+	reg = ((conv_op->kernel_channel_csc - 1)
+		<< SHIFT(CSC_D_WEIGHT_SIZE_EXT_1_0, WEIGHT_CHANNEL_EXT)) |
+		((conv_surface->dst_data.channel - 1)
+		<< SHIFT(CSC_D_WEIGHT_SIZE_EXT_1_0, WEIGHT_KERNEL));
+	csc_reg_write(D_WEIGHT_SIZE_EXT_1, reg);
+
+	csc_reg_write(D_WEIGHT_BYTES, conv_surface->weight_data.size);
+	csc_reg_write(D_WMB_BYTES, conv_surface->wmb_data.size);
+
+	reg = ((conv_op->input_width_cmac - 1)
+		<< SHIFT(CSC_D_DATAOUT_SIZE_0_0, DATAOUT_WIDTH)) |
+		((conv_op->input_height_cmac - 1)
+		<< SHIFT(CSC_D_DATAOUT_SIZE_0_0, DATAOUT_HEIGHT));
+	csc_reg_write(D_DATAOUT_SIZE_0, reg);
+
+	reg = ((conv_surface->dst_data.channel - 1)
+		<< SHIFT(CSC_D_DATAOUT_SIZE_1_0, DATAOUT_CHANNEL));
+	csc_reg_write(D_DATAOUT_SIZE_1, reg);
+
+	reg = ((conv_surface->dst_data.width *
+				conv_surface->dst_data.height - 1)
+		<< SHIFT(CSC_D_ATOMICS_0, ATOMICS));
+	csc_reg_write(D_ATOMICS, reg);
+	reg = ((conv_op->release - 1)
+		<< SHIFT(CSC_D_RELEASE_0, RLS_SLICES));
+	csc_reg_write(D_RELEASE, reg);
+
+	if (conv_op->conv_mode == CONV_MODE_DIRECT) {
+		stride_x = conv_op->conv_stride_x - 1;
+		stride_y = conv_op->conv_stride_y - 1;
+		pad_x = conv_op->pad_x_left;
+		pad_y = conv_op->pad_y_top;
+	} else {
+		stride_x = 0;
+		stride_y = 0;
+		pad_x = 0;
+		pad_y = 0;
+	}
+
+	reg = (stride_x
+		<< SHIFT(CSC_D_CONV_STRIDE_EXT_0, CONV_X_STRIDE_EXT)) |
+		(stride_y
+		<< SHIFT(CSC_D_CONV_STRIDE_EXT_0, CONV_Y_STRIDE_EXT));
+	csc_reg_write(D_CONV_STRIDE_EXT, reg);
+
+	reg = ((conv_op->dilation_x - 1)
+		<< SHIFT(CSC_D_DILATION_EXT_0, X_DILATION_EXT)) |
+		((conv_op->dilation_y - 1)
+		<< SHIFT(CSC_D_DILATION_EXT_0, Y_DILATION_EXT));
+	csc_reg_write(D_DILATION_EXT, reg);
+
+	reg = (pad_x
+		<< SHIFT(CSC_D_ZERO_PADDING_0, PAD_LEFT)) |
+		(pad_y
+		<< SHIFT(CSC_D_ZERO_PADDING_0, PAD_TOP));
+	csc_reg_write(D_ZERO_PADDING, reg);
+
+	reg = (conv_op->pad_val
+		<< SHIFT(CSC_D_ZERO_PADDING_VALUE_0, PAD_VALUE)) &
+		MASK(CSC_D_ZERO_PADDING_VALUE_0, PAD_VALUE);
+	csc_reg_write(D_ZERO_PADDING_VALUE, reg);
+
+	reg = ((conv_op->data_bank - 1)
+		<< SHIFT(CSC_D_BANK_0, DATA_BANK)) |
+		((conv_op->weight_bank - 1)
+		<< SHIFT(CSC_D_BANK_0, WEIGHT_BANK));
+	csc_reg_write(D_BANK, reg);
+	csc_reg_write(D_PRA_CFG, conv_op->pra_truncate);
+
+	/* CBUF */
+	/* there's no CBUF register */
+
+	/* CDMA */
+	reg = (map_conv[conv_op->conv_mode]
+		<< SHIFT(CDMA_D_MISC_CFG_0, CONV_MODE)) |
+		(map_precision[conv_op->in_precision]
+		<< SHIFT(CDMA_D_MISC_CFG_0, IN_PRECISION)) |
+		(map_precision[conv_op->out_precision]
+		<< SHIFT(CDMA_D_MISC_CFG_0, PROC_PRECISION)) |
+		(conv_op->data_reuse
+		<< SHIFT(CDMA_D_MISC_CFG_0, DATA_REUSE)) |
+		(conv_op->weight_reuse
+		<< SHIFT(CDMA_D_MISC_CFG_0, WEIGHT_REUSE)) |
+		(conv_op->skip_data_rls
+		<< SHIFT(CDMA_D_MISC_CFG_0, SKIP_DATA_RLS)) |
+		(conv_op->skip_weight_rls
+		<< SHIFT(CDMA_D_MISC_CFG_0, SKIP_WEIGHT_RLS));
+	cdma_reg_write(D_MISC_CFG, reg);
+
+	reg = (get_in_format(conv_op->data_format) <<
+		SHIFT(CDMA_D_DATAIN_FORMAT_0, DATAIN_FORMAT)) |
+		(map_img_fmt[conv_op->data_format][0]
+		<< SHIFT(CDMA_D_DATAIN_FORMAT_0, PIXEL_FORMAT)) |
+		(map_pixel[conv_op->pixel_mapping]
+		<< SHIFT(CDMA_D_DATAIN_FORMAT_0, PIXEL_MAPPING)) |
+		(conv_op->pixel_override
+		<< SHIFT(CDMA_D_DATAIN_FORMAT_0, PIXEL_SIGN_OVERRIDE));
+	cdma_reg_write(D_DATAIN_FORMAT, reg);
+
+	reg = ((conv_surface->src_data.width - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_0_0, DATAIN_WIDTH)) |
+		((conv_surface->src_data.height - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_0_0, DATAIN_HEIGHT));
+	cdma_reg_write(D_DATAIN_SIZE_0, reg);
+
+	reg = ((conv_surface->src_data.channel - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_1_0, DATAIN_CHANNEL));
+	cdma_reg_write(D_DATAIN_SIZE_1, reg);
+
+	reg = ((conv_op->input_width_csc - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_EXT_0_0, DATAIN_WIDTH_EXT)) |
+		((conv_op->input_height_csc - 1)
+		<< SHIFT(CDMA_D_DATAIN_SIZE_EXT_0_0, DATAIN_HEIGHT_EXT));
+	cdma_reg_write(D_DATAIN_SIZE_EXT_0, reg);
+
+	reg = (map_ram[conv_surface->src_data.type]
+		<< SHIFT(CDMA_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE));
+	cdma_reg_write(D_DAIN_RAM_TYPE, reg);
+
+	high = HIGH32BITS(input_address);
+	low = LOW32BITS(input_address);
+	cdma_reg_write(D_DAIN_ADDR_HIGH_0, high);
+	cdma_reg_write(D_DAIN_ADDR_LOW_0, low);
+
+	high = HIGH32BITS((input_address + conv_surface->offset_u));
+	low = LOW32BITS(input_address + conv_surface->offset_u);
+	cdma_reg_write(D_DAIN_ADDR_HIGH_1, high);
+	cdma_reg_write(D_DAIN_ADDR_LOW_1, low);
+
+	cdma_reg_write(D_LINE_STRIDE, conv_surface->src_data.line_stride);
+	cdma_reg_write(D_SURF_STRIDE, conv_surface->src_data.surf_stride);
+	cdma_reg_write(D_LINE_UV_STRIDE, conv_surface->in_line_uv_stride);
+
+	reg = ((conv_surface->src_data.line_stride ==
+			((uint32_t)conv_surface->src_data.width * atom_size))
+		<< SHIFT(CDMA_D_DAIN_MAP_0, LINE_PACKED));
+	reg |= ((conv_surface->src_data.surf_stride ==
+			((uint32_t)(conv_surface->src_data.width *
+			conv_surface->src_data.height) * atom_size))
+		<< SHIFT(CDMA_D_DAIN_MAP_0, SURF_PACKED));
+	cdma_reg_write(D_DAIN_MAP, reg);
+
+	reg = ((conv_op->batch - 1)
+		<< SHIFT(CDMA_D_BATCH_NUMBER_0, BATCHES));
+	cdma_reg_write(D_BATCH_NUMBER, reg);
+
+	cdma_reg_write(D_BATCH_STRIDE, conv_op->batch_stride);
+
+	reg = ((conv_op->entry_per_slice - 1)
+		<< SHIFT(CDMA_D_ENTRY_PER_SLICE_0, ENTRIES));
+	cdma_reg_write(D_ENTRY_PER_SLICE, reg);
+
+	reg = ((conv_op->fetch_grain - 1)
+		<< SHIFT(CDMA_D_FETCH_GRAIN_0, GRAINS));
+	cdma_reg_write(D_FETCH_GRAIN, reg);
+
+	reg = (map_weight_fmt[conv_op->weight_format]
+		<< SHIFT(CDMA_D_WEIGHT_FORMAT_0, WEIGHT_FORMAT));
+	cdma_reg_write(D_WEIGHT_FORMAT, reg);
+
+	reg = ((conv_op->bytes_per_kernel - 1)
+		<< SHIFT(CDMA_D_WEIGHT_SIZE_0_0, BYTE_PER_KERNEL));
+	cdma_reg_write(D_WEIGHT_SIZE_0, reg);
+
+	reg = ((conv_surface->dst_data.channel - 1)
+		<< SHIFT(CDMA_D_WEIGHT_SIZE_1_0, WEIGHT_KERNEL));
+	cdma_reg_write(D_WEIGHT_SIZE_1, reg);
+
+	reg = (map_ram[conv_surface->weight_data.type]
+		<< SHIFT(CDMA_D_WEIGHT_RAM_TYPE_0, WEIGHT_RAM_TYPE));
+	cdma_reg_write(D_WEIGHT_RAM_TYPE, reg);
+
+	high = HIGH32BITS(weight_address);
+	low = LOW32BITS(weight_address);
+	cdma_reg_write(D_WEIGHT_ADDR_HIGH, high);
+	cdma_reg_write(D_WEIGHT_ADDR_LOW, low);
+	cdma_reg_write(D_WEIGHT_BYTES, conv_surface->weight_data.size);
+
+	if (conv_op->weight_format == WEIGHT_FORMAT_COMPRESSED) {
+		high = HIGH32BITS(wgs_address);
+		low = LOW32BITS(wgs_address);
+		cdma_reg_write(D_WGS_ADDR_HIGH, high);
+		cdma_reg_write(D_WGS_ADDR_LOW, low);
+
+		high = HIGH32BITS(wmb_address);
+		low = LOW32BITS(wmb_address);
+		cdma_reg_write(D_WMB_ADDR_HIGH, high);
+		cdma_reg_write(D_WMB_ADDR_LOW, low);
+		cdma_reg_write(D_WMB_BYTES, conv_surface->wmb_data.size);
+	}
+
+	reg = (map_mean[conv_op->mean_format]
+		<< SHIFT(CDMA_D_MEAN_FORMAT_0, MEAN_FORMAT));
+	cdma_reg_write(D_MEAN_FORMAT, reg);
+
+	if (conv_op->mean_format == MEAN_FORMAT_ENABLE) {
+		reg = ((conv_op->mean_ry
+			<< SHIFT(CDMA_D_MEAN_GLOBAL_0_0, MEAN_RY)) &
+			MASK(CDMA_D_MEAN_GLOBAL_0_0, MEAN_RY)) |
+			((conv_op->mean_gu
+			<< SHIFT(CDMA_D_MEAN_GLOBAL_0_0, MEAN_GU)) &
+			MASK(CDMA_D_MEAN_GLOBAL_0_0, MEAN_GU));
+		cdma_reg_write(D_MEAN_GLOBAL_0, reg);
+
+		reg = ((conv_op->mean_bv
+			<< SHIFT(CDMA_D_MEAN_GLOBAL_1_0, MEAN_BV))&
+			MASK(CDMA_D_MEAN_GLOBAL_1_0, MEAN_BV)) |
+			((conv_op->mean_ax
+			<< SHIFT(CDMA_D_MEAN_GLOBAL_1_0, MEAN_AX))&
+			MASK(CDMA_D_MEAN_GLOBAL_1_0, MEAN_AX));
+		cdma_reg_write(D_MEAN_GLOBAL_1, reg);
+	}
+
+	if (conv_op->in_cvt.enable) {
+		reg = ((FIELD_ENUM(CDMA_D_CVT_CFG_0, CVT_EN, ENABLE))
+			<< SHIFT(CDMA_D_CVT_CFG_0, CVT_EN)) |
+			(conv_op->in_cvt.truncate
+			<< SHIFT(CDMA_D_CVT_CFG_0, CVT_TRUNCATE));
+		cdma_reg_write(D_CVT_CFG, reg);
+		cdma_reg_write(D_CVT_OFFSET, conv_op->in_cvt.offset);
+		cdma_reg_write(D_CVT_SCALE, conv_op->in_cvt.scale);
+	} else {
+		reg = ((FIELD_ENUM(CDMA_D_CVT_CFG_0, CVT_EN, DISABLE))
+			<< SHIFT(CDMA_D_CVT_CFG_0, CVT_EN));
+		cdma_reg_write(D_CVT_CFG, reg);
+	}
+
+	reg = ((conv_op->conv_stride_x - 1)
+		<< SHIFT(CDMA_D_CONV_STRIDE_0, CONV_X_STRIDE)) |
+		((conv_op->conv_stride_y - 1)
+		<< SHIFT(CDMA_D_CONV_STRIDE_0, CONV_Y_STRIDE));
+	cdma_reg_write(D_CONV_STRIDE, reg);
+
+	reg = (conv_op->pad_x_left <<
+		SHIFT(CDMA_D_ZERO_PADDING_0, PAD_LEFT)) |
+		(conv_op->pad_x_right
+		<< SHIFT(CDMA_D_ZERO_PADDING_0, PAD_RIGHT)) |
+		(conv_op->pad_y_top
+		<< SHIFT(CDMA_D_ZERO_PADDING_0, PAD_TOP)) |
+		(conv_op->pad_y_bottom
+		<< SHIFT(CDMA_D_ZERO_PADDING_0, PAD_BOTTOM));
+	cdma_reg_write(D_ZERO_PADDING,   reg);
+
+	reg = conv_op->pad_val <<
+		SHIFT(CDMA_D_ZERO_PADDING_VALUE_0, PAD_VALUE) &
+		MASK(CDMA_D_ZERO_PADDING_VALUE_0, PAD_VALUE);
+	cdma_reg_write(D_ZERO_PADDING_VALUE, reg);
+	reg = ((conv_op->weight_bank - 1)
+		<< SHIFT(CDMA_D_BANK_0, WEIGHT_BANK)) |
+		((conv_op->data_bank - 1)
+		<< SHIFT(CDMA_D_BANK_0, DATA_BANK));
+	cdma_reg_write(D_BANK, reg);
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+int
+dla_conv_is_ready(struct dla_processor *processor,
+			    struct dla_processor_group *group)
+{
+	return 1;
+}
+
+void
+dla_conv_dump_config(struct dla_processor_group *group)
+{
+	struct dla_conv_op_desc *conv_op;
+	struct dla_conv_surface_desc *conv_surface;
+
+	conv_surface = &group->surface_desc->conv_surface;
+	conv_op = &group->operation_desc->conv_op;
+
+	dla_debug_conv_surface_desc(conv_surface, group->roi_index);
+	dla_debug_conv_op_desc(conv_op, group->roi_index);
+}
+
+int
+dla_conv_program(struct dla_processor_group *group)
+{
+	int32_t ret;
+
+	dla_trace("Enter: %s", __func__);
+
+	ret = processor_conv_program(group);
+	if (ret)
+		goto exit;
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/dla_engine_internal.h b/drivers/nvdla/dla_engine_internal.h
new file mode 100644
index 000000000000..d29c7b4c56c3
--- /dev/null
+++ b/drivers/nvdla/dla_engine_internal.h
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_DLA_ENGINE_INTERNAL_H_
+#define __FIRMWARE_DLA_ENGINE_INTERNAL_H_
+
+#include <opendla.h>
+#include <dla_engine.h>
+#include <dla_interface.h>
+#include <dla_debug.h>
+
+#include "nvdla_interface.h"
+
+#define BITS(num, range) ((((0xFFFFFFFF >> (31 - (1 ? range))) & \
+			(0xFFFFFFFF << (0 ? range))) & num) >> \
+			(0 ? range))
+#define HIGH32BITS(val64bit) ((uint32_t)(val64bit >> 32))
+#define LOW32BITS(val64bit) ((uint32_t)(val64bit))
+
+#ifdef MIN
+#undef MIN
+#endif /* MIN */
+
+#ifdef MAX
+#undef MAX
+#endif /* MAX */
+
+#define MIN(a, b) ((a) > (b) ? (b) : (a))
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+
+/*********************************************************/
+/******************** Utilities **************************/
+/*********************************************************/
+#ifdef DEBUG
+#define CHECK_ALIGN(val, align)		 assert((val&(align-1)) == 0)
+#else
+#define CHECK_ALIGN(val, align)
+#endif /* DEBUG */
+
+#define MASK(reg, field)		(reg##_##field##_FIELD)
+#define FIELD_ENUM(r, f, e)		(r##_##f##_##e)
+#define SHIFT(reg, field)		(reg##_##field##_SHIFT)
+
+#define GLB_REG(name)                GLB_##name##_0
+#define MCIF_REG(name)               MCIF_##name##_0
+#define CVIF_REG(name)               CVIF_##name##_0
+#define BDMA_REG(name)               BDMA_##name##_0
+#define CDMA_REG(name)               CDMA_##name##_0
+#define CSC_REG(name)                CSC_##name##_0
+#define CMAC_A_REG(name)             CMAC_A_##name##_0
+#define CMAC_B_REG(name)             CMAC_B_##name##_0
+#define CACC_REG(name)               CACC_##name##_0
+#define SDP_RDMA_REG(name)           SDP_RDMA_##name##_0
+#define SDP_REG(name)                SDP_##name##_0
+#define PDP_RDMA_REG(name)           PDP_RDMA_##name##_0
+#define PDP_REG(name)                PDP_##name##_0
+#define CDP_RDMA_REG(name)           CDP_RDMA_##name##_0
+#define CDP_REG(name)                CDP_##name##_0
+#define RBK_REG(name)                RBK_##name##_0
+
+/* alias for register read for each sub-module */
+#define glb_reg_read(reg)           reg_read(GLB_REG(reg))
+#define bdma_reg_read(reg)          reg_read(BDMA_REG(reg))
+#define cdma_reg_read(reg)          reg_read(CDMA_REG(reg))
+#define csc_reg_read(reg)           reg_read(CSC_REG(reg))
+#define cmac_a_reg_read(reg)        reg_read(CMAC_A_REG(reg))
+#define cmac_b_reg_read(reg)        reg_read(CMAC_B_REG(reg))
+#define cacc_reg_read(reg)          reg_read(CACC_REG(reg))
+#define sdp_rdma_reg_read(reg)      reg_read(SDP_RDMA_REG(reg))
+#define sdp_reg_read(reg)           reg_read(SDP_REG(reg))
+#define pdp_rdma_reg_read(reg)      reg_read(PDP_RDMA_REG(reg))
+#define pdp_reg_read(reg)           reg_read(PDP_REG(reg))
+#define cdp_rdma_reg_read(reg)      reg_read(CDP_RDMA_REG(reg))
+#define cdp_reg_read(reg)           reg_read(CDP_REG(reg))
+#define rubik_reg_read(reg)         reg_read(RBK_REG(reg))
+
+/* alias for register write for each sub-module */
+#define glb_reg_write(reg, val)      reg_write(GLB_REG(reg), val)
+#define bdma_reg_write(reg, val)     reg_write(BDMA_REG(reg), val)
+#define cdma_reg_write(reg, val)     reg_write(CDMA_REG(reg), val)
+#define csc_reg_write(reg, val)      reg_write(CSC_REG(reg), val)
+#define cmac_a_reg_write(reg, val)   reg_write(CMAC_A_REG(reg), val)
+#define cmac_b_reg_write(reg, val)   reg_write(CMAC_B_REG(reg), val)
+#define cacc_reg_write(reg, val)     reg_write(CACC_REG(reg), val)
+#define sdp_rdma_reg_write(reg, val) reg_write(SDP_RDMA_REG(reg), val)
+#define sdp_reg_write(reg, val)      reg_write(SDP_REG(reg), val)
+#define pdp_rdma_reg_write(reg, val) reg_write(PDP_RDMA_REG(reg), val)
+#define pdp_reg_write(reg, val)      reg_write(PDP_REG(reg), val)
+#define cdp_rdma_reg_write(reg, val) reg_write(CDP_RDMA_REG(reg), val)
+#define cdp_reg_write(reg, val)      reg_write(CDP_REG(reg), val)
+#define rubik_reg_write(reg, val)    reg_write(RBK_REG(reg), val)
+
+void reg_write(uint32_t addr, uint32_t reg);
+uint32_t reg_read(uint32_t addr);
+
+/**
+ * Operation descriptor cache functions
+ */
+void
+dla_put_op_desc(struct dla_common_op_desc *op_desc);
+struct dla_common_op_desc
+*dla_get_op_desc(struct dla_task *task,
+			   int16_t index,
+			   uint8_t op_type,
+			   uint8_t roi_index);
+void
+dla_dump_op_desc(struct dla_common_op_desc *desc);
+void
+dla_get_refcount(struct dla_common_op_desc *op_desc);
+void
+dla_init_op_cache(struct dla_engine *engine);
+
+/**
+ * Operation completion handler
+ */
+int
+dla_op_completion(struct dla_processor *processor,
+		      struct dla_processor_group *group);
+
+int32_t
+dla_read_lut(struct dla_engine *engine, int16_t index, void *dst);
+int
+dla_enable_intr(uint32_t mask);
+int
+dla_disable_intr(uint32_t mask);
+int
+utils_get_free_group(struct dla_processor *processor,
+			uint8_t *group_id,
+			uint8_t *rdma_id);
+int32_t
+dla_get_dma_cube_address(void *driver_context,
+						void *task_data,
+						int16_t index,
+						uint32_t offset,
+						void *dst_ptr,
+						uint32_t destination);
+int
+dla_read_input_address(struct dla_data_cube *data,
+		       uint64_t *address,
+		       int16_t op_index,
+		       uint8_t roi_index,
+		       uint8_t bpp);
+
+/**
+ * BDMA operations
+ */
+void
+dla_bdma_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_bdma_enable(struct dla_processor_group *group);
+int
+dla_bdma_program(struct dla_processor_group *group);
+int
+dla_bdma_is_ready(struct dla_processor *processor,
+			    struct dla_processor_group *group);
+void
+dla_bdma_dump_config(struct dla_processor_group *group);
+void
+dla_bdma_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_bdma_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_bdma_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_bdma_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_bdma_dump_stat(struct dla_processor *processor) {}
+#endif
+
+/**
+ * Convolution operations
+ */
+void
+dla_conv_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_conv_enable(struct dla_processor_group *group);
+int
+dla_conv_program(struct dla_processor_group *group);
+int
+dla_conv_is_ready(struct dla_processor *processor,
+			    struct dla_processor_group *group);
+void
+dla_conv_dump_config(struct dla_processor_group *group);
+void
+dla_conv_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_conv_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_conv_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_conv_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_conv_dump_stat(struct dla_processor *processor) {}
+#endif /* STAT_ENABLE */
+
+/**
+ * SDP operations
+ */
+void
+dla_sdp_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_sdp_enable(struct dla_processor_group *group);
+int
+dla_sdp_program(struct dla_processor_group *group);
+int
+dla_sdp_is_ready(struct dla_processor *processor,
+			   struct dla_processor_group *group);
+void
+dla_sdp_dump_config(struct dla_processor_group *group);
+void
+dla_sdp_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_sdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_sdp_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_sdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_sdp_dump_stat(struct dla_processor *processor) {}
+#endif
+
+/**
+ * PDP operations
+ */
+void
+dla_pdp_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_pdp_enable(struct dla_processor_group *group);
+int
+dla_pdp_program(struct dla_processor_group *group);
+int
+dla_pdp_is_ready(struct dla_processor *processor,
+			   struct dla_processor_group *group);
+void
+dla_pdp_dump_config(struct dla_processor_group *group);
+void
+dla_pdp_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_pdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_pdp_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_pdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_pdp_dump_stat(struct dla_processor *processor) {}
+#endif
+
+/**
+ * CDP operations
+ */
+void
+dla_cdp_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_cdp_enable(struct dla_processor_group *group);
+int
+dla_cdp_program(struct dla_processor_group *group);
+int
+dla_cdp_is_ready(struct dla_processor *processor,
+			   struct dla_processor_group *group);
+void
+dla_cdp_dump_config(struct dla_processor_group *group);
+void
+dla_cdp_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_cdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_cdp_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_cdp_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_cdp_dump_stat(struct dla_processor *processor) {}
+#endif
+
+/**
+ * RUBIK operations
+ */
+void
+dla_rubik_set_producer(int32_t group_id, int32_t rdma_group_id);
+int
+dla_rubik_enable(struct dla_processor_group *group);
+int
+dla_rubik_program(struct dla_processor_group *group);
+int
+dla_rubik_is_ready(struct dla_processor *processor,
+			     struct dla_processor_group *group);
+void
+dla_rubik_dump_config(struct dla_processor_group *group);
+void
+dla_rubik_rdma_check(struct dla_processor_group *group);
+
+#if STAT_ENABLE
+void
+dla_rubik_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group);
+void
+dla_rubik_dump_stat(struct dla_processor *processor);
+
+#else
+static inline void
+dla_rubik_stat_data(struct dla_processor *processor,
+				struct dla_processor_group *group) {}
+static inline void
+dla_rubik_dump_stat(struct dla_processor *processor) {}
+#endif
+
+#endif
diff --git a/drivers/nvdla/engine.c b/drivers/nvdla/engine.c
new file mode 100644
index 000000000000..5d2ca2702514
--- /dev/null
+++ b/drivers/nvdla/engine.c
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+#include "common.h"
+
+static const uint32_t map_rdma_ptr_addr[] = {
+	0xFFFFFFFF,
+	0xFFFFFFFF,
+	SDP_REG(RDMA_S_POINTER),
+	PDP_REG(RDMA_S_POINTER),
+	CDP_REG(RDMA_S_POINTER),
+	0xFFFFFFFF,
+};
+
+/*
+static const uint32_t map_sts_addr[] = {
+	BDMA_REG(STATUS),
+	CACC_REG(S_STATUS),
+	SDP_REG(S_STATUS),
+	PDP_REG(S_STATUS),
+	CDP_REG(S_STATUS),
+	RBK_REG(S_STATUS),
+};
+*/
+
+static const uint32_t map_ptr_addr[] = {
+	BDMA_REG(STATUS),
+	CACC_REG(S_POINTER),
+	SDP_REG(S_POINTER),
+	PDP_REG(S_POINTER),
+	CDP_REG(S_POINTER),
+	RBK_REG(S_POINTER),
+};
+
+int32_t dla_enable_intr(uint32_t mask)
+{
+	uint32_t reg = glb_reg_read(S_INTR_MASK);
+
+	reg = reg & (~mask);
+	glb_reg_write(S_INTR_MASK, reg);
+
+	RETURN(0);
+}
+
+int32_t dla_disable_intr(uint32_t mask)
+{
+	uint32_t reg = glb_reg_read(S_INTR_MASK);
+
+	reg = reg | mask;
+	glb_reg_write(S_INTR_MASK, reg);
+
+	RETURN(0);
+}
+
+/*
+uint8_t bdma_grp_sts[2] = {
+	FIELD_ENUM(BDMA_STATUS_0, IDLE, YES),
+	FIELD_ENUM(BDMA_STATUS_0, IDLE, YES)
+};
+*/
+
+struct dla_roi_desc roi_desc;
+
+/*
+ * Get DMA data cube address
+ */
+int32_t
+dla_get_dma_cube_address(void *driver_context, void *task_data,
+					int16_t index, uint32_t offset, void *dst_ptr,
+					uint32_t destination)
+{
+	int32_t ret = 0;
+	uint64_t *pdst = (uint64_t *)dst_ptr;
+       ret = dla_get_dma_address(driver_context, task_data, index,
+								dst_ptr, destination);
+	if (ret)
+		goto exit;
+
+	pdst[0] += offset;
+
+exit:
+	return ret;
+}
+
+/*
+ * Read input buffer address
+ *
+ * For input layer, in case of static ROI this address is read
+ * from address list and index is specified in data cube. In case
+ * dynamic ROI, it has to be read depending on ROI information
+ * and using surface address
+ *
+ * For all other layers, this address is read from address list
+ * using index specified in data cube
+ */
+int
+dla_read_input_address(struct dla_data_cube *data,
+		       uint64_t *address,
+		       int16_t op_index,
+		       uint8_t roi_index,
+		       uint8_t bpp)
+{
+	uint64_t roi_desc_addr;
+	int32_t ret = ERR(INVALID_INPUT);
+	struct dla_engine *en = dla_get_engine();
+
+	/*
+	 * If memory type is HW then no address required
+	 */
+	if (data->type == DLA_MEM_HW) {
+		ret = 0;
+		goto exit;
+	}
+
+	/*
+	 * If address list index is not -1 means this address has to
+	 * be read from address list
+	 */
+	if (data->address != -1) {
+
+		/*
+		 * But if other parameters indicate that this is input layer
+		 * for dynamic ROI then it is an error
+		 */
+		if (en->network->dynamic_roi &&
+			en->network->input_layer == op_index)
+			goto exit;
+		ret = dla_get_dma_cube_address(en->driver_context,
+						en->task->task_data,
+						data->address,
+						data->offset,
+						(void *)address,
+						DESTINATION_DMA);
+		goto exit;
+	}
+
+	/*
+	 * Check if it is dynamic ROI and this is input layer
+	 */
+	if (en->network->dynamic_roi && en->network->input_layer == op_index) {
+		if (!en->task->surface_addr)
+			goto exit;
+
+		/* Calculate address of ROI descriptor in array */
+		roi_desc_addr = en->task->roi_array_addr;
+
+		/* Read ROI descriptor */
+		ret = dla_data_read(en->driver_context,
+				en->task->task_data,
+				roi_desc_addr,
+				(void *)&roi_desc,
+				sizeof(roi_desc),
+				sizeof(struct dla_roi_array_desc) +
+				roi_index * sizeof(struct dla_roi_desc));
+		if (ret)
+			goto exit;
+
+		/* Calculate ROI address */
+		*address = en->task->surface_addr;
+		*address += (roi_desc.top * data->line_stride) +
+						(bpp * roi_desc.left);
+	}
+
+exit:
+	RETURN(ret);
+}
+
+int
+utils_get_free_group(struct dla_processor *processor,
+		     uint8_t *group_id,
+		     uint8_t *rdma_id)
+{
+	int32_t ret = 0;
+	uint32_t pointer;
+	uint32_t hw_consumer_ptr;
+	uint32_t hw_rdma_ptr;
+
+	hw_rdma_ptr = 0;
+
+	if (processor->op_type == DLA_OP_BDMA) {
+		pointer = reg_read(map_ptr_addr[processor->op_type]);
+		hw_consumer_ptr = ((pointer & MASK(BDMA_STATUS_0, GRP0_BUSY)) >>
+				SHIFT(BDMA_STATUS_0, GRP0_BUSY)) ==
+				FIELD_ENUM(BDMA_STATUS_0, GRP0_BUSY, YES) ?
+				1 : 0;
+	} else {
+		pointer = reg_read(map_ptr_addr[processor->op_type]);
+		hw_consumer_ptr = (pointer & MASK(CDP_S_POINTER_0, CONSUMER)) >>
+				SHIFT(CDP_S_POINTER_0, CONSUMER);
+
+		/*
+		 * Read current consumer pointer for RDMA only if processor
+		 * has RDMA module
+		 */
+		if (map_rdma_ptr_addr[processor->op_type] != 0xFFFFFFFF) {
+			pointer =
+			reg_read(map_rdma_ptr_addr[processor->op_type]);
+			hw_rdma_ptr = (pointer &
+					MASK(CDP_S_POINTER_0, CONSUMER)) >>
+					SHIFT(CDP_S_POINTER_0, CONSUMER);
+		}
+	}
+
+	/*
+	 * If both processors are programmed then exit
+	 */
+	if (processor->group_status == 0x3) {
+		ret = ERR(PROCESSOR_BUSY);
+		goto exit;
+	}
+
+	if (!processor->group_status)
+		/*
+		 * If both groups are idle then use consumer pointer
+		 */
+		*group_id = hw_consumer_ptr;
+	else
+		/*
+		 * Here it is assumed that only one group is idle or busy
+		 * and hence right shift will work to get correct
+		 * group id
+		 */
+		*group_id = !(processor->group_status >> 1);
+
+	/*
+	 * If both groups are idle then read group id from pointer
+	 */
+	if (!processor->rdma_status)
+		*rdma_id = hw_rdma_ptr;
+	else
+		*rdma_id = !(processor->rdma_status >> 1);
+
+exit:
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/engine_data.c b/drivers/nvdla/engine_data.c
new file mode 100644
index 000000000000..c967cffebb1a
--- /dev/null
+++ b/drivers/nvdla/engine_data.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <nvdla_interface.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+
+static union dla_operation_container operation_desc[DLA_OP_NUM][DLA_NUM_GROUPS];
+static union dla_surface_container surface_desc[DLA_OP_NUM][DLA_NUM_GROUPS];
+
+static struct dla_task global_task;
+
+static struct dla_engine engine = {
+	.processors[DLA_OP_BDMA] = {
+		.name = "BDMA",
+		.op_type = DLA_OP_BDMA,
+		.program = dla_bdma_program,
+		.enable = dla_bdma_enable,
+		.set_producer = dla_bdma_set_producer,
+		.is_ready = dla_bdma_is_ready,
+		.dump_config = dla_bdma_dump_config,
+		.rdma_check = dla_bdma_rdma_check,
+		.get_stat_data = dla_bdma_stat_data,
+		.dump_stat = dla_bdma_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_BDMA][0],
+			.surface_desc = &surface_desc[DLA_OP_BDMA][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_BDMA][1],
+			.surface_desc = &surface_desc[DLA_OP_BDMA][1],
+		},
+	},
+	.processors[DLA_OP_CONV] = {
+		.name = "Convolution",
+		.op_type = DLA_OP_CONV,
+		.program = dla_conv_program,
+		.enable = dla_conv_enable,
+		.set_producer = dla_conv_set_producer,
+		.is_ready = dla_conv_is_ready,
+		.dump_config = dla_conv_dump_config,
+		.rdma_check = dla_conv_rdma_check,
+		.get_stat_data = dla_conv_stat_data,
+		.dump_stat = dla_conv_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_CONV][0],
+			.surface_desc = &surface_desc[DLA_OP_CONV][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_CONV][1],
+			.surface_desc = &surface_desc[DLA_OP_CONV][1],
+		},
+	},
+	.processors[DLA_OP_SDP] = {
+		.name = "SDP",
+		.op_type = DLA_OP_SDP,
+		.program = dla_sdp_program,
+		.enable = dla_sdp_enable,
+		.set_producer = dla_sdp_set_producer,
+		.is_ready = dla_sdp_is_ready,
+		.dump_config = dla_sdp_dump_config,
+		.rdma_check = dla_sdp_rdma_check,
+		.get_stat_data = dla_sdp_stat_data,
+		.dump_stat = dla_sdp_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_SDP][0],
+			.surface_desc = &surface_desc[DLA_OP_SDP][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_SDP][1],
+			.surface_desc = &surface_desc[DLA_OP_SDP][1],
+		},
+	},
+	.processors[DLA_OP_PDP] = {
+		.name = "PDP",
+		.op_type = DLA_OP_PDP,
+		.program = dla_pdp_program,
+		.enable = dla_pdp_enable,
+		.set_producer = dla_pdp_set_producer,
+		.is_ready = dla_pdp_is_ready,
+		.dump_config = dla_pdp_dump_config,
+		.rdma_check = dla_pdp_rdma_check,
+		.get_stat_data = dla_pdp_stat_data,
+		.dump_stat = dla_pdp_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_PDP][0],
+			.surface_desc = &surface_desc[DLA_OP_PDP][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_PDP][1],
+			.surface_desc = &surface_desc[DLA_OP_PDP][1],
+		},
+	},
+	.processors[DLA_OP_CDP] = {
+		.name = "CDP",
+		.op_type = DLA_OP_CDP,
+		.program = dla_cdp_program,
+		.enable = dla_cdp_enable,
+		.set_producer = dla_cdp_set_producer,
+		.is_ready = dla_cdp_is_ready,
+		.dump_config = dla_cdp_dump_config,
+		.rdma_check = dla_cdp_rdma_check,
+		.get_stat_data = dla_cdp_stat_data,
+		.dump_stat = dla_cdp_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_CDP][0],
+			.surface_desc = &surface_desc[DLA_OP_CDP][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_CDP][1],
+			.surface_desc = &surface_desc[DLA_OP_CDP][1],
+		},
+	},
+
+	.processors[DLA_OP_RUBIK] = {
+		.name = "RUBIK",
+		.op_type = DLA_OP_RUBIK,
+		.program = dla_rubik_program,
+		.enable = dla_rubik_enable,
+		.set_producer = dla_rubik_set_producer,
+		.is_ready = dla_rubik_is_ready,
+		.dump_config = dla_rubik_dump_config,
+		.rdma_check = dla_rubik_rdma_check,
+		.get_stat_data = dla_rubik_stat_data,
+		.dump_stat = dla_rubik_dump_stat,
+		.consumer_ptr = 0,
+		.roi_index = 0,
+		.group_status = 0,
+		.rdma_status = 0,
+		.last_group = 1,
+		.groups[0] = {
+			.id = 0,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_RUBIK][0],
+			.surface_desc = &surface_desc[DLA_OP_RUBIK][0],
+		},
+		.groups[1] = {
+			.id = 1,
+			.rdma_id = 0,
+			.active = 0,
+			.events = 0,
+			.roi_index = 0,
+			.is_rdma_needed = 0,
+			.lut_index = -1,
+			.operation_desc = &operation_desc[DLA_OP_RUBIK][1],
+			.surface_desc = &surface_desc[DLA_OP_RUBIK][1],
+		},
+	},
+
+};
+
+struct dla_engine *dla_get_engine(void)
+{
+	return &engine;
+}
+
+int32_t dla_register_driver(void **engine_context, void *driver_context)
+{
+	*engine_context = &engine;
+	engine.task = &global_task;
+	engine.driver_context = driver_context;
+	engine.task->task_data = NULL;
+
+	dla_init_op_cache(&engine);
+
+	RETURN(0);
+}
+
+uint32_t reg_read(uint32_t addr)
+{
+	return dla_reg_read(engine.driver_context, addr);
+}
+
+void reg_write(uint32_t addr, uint32_t reg)
+{
+	dla_reg_write(engine.driver_context, addr, reg);
+}
diff --git a/drivers/nvdla/engine_debug.c b/drivers/nvdla/engine_debug.c
new file mode 100644
index 000000000000..7ed4f0aebc6c
--- /dev/null
+++ b/drivers/nvdla/engine_debug.c
@@ -0,0 +1,551 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dla_debug.h>
+#include <dla_interface.h>
+#include <dla_sched.h>
+
+#include "engine_debug.h"
+
+#if DEBUG_NETWORK_DATA
+
+void
+dla_debug_network_desc(struct dla_network_desc *nd)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW dla_network_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("op desc index      = %d\n", nd->operation_desc_index);
+	dla_debug("surface desc index = %d\n", nd->surface_desc_index);
+	dla_debug("dep graph index    = %d\n", nd->dependency_graph_index);
+	dla_debug("lut data index     = %d\n", nd->lut_data_index);
+	dla_debug("stat_list_index    = %d\n", nd->stat_list_index);
+	dla_debug("roi array index    = %d\n", nd->roi_array_index);
+	dla_debug("surface index      = %d\n", nd->surface_index);
+	dla_debug("num rois           = %u\n", nd->num_rois);
+	dla_debug("num ops            = %u\n", nd->num_operations);
+	dla_debug("num luts           = %u\n", nd->num_luts);
+	dla_debug("num addr           = %u\n", nd->num_addresses);
+	dla_debug("input layer        = %u\n", nd->input_layer);
+	dla_debug("dynamic roi        = %u\n", nd->dynamic_roi);
+}
+
+static void
+dla_debug_bdma_transfer(struct dla_bdma_transfer_desc *tr, int32_t id)
+{
+	dla_debug("transfer[%d]            = [ dla_bdma_transfer_desc =>\n", id);
+	dla_debug("    source_address      = %x\n", tr->source_address);
+	dla_debug("    destination_address = %x\n", tr->destination_address);
+	dla_debug("    line_size           = %x\n", tr->line_size);
+	dla_debug("    line_repeat         = %x\n", tr->line_repeat);
+	dla_debug("    source_line         = %x\n", tr->source_line);
+	dla_debug("    destination_line    = %x\n", tr->destination_line);
+	dla_debug("    surface_repeat      = %x\n", tr->surface_repeat);
+	dla_debug("    source_surface      = %x\n", tr->source_surface);
+	dla_debug("    destination_surface = %x\n", tr->destination_surface);
+}
+
+void
+dla_debug_bdma_surface_desc(struct dla_bdma_surface_desc *desc, int32_t roi)
+{
+	int32_t i;
+
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_bdma_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("source_type      = %u\n", desc->source_type);
+	dla_debug("destination_type = %u\n", desc->destination_type);
+	dla_debug("num_transfers    = %u\n", desc->num_transfers);
+	for (i = 0; i < desc->num_transfers; i++)
+		dla_debug_bdma_transfer(&desc->transfers[i], i);
+}
+
+void
+dla_debug_bdma_op_desc(struct dla_bdma_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_bdma_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("num_transfers    = %u\n", desc->num_transfers);
+}
+
+void
+dla_debug_address_info(struct dla_task *tk)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW address list\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("task base address        = %llu\n", tk->base);
+	dla_debug("op desc address          = %llu\n", tk->operation_desc_addr);
+	dla_debug("surface desc address     = %llu\n", tk->surface_desc_addr);
+	dla_debug("dependency graph address = %llu\n", tk->dependency_graph_addr);
+	dla_debug("LUT data address         = %llu\n", tk->lut_data_addr);
+	dla_debug("stat address             = %llu\n", tk->stat_data_addr);
+	dla_debug("ROI array address        = %llu\n", tk->roi_array_addr);
+	dla_debug("surface address          = %llu\n", tk->surface_addr);
+}
+
+void
+dla_debug_op_desc(struct dla_common_op_desc *desc, int32_t roi)
+{
+	int32_t i;
+
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_common_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("[%p] Operation index %d ROI %d dep_count %d type %d\n",
+			(unsigned int *)desc, desc->index, desc->roi_index,
+			desc->dependency_count, desc->op_type);
+	dla_debug("consumers = [ dla_consumer =>\n");
+	for (i = 0; i < DLA_OP_NUM; i++)
+		dla_debug(" [ %d %d ]", desc->consumers[i].index,
+					desc->consumers[i].event);
+	dla_debug("]");
+	dla_debug("fused_parent = [ dla_consumer =>\n");
+	dla_debug(" [ %d %d ]", desc->fused_parent.index,
+					desc->fused_parent.event);
+	dla_debug("]");
+}
+
+static void
+dla_debug_data_cube(struct dla_data_cube *cube)
+{
+	dla_debug("    type          = %u\n", cube->type);
+	dla_debug("    address       = %d\n", cube->address);
+	dla_debug("    width         = %x\n", cube->width);
+	dla_debug("    height        = %x\n", cube->height);
+	dla_debug("    channel       = %x\n", cube->channel);
+	dla_debug("    size          = %u\n", cube->size);
+	dla_debug("    line_stride   = %u\n", cube->line_stride);
+	dla_debug("    surf_stride   = %u\n", cube->surf_stride);
+	dla_debug("    plane_stride  = %u\n", cube->plane_stride);
+	dla_debug("]");
+}
+
+static void
+dla_debug_converter(struct dla_cvt_param *cvt)
+{
+	dla_debug("[ scale = %d, truncate = %u, enable = %u, offset = %d ]\n",
+			cvt->scale, cvt->truncate, cvt->enable, cvt->offset);
+}
+
+static void
+dla_debug_float_data(struct dla_float_data *float_data)
+{
+	dla_debug("[ scale = %d, shifter = %d ]\n",
+			float_data->scale, float_data->shifter);
+}
+
+static void
+dla_debug_dla_slope(union dla_slope *slope)
+{
+	dla_debug("    data_i =\n");
+	dla_debug_float_data(&slope->data_i);
+	dla_debug("    data_f = %u\n", slope->data_f);
+}
+
+static void
+dla_debug_lut_offset(union dla_lut_offset *offset)
+{
+	dla_debug("    exp_offset = %d\n", offset->exp_offset);
+	dla_debug("    frac_bits  = %d\n", offset->frac_bits);
+}
+
+void
+dla_debug_lut_params(struct dla_lut_param *lut_param)
+{
+	int32_t i, j;
+
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW dla_lut_param\n");
+	dla_debug("---------------------------------------------------------\n");
+
+	dla_debug("linear_exp_table            = [\n");
+	for (i = 0; i < (1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1; i++)
+		dla_debug(" %u", lut_param->linear_exp_table[i]);
+	dla_debug("]");
+
+	dla_debug("linear_only_table           = [\n");
+	for (j = 0; j < (1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1; j++)
+		dla_debug(" %u\n", lut_param->linear_only_table[j]);
+	dla_debug("]\n");
+
+	dla_debug("linear_exp_offset           =\n");
+	dla_debug_lut_offset(&lut_param->linear_exp_offset);
+	dla_debug("linear_only_offset          =\n");
+	dla_debug_lut_offset(&lut_param->linear_only_offset);
+	dla_debug("linear_exp_start            = %llu\n",
+				lut_param->linear_exp_start);
+	dla_debug("linear_exp_end            = %llu\n",
+				lut_param->linear_exp_end);
+	dla_debug("linear_only_start           = %llu\n",
+				lut_param->linear_only_start);
+	dla_debug("linear_only_end           = %llu\n",
+				lut_param->linear_only_end);
+	dla_debug("linear_exp_underflow_slope  =\n");
+	dla_debug_dla_slope(&lut_param->linear_exp_underflow_slope);
+	dla_debug("linear_exp_overflow_slope   =\n");
+	dla_debug_dla_slope(&lut_param->linear_exp_overflow_slope);
+	dla_debug("linear_only_underflow_slope =\n");
+	dla_debug_dla_slope(&lut_param->linear_only_underflow_slope);
+	dla_debug("linear_only_overflow_slope  =\n");
+	dla_debug_dla_slope(&lut_param->linear_only_overflow_slope);
+	dla_debug("hybrid_priority             = %u\n",
+				lut_param->hybrid_priority);
+	dla_debug("underflow_priority          = %u\n",
+				lut_param->underflow_priority);
+	dla_debug("overflow_priority           = %u\n",
+				lut_param->overflow_priority);
+	dla_debug("method                      = %u\n",
+				lut_param->method);
+}
+
+void
+dla_debug_bdma_stats(struct dla_bdma_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_bdma_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("read_stall   = %u\n", stat->read_stall);
+	dla_debug("write_stall  = %u\n", stat->write_stall);
+	dla_debug("runtime      = %u\n", stat->runtime);
+}
+
+void
+dla_debug_conv_surface_desc(struct dla_conv_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_conv_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("weight_data         = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->weight_data);
+	dla_debug("wmb_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->wmb_data);
+	dla_debug("wgs_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->wgs_data);
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+	dla_debug("offset_u            = %lld\n", desc->offset_u);
+	dla_debug("in_line_uv_stride   = %u\n", desc->in_line_uv_stride);
+}
+
+void
+dla_debug_conv_op_desc(struct dla_conv_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_conv_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("conv_mode          = %u\n", desc->conv_mode);
+	dla_debug("data_reuse         = %u\n", desc->data_reuse);
+	dla_debug("weight_reuse       = %u\n", desc->weight_reuse);
+	dla_debug("skip_data_rls      = %u\n", desc->skip_data_rls);
+	dla_debug("skip_weight_rls    = %u\n", desc->skip_weight_rls);
+	dla_debug("entry_per_slice    = %u\n", desc->entry_per_slice);
+	dla_debug("data_format        = %u\n", desc->data_format);
+	dla_debug("pixel_mapping      = %u\n", desc->pixel_mapping);
+	dla_debug("fetch_grain        = %u\n", desc->fetch_grain);
+	dla_debug("batch              = %u\n", desc->batch);
+	dla_debug("weight_format      = %u\n", desc->weight_format);
+	dla_debug("data_bank          = %u\n", desc->data_bank);
+	dla_debug("weight_bank        = %u\n", desc->weight_bank);
+	dla_debug("batch_stride       = %u\n", desc->batch_stride);
+	dla_debug("post_extension     = %u\n", desc->post_extension);
+	dla_debug("pixel_override     = %u\n", desc->pixel_override);
+	dla_debug("release            = %u\n", desc->release);
+	dla_debug("input_width_csc    = %u\n", desc->input_width_csc);
+	dla_debug("input_height_csc   = %u\n", desc->input_height_csc);
+	dla_debug("input_channel_csc  = %u\n", desc->input_channel_csc);
+	dla_debug("kernel_width_csc   = %u\n", desc->kernel_width_csc);
+	dla_debug("kernel_height_csc  = %u\n", desc->kernel_height_csc);
+	dla_debug("kernel_channel_csc = %u\n", desc->kernel_channel_csc);
+	dla_debug("input_width_cmac   = %u\n", desc->input_width_cmac);
+	dla_debug("input_height_cmac  = %u\n", desc->input_height_cmac);
+	dla_debug("bytes_per_kernel   = %u\n", desc->bytes_per_kernel);
+	dla_debug("mean_ry            = %d\n", desc->mean_ry);
+	dla_debug("mean_gu            = %d\n", desc->mean_gu);
+	dla_debug("mean_bv            = %d\n", desc->mean_bv);
+	dla_debug("mean_ax            = %d\n", desc->mean_ax);
+	dla_debug("mean_format        = %u\n", desc->mean_format);
+	dla_debug("conv_stride_x      = %u\n", desc->conv_stride_x);
+	dla_debug("conv_stride_y      = %u\n", desc->conv_stride_y);
+	dla_debug("pad_x_left         = %u\n", desc->pad_x_left);
+	dla_debug("pad_x_right        = %u\n", desc->pad_x_right);
+	dla_debug("pad_y_top          = %u\n", desc->pad_y_top);
+	dla_debug("pad_y_bottom       = %u\n", desc->pad_y_bottom);
+	dla_debug("dilation_x         = %u\n", desc->dilation_x);
+	dla_debug("dilation_y         = %u\n", desc->dilation_y);
+	dla_debug("pra_truncate       = %u\n", desc->pra_truncate);
+	dla_debug("in_precision       = %u\n", desc->in_precision);
+	dla_debug("out_precision      = %u\n", desc->out_precision);
+	dla_debug("pad_val            = %d\n", desc->pad_val);
+	dla_debug("in_cvt             =\n");
+	dla_debug_converter(&desc->in_cvt);
+	dla_debug("out_cvt            =\n");
+	dla_debug_converter(&desc->out_cvt);
+}
+
+void
+dla_debug_conv_stats(struct dla_conv_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_conv_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("data_read_stall      = %u\n", stat->data_read_stall);
+	dla_debug("weight_read_stall    = %u\n", stat->weight_read_stall);
+	dla_debug("data_read_latency    = %u\n", stat->data_read_latency);
+	dla_debug("weight_read_latency  = %u\n", stat->weight_read_latency);
+	dla_debug("saturation_count     = %u\n", stat->saturation_count);
+	dla_debug("nan_data_num         = %u\n", stat->nan_data_num);
+	dla_debug("nan_weight_num       = %u\n", stat->nan_weight_num);
+	dla_debug("inf_data_num         = %u\n", stat->inf_data_num);
+	dla_debug("inf_weight_num       = %u\n", stat->inf_weight_num);
+	dla_debug("runtime              = %u\n", stat->runtime);
+}
+
+void
+dla_debug_pdp_surface_desc(struct dla_pdp_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_pdp_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+}
+
+void
+dla_debug_pdp_op_desc(struct dla_pdp_op_desc *desc, int32_t roi)
+{
+	int32_t i;
+
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_pdp_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("precision               = %u\n", desc->precision);
+	dla_debug("padding_value           = [\n");
+	for (i = 0; i < PDP_PAD_VAL_NUM; i++)
+		dla_debug(" %d\n", desc->padding_value[i]);
+	dla_debug("]\n");
+	dla_debug("split_num               = %u\n", desc->split_num);
+	dla_debug("partial_in_width_first  = %u\n",
+					desc->partial_in_width_first);
+	dla_debug("partial_in_width_mid    = %u\n", desc->partial_in_width_mid);
+	dla_debug("partial_in_width_last   = %u\n", desc->partial_in_width_last);
+	dla_debug("partial_width_first     = %u\n", desc->partial_width_first);
+	dla_debug("partial_width_mid       = %u\n", desc->partial_width_mid);
+	dla_debug("partial_width_last      = %u\n", desc->partial_width_last);
+	dla_debug("pool_mode               = %u\n", desc->pool_mode);
+	dla_debug("pool_width              = %u\n", desc->pool_width);
+	dla_debug("pool_height             = %u\n", desc->pool_height);
+	dla_debug("stride_x                = %u\n", desc->stride_x);
+	dla_debug("stride_y                = %u\n", desc->stride_y);
+	dla_debug("pad_left                = %u\n", desc->pad_left);
+	dla_debug("pad_right               = %u\n", desc->pad_right);
+	dla_debug("pad_top                 = %u\n", desc->pad_top);
+	dla_debug("pad_bottom              = %u\n", desc->pad_bottom);
+}
+
+void
+dla_debug_pdp_stats(struct dla_pdp_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_pdp_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("inf_input_num   = %u\n", stat->inf_input_num);
+	dla_debug("nan_input_num   = %u\n", stat->nan_input_num);
+	dla_debug("nan_output_num  = %u\n", stat->nan_output_num);
+	dla_debug("write_stall     = %u\n", stat->write_stall);
+	dla_debug("runtime         = %u\n", stat->runtime);
+}
+
+void
+dla_debug_cdp_surface_desc(struct dla_cdp_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_cdp_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+}
+
+void
+dla_debug_cdp_op_desc(struct dla_cdp_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_cdp_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("in_precision      = %u\n", desc->in_precision);
+	dla_debug("out_precision     = %u\n", desc->out_precision);
+	dla_debug("lut_index         = %d\n", desc->lut_index);
+	dla_debug("in_cvt             =\n");
+	dla_debug_converter(&desc->in_cvt);
+	dla_debug("out_cvt             =\n");
+	dla_debug_converter(&desc->out_cvt);
+	dla_debug("local_size        = %u\n", desc->local_size);
+	dla_debug("bypass_sqsum      = %u\n", desc->bypass_sqsum);
+	dla_debug("bypass_out_mul    = %u\n", desc->bypass_out_mul);
+}
+
+void
+dla_debug_cdp_stats(struct dla_cdp_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_cdp_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("nan_input_num     = %u\n", stat->nan_input_num);
+	dla_debug("inf_input_num     = %u\n", stat->inf_input_num);
+	dla_debug("nan_output_num    = %u\n", stat->nan_output_num);
+	dla_debug("write_stall       = %u\n", stat->write_stall);
+	dla_debug("lut_uflow         = %u\n", stat->lut_uflow);
+	dla_debug("lut_oflow         = %u\n", stat->lut_oflow);
+	dla_debug("lut_hybrid        = %u\n", stat->lut_hybrid);
+	dla_debug("lut_le_hit        = %u\n", stat->lut_le_hit);
+	dla_debug("lut_lo_hit        = %u\n", stat->lut_lo_hit);
+	dla_debug("saturation_count  = %u\n", stat->saturation_count);
+	dla_debug("runtime           = %u\n", stat->runtime);
+}
+
+void
+dla_debug_rubik_surface_desc(struct dla_rubik_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_rubik_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+}
+
+void
+dla_debug_rubik_op_desc(struct dla_rubik_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_rubik_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("mode       = %u\n", desc->mode);
+	dla_debug("precision  = %u\n", desc->precision);
+	dla_debug("stride_x   = %u\n", desc->stride_x);
+	dla_debug("stride_y   = %u\n", desc->stride_y);
+}
+
+void
+dla_debug_rubik_stats(struct dla_rubik_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_rubik_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("read_stall   = %u\n", stat->read_stall);
+	dla_debug("write_stall  = %u\n", stat->write_stall);
+	dla_debug("runtime      = %u\n", stat->runtime);
+}
+
+static void
+dla_debug_sdp_op(struct dla_sdp_op *sdp_op)
+{
+	dla_debug("    enable         = %u\n", sdp_op->enable);
+	dla_debug("    alu_type       = %u\n", sdp_op->alu_type);
+	dla_debug("    type           = %u\n", sdp_op->type);
+	dla_debug("    mode           = %u\n", sdp_op->mode);
+	dla_debug("    act            = %u\n", sdp_op->act);
+	dla_debug("    shift_value    = %u\n", sdp_op->shift_value);
+	dla_debug("    truncate       = %u\n", sdp_op->truncate);
+	dla_debug("    precision      = %u\n", sdp_op->precision);
+	dla_debug("    alu_operand    = %d\n", sdp_op->alu_operand);
+	dla_debug("    mul_operand    = %d\n", sdp_op->mul_operand);
+	dla_debug("cvt.alu_cvt          =\n");
+	dla_debug_converter(&sdp_op->cvt.alu_cvt);
+	dla_debug("cvt.mul_cvt          =\n");
+	dla_debug_converter(&sdp_op->cvt.mul_cvt);
+	dla_debug("]\n");
+}
+
+void
+dla_debug_sdp_surface_desc(struct dla_sdp_surface_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_sdp_surface_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->src_data);
+	dla_debug("x1_data             = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->x1_data);
+	dla_debug("x2_data             = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->x2_data);
+	dla_debug("y_data              = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->y_data);
+	dla_debug("dst_data            = [ dla_data_cube =>\n");
+	dla_debug_data_cube(&desc->dst_data);
+}
+
+void
+dla_debug_sdp_op_desc(struct dla_sdp_op_desc *desc, int32_t roi)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW ROI[%d]: dla_sdp_op_desc\n", roi);
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("src_precision    = %u\n", desc->src_precision);
+	dla_debug("dst_precision    = %u\n", desc->dst_precision);
+	dla_debug("lut_index        = %d\n", desc->lut_index);
+	dla_debug("out_cvt          =\n");
+	dla_debug_converter(&desc->out_cvt);
+	dla_debug("conv_mode        = %u\n", desc->conv_mode);
+	dla_debug("batch_num        = %u\n", desc->batch_num);
+	dla_debug("batch_stride     = %u\n", desc->batch_stride);
+	dla_debug("x1_op            = [ dla_sdp_op =>\n");
+	dla_debug_sdp_op(&desc->x1_op);
+	dla_debug("x2_op            = [ dla_sdp_op =>\n");
+	dla_debug_sdp_op(&desc->x2_op);
+	dla_debug("y_op             = [ dla_sdp_op =>\n");
+	dla_debug_sdp_op(&desc->y_op);
+}
+
+void
+dla_debug_sdp_stats(struct dla_sdp_stat_desc *stat)
+{
+	dla_debug("*********************************************************\n");
+	dla_debug("NVDLA FW STATS: dla_sdp_stat_desc\n");
+	dla_debug("---------------------------------------------------------\n");
+	dla_debug("nan_input_num     = %u\n", stat->nan_input_num);
+	dla_debug("inf_input_num     = %u\n", stat->inf_input_num);
+	dla_debug("nan_output_num    = %u\n", stat->nan_output_num);
+	dla_debug("wdma_write_stall  = %u\n", stat->wdma_write_stall);
+	dla_debug("lut_underflow     = %u\n", stat->lut_underflow);
+	dla_debug("lut_overflow      = %u\n", stat->lut_overflow);
+	dla_debug("lut_hybrid        = %u\n", stat->lut_hybrid);
+	dla_debug("lut_le_hit        = %u\n", stat->lut_le_hit);
+	dla_debug("lut_lo_hit        = %u\n", stat->lut_lo_hit);
+	dla_debug("saturation_count  = %u\n", stat->saturation_count);
+	dla_debug("runtime           = %u\n", stat->runtime);
+}
+#endif /* DEBUG_NETWORK_DATA */
diff --git a/drivers/nvdla/engine_debug.h b/drivers/nvdla/engine_debug.h
new file mode 100644
index 000000000000..d953fc4c2a91
--- /dev/null
+++ b/drivers/nvdla/engine_debug.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_ENGINE_DEBUG_H_
+#define __FIRMWARE_ENGINE_DEBUG_H_
+
+#include <dla_debug.h>
+#include <dla_interface.h>
+
+#if DEBUG_NETWORK_DATA
+void
+dla_debug_op_desc(struct dla_common_op_desc *desc, int32_t roi);
+void
+dla_debug_network_desc(struct dla_network_desc *network_desc);
+void
+dla_debug_address_info(struct dla_task *task);
+void
+dla_debug_bdma_surface_desc(struct dla_bdma_surface_desc *desc, int32_t roi);
+void
+dla_debug_bdma_op_desc(struct dla_bdma_op_desc *desc, int32_t roi);
+void
+dla_debug_bdma_stats(struct dla_bdma_stat_desc *stat);
+void
+dla_debug_conv_surface_desc(struct dla_conv_surface_desc *desc, int32_t roi);
+void
+dla_debug_conv_op_desc(struct dla_conv_op_desc *desc, int32_t roi);
+void
+dla_debug_conv_stats(struct dla_conv_stat_desc *stat);
+void
+dla_debug_sdp_op_desc(struct dla_sdp_op_desc *desc, int32_t roi);
+void
+dla_debug_sdp_surface_desc(struct dla_sdp_surface_desc *desc, int32_t roi);
+void
+dla_debug_sdp_stats(struct dla_sdp_stat_desc *stat);
+void
+dla_debug_pdp_surface_desc(struct dla_pdp_surface_desc *desc, int32_t roi);
+void
+dla_debug_pdp_op_desc(struct dla_pdp_op_desc *desc, int32_t roi);
+void
+dla_debug_pdp_stats(struct dla_pdp_stat_desc *stat);
+void
+dla_debug_cdp_surface_desc(struct dla_cdp_surface_desc *desc, int32_t roi);
+void
+dla_debug_cdp_op_desc(struct dla_cdp_op_desc *desc, int32_t roi);
+void
+dla_debug_cdp_stats(struct dla_cdp_stat_desc *stat);
+void
+dla_debug_rubik_op_desc(struct dla_rubik_op_desc *desc, int32_t roi);
+void
+dla_debug_rubik_surface_desc(struct dla_rubik_surface_desc *desc, int32_t roi);
+void
+dla_debug_rubik_stats(struct dla_rubik_stat_desc *stat);
+void
+dla_debug_lut_params(struct dla_lut_param *lut_param);
+
+#else
+
+static inline void
+dla_debug_op_desc(struct dla_common_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_network_desc(struct dla_network_desc *network_desc) {}
+static inline void
+dla_debug_address_info(struct dla_task *task) {}
+static inline void
+dla_debug_bdma_surface_desc(struct dla_bdma_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_bdma_op_desc(struct dla_bdma_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_bdma_stats(struct dla_bdma_stat_desc *stat) {}
+static inline void
+dla_debug_conv_surface_desc(struct dla_conv_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_conv_op_desc(struct dla_conv_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_conv_stats(struct dla_conv_stat_desc *stat) {}
+static inline void
+dla_debug_sdp_op_desc(struct dla_sdp_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_sdp_surface_desc(struct dla_sdp_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_sdp_stats(struct dla_sdp_stat_desc *stat) {}
+static inline void
+dla_debug_pdp_surface_desc(struct dla_pdp_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_pdp_op_desc(struct dla_pdp_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_pdp_stats(struct dla_pdp_stat_desc *stat) {}
+static inline void
+dla_debug_cdp_surface_desc(struct dla_cdp_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_cdp_op_desc(struct dla_cdp_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_cdp_stats(struct dla_cdp_stat_desc *stat) {}
+static inline void
+dla_debug_rubik_op_desc(struct dla_rubik_op_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_rubik_surface_desc(struct dla_rubik_surface_desc *desc, int32_t roi) {}
+static inline void
+dla_debug_rubik_stats(struct dla_rubik_stat_desc *stat) {}
+static inline void
+dla_debug_lut_params(struct dla_lut_param *lut_param) {}
+
+#endif /* DEBUG_NETWORK_DATA */
+#endif /* __FIRMWARE_ENGINE_DEBUG_H_ */
diff --git a/drivers/nvdla/engine_isr.c b/drivers/nvdla/engine_isr.c
new file mode 100644
index 000000000000..19ae2dd907e4
--- /dev/null
+++ b/drivers/nvdla/engine_isr.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_engine.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+
+int32_t dla_isr_handler(void *engine_data)
+{
+	uint32_t __maybe_unused mask;
+	uint32_t reg;
+	struct dla_processor *processor = NULL;
+	struct dla_processor_group *group;
+	struct dla_engine *engine = (struct dla_engine *)engine_data;
+
+	mask = glb_reg_read(S_INTR_MASK);
+	reg = glb_reg_read(S_INTR_STATUS);
+
+	dla_trace("Enter: dla_isr_handler, reg:%x, mask:%x\n", reg, mask);
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CACC_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CACC_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, SDP_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_SDP];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, SDP_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_SDP];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDP_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_CDP];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDP_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_CDP];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, RUBIK_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_RUBIK];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, RUBIK_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_RUBIK];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, PDP_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_PDP];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, PDP_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_PDP];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, BDMA_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_BDMA];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, BDMA_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_BDMA];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_OP_COMPLETED);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_DAT_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_CDMA_DT_DONE);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_DAT_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_CDMA_DT_DONE);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_WT_DONE_STATUS0)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[0];
+		group->events |= (1 << DLA_EVENT_CDMA_WT_DONE);
+	}
+	if (reg & MASK(GLB_S_INTR_STATUS_0, CDMA_WT_DONE_STATUS1)) {
+		processor = &engine->processors[DLA_OP_CONV];
+		group = &processor->groups[1];
+		group->events |= (1 << DLA_EVENT_CDMA_WT_DONE);
+	}
+
+	glb_reg_write(S_INTR_STATUS, reg);
+
+	mask = glb_reg_read(S_INTR_MASK);
+	reg = glb_reg_read(S_INTR_STATUS);
+
+	dla_trace("Exit: dla_isr_handler, reg:%x, mask:%x\n", reg, mask);
+	RETURN(0);
+}
diff --git a/drivers/nvdla/include/dla_debug.h b/drivers/nvdla/include/dla_debug.h
new file mode 100644
index 000000000000..bef99d620789
--- /dev/null
+++ b/drivers/nvdla/include/dla_debug.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_DLA_DEBUG_H_
+#define __FIRMWARE_DLA_DEBUG_H_
+
+#define STRINGIFY(s) #s
+#define DEFER_STRINGIFY(s) STRINGIFY(s)
+#define FILELINE DEFER_STRINGIFY(__LINE__)
+#define FILENAME DEFER_STRINGIFY(__FILE__)
+
+#define LOG_EVENT_BDMA_SHIFT		0U
+#define LOG_EVENT_CONV_SHIFT		4U
+#define LOG_EVENT_SDP_SHIFT		8U
+#define LOG_EVENT_PDP_SHIFT		12U
+#define LOG_EVENT_CDP_SHIFT		16U
+#define LOG_EVENT_RBK_SHIFT		20U
+#define LOG_EVENT_GROUP_SHIFT		24U
+#define LOG_EVENT_ROI_SHIFT		28U
+
+#define LOG_TASK_START			1
+#define LOG_TASK_END			2
+#define LOG_READ_OP_CONFIG_START	3
+#define LOG_READ_OP_CONFIG_END		4
+#define LOG_READ_SURF_CONFIG_START	5
+#define LOG_READ_SURF_CONFIG_END	6
+#define LOG_PROGRAM_START		7
+#define LOG_PROGRAM_END			8
+#define LOG_OPERATION_START		9
+#define LOG_OPERATION_END		10
+
+#define LOG_EVENT(roi, group, processor, event)
+
+/**
+ * Used to enable/disable reading stat registers
+ */
+#define STAT_ENABLE		1
+
+/**
+ * Used to print debug network data
+ */
+#define DEBUG_NETWORK_DATA		0
+
+#define pr_dump_stack(format, ...)
+#define dla_trace(format, ...)
+
+#define assert(condition)
+
+#define RETURN(err) { return (err); }
+
+#define DEBUG_ASSERT
+
+#ifdef DEBUG_ASSERT
+#define ASSERT_GOTO(_condition, _ret, _err_value, _goto)	\
+do {								\
+	if (!(_condition)) {					\
+		dla_error("Assertion Fail(" FILENAME FILELINE "):" \
+					STRINGIFY(_condition));	\
+		_ret = _err_value;				\
+		goto _goto;					\
+	} else {						\
+		_ret = 0;					\
+	}							\
+} while (0)
+#else
+#define ASSERT_GOTO(_condition, _ret, _err_value, _goto) assert(condition)
+#endif /* DEBUG_ASSERT */
+
+#endif
diff --git a/drivers/nvdla/include/dla_engine.h b/drivers/nvdla/include/dla_engine.h
new file mode 100644
index 000000000000..707adc41d5d4
--- /dev/null
+++ b/drivers/nvdla/include/dla_engine.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DLA_ENGINE_H_
+#define __DLA_ENGINE_H_
+
+#include <dla_interface.h>
+#include <dla_sched.h>
+
+struct dla_processor_group {
+	uint8_t id;
+	uint8_t rdma_id;
+	uint8_t active;
+	uint8_t events;
+	uint8_t roi_index;
+	uint8_t is_rdma_needed;
+	uint8_t pending;
+	int32_t lut_index;
+	uint8_t programming;
+	uint64_t start_time;
+
+	struct dla_common_op_desc *op_desc;
+	struct dla_common_op_desc *consumers[DLA_OP_NUM];
+	struct dla_common_op_desc *fused_parent;
+	union dla_operation_container *operation_desc;
+	union dla_surface_container *surface_desc;
+};
+
+struct dla_processor {
+	const char *name;
+	uint8_t op_type;
+	uint8_t consumer_ptr;
+	uint8_t roi_index;
+	uint8_t group_status;
+	uint8_t rdma_status;
+	uint8_t last_group;
+
+	struct dla_common_op_desc *tail_op;
+	struct dla_processor_group groups[DLA_NUM_GROUPS];
+	union dla_stat_container *stat_data_desc;
+
+	int32_t (*is_ready)(struct dla_processor *processor,
+				  struct dla_processor_group *group);
+	int32_t (*enable)(struct dla_processor_group *group);
+	int32_t (*program)(struct dla_processor_group *group);
+	void (*set_producer)(int32_t group_id, int32_t rdma_id);
+	void (*dump_config)(struct dla_processor_group *group);
+	void (*rdma_check)(struct dla_processor_group *group);
+	void (*get_stat_data)(struct dla_processor *processor,
+				struct dla_processor_group *group);
+	void (*dump_stat)(struct dla_processor *processor);
+};
+
+struct dla_engine {
+	struct dla_task *task;
+	struct dla_config *config_data;
+	struct dla_network_desc *network;
+	struct dla_processor processors[DLA_OP_NUM];
+
+	uint16_t num_proc_hwl;
+	int32_t status;
+	uint32_t stat_enable;
+
+	void *driver_context;
+};
+
+struct dla_engine *dla_get_engine(void);
+
+#endif
diff --git a/drivers/nvdla/include/dla_err.h b/drivers/nvdla/include/dla_err.h
new file mode 100644
index 000000000000..d9efcd08d8f7
--- /dev/null
+++ b/drivers/nvdla/include/dla_err.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_DLA_ERR_H_
+#define __FIRMWARE_DLA_ERR_H_
+
+#define ERR(code) -DLA_ERR_##code
+
+#define DLA_ERR_NONE			0
+#define DLA_ERR_INVALID_METHOD		1
+#define DLA_ERR_INVALID_TASK		2
+#define DLA_ERR_INVALID_INPUT		3
+#define DLA_ERR_INVALID_FALC_DMA	4
+#define DLA_ERR_INVALID_QUEUE		5
+#define DLA_ERR_INVALID_PREACTION	6
+#define DLA_ERR_INVALID_POSTACTION	7
+#define DLA_ERR_NO_MEM			8
+#define DLA_ERR_INVALID_DESC_VER	9
+#define DLA_ERR_INVALID_ENGINE_ID	10
+#define DLA_ERR_INVALID_REGION		11
+#define DLA_ERR_PROCESSOR_BUSY		12
+#define DLA_ERR_RETRY			13
+#define DLA_ERR_TASK_STATUS_MISMATCH	14
+
+#endif
diff --git a/drivers/nvdla/include/dla_interface.h b/drivers/nvdla/include/dla_interface.h
new file mode 100644
index 000000000000..cbf4791bd909
--- /dev/null
+++ b/drivers/nvdla/include/dla_interface.h
@@ -0,0 +1,886 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FIRMWARE_DLA_INTERFACE_H_
+#define __FIRMWARE_DLA_INTERFACE_H_
+
+#include <nvdla_interface.h>
+
+/**
+ * @ingroup Processors
+ * @name DLA Processors
+ * Processor modules in DLA engine. Each processor has it's
+ * own operation a.k.a. HW layer. Network is formed using
+ * graph of these operations
+ * @{
+ */
+#define DLA_OP_BDMA		0
+#define DLA_OP_CONV		1
+#define DLA_OP_SDP		2
+#define DLA_OP_PDP		3
+#define DLA_OP_CDP		4
+#define DLA_OP_RUBIK		5
+/** @} */
+
+/**
+ * @ingroup Processors
+ * @name Maximum number of processors
+ * @brief DLA ash 6 processors
+ * @{
+ */
+#define DLA_OP_NUM		6
+/** @} */
+
+/**
+ * @ingroup Processors
+ * @name Number of groups
+ * @brief Each processor has 2 groups of registers
+ * @{
+ */
+#define DLA_NUM_GROUPS		2
+/** @} */
+
+/**
+ * Network descriptor
+ *
+ * Contains all information to execute a network
+ *
+ * @op_head: Index of first operation of each type in operations list
+ * @num_rois: Number of ROIs
+ * @num_operations: Number of operations in one list
+ * @num_luts: Number of LUTs
+ */
+struct dla_network_desc {
+	int16_t operation_desc_index;
+	int16_t surface_desc_index;
+
+	int16_t dependency_graph_index;
+	int16_t lut_data_index;
+
+	int16_t roi_array_index;
+	int16_t surface_index;
+
+	int16_t stat_list_index;
+	int16_t reserved1;
+
+	int16_t op_head[DLA_OP_NUM];
+
+	uint16_t num_rois;
+	uint16_t num_operations;
+
+	uint16_t num_luts;
+	uint16_t num_addresses;
+
+	int16_t input_layer;
+	uint8_t dynamic_roi;
+	uint8_t reserved0;
+} __packed __aligned(4);
+
+/**
+ * @name Memory types
+ * @brief DLA engnine can read/write to/from 3 memory types
+ * @{
+ */
+#define DLA_MEM_MC			0 /* External DRAM */
+#define DLA_MEM_CV			1 /* CV-SRAM */
+#define DLA_MEM_HW			2 /* DLA sub-module */
+/** @} */
+
+/**
+ * @ingroup Events
+ * @name Operation events
+ * @brief Different events triggered by an operations
+ * @{
+ */
+#define DLA_EVENT_OP_COMPLETED		1
+#define DLA_EVENT_OP_PROGRAMMED		2
+#define DLA_EVENT_OP_ENABLED		3
+#define DLA_EVENT_CDMA_WT_DONE		4
+#define DLA_EVENT_CDMA_DT_DONE		5
+/** @} */
+
+struct dla_consumer {
+	int16_t index; /* the index of dla_common_op_desc in dep_graph_addr */
+	uint8_t event;
+	uint8_t res;
+} __packed __aligned(4);
+
+struct dla_common_op_desc {
+	int16_t index; /* set by ucode */
+	int8_t roi_index;
+	uint8_t op_type;
+
+	uint8_t dependency_count;
+	uint8_t reserved0[3];
+
+	struct dla_consumer consumers[DLA_OP_NUM];
+	struct dla_consumer fused_parent;
+} __packed __aligned(4);
+
+struct dla_roi_array_desc {
+	uint32_t array_length;
+
+	uint32_t array_reserved;
+} __packed __aligned(4);
+
+struct dla_roi_desc {
+	uint32_t left;
+
+	uint32_t top;
+
+	uint32_t right;
+
+	uint32_t bottom;
+} __packed __aligned(4);
+
+/**
+ * @ingroup BDMA
+ * @name Maximum BDMA transfers
+ * @brief BDMA supports multiple transfers in operation. This indicates
+ *        maximum number of transfers possible in one operation.
+ * @{
+ */
+#define NUM_MAX_BDMA_OPS	20
+/** @} */
+
+struct dla_bdma_transfer_desc {
+	int16_t source_address;
+	int16_t destination_address;
+
+	uint32_t line_size;
+
+	uint32_t line_repeat;
+
+	uint32_t source_line;
+
+	uint32_t destination_line;
+
+	uint32_t surface_repeat;
+
+	uint32_t source_surface;
+
+	uint32_t destination_surface;
+} __packed __aligned(4);
+
+struct dla_bdma_surface_desc {
+	uint8_t source_type;
+	uint8_t destination_type;
+	uint16_t num_transfers;
+
+	struct dla_bdma_transfer_desc transfers[NUM_MAX_BDMA_OPS];
+} __packed __aligned(4);
+
+struct dla_bdma_op_desc {
+	uint16_t num_transfers;
+	uint16_t reserved0;
+} __packed __aligned(4);
+
+struct dla_bdma_stat_desc {
+	uint32_t read_stall;
+	uint32_t write_stall;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+/**
+ * @ingroup Convolution
+ * @name Convolution mode
+ * @brief Convolution modes support by DLA
+ * @{
+ */
+#define CONV_MODE_DIRECT	0
+#define CONV_MODE_WINOGRAD	1
+/** @} */
+
+/**
+ * @ingroup Processors
+ * @name Precision BPE mapping
+ * @brief Precision formats and Bit Per Elements mapping
+ * @{
+ */
+#define BPE_PRECISION_INT8		1
+#define BPE_PRECISION_INT16		2
+#define BPE_PRECISION_FP16		2
+/** @} */
+
+
+/**
+ * @ingroup Processors
+ * @name Precision types
+ * @brief Precision formats supported by DLA engine
+ * @{
+ */
+#define PRECISION_INT8		0
+#define PRECISION_INT16		1
+#define PRECISION_FP16		2
+/** @} */
+
+/**
+ * @ingroup Processors
+ * @name Data formats
+ * @brief Data formats supported by DLA engine
+ * @{
+ */
+#define FORMAT_T_R8			0
+#define FORMAT_T_R10			1
+#define FORMAT_T_R12			2
+#define FORMAT_T_R16			3
+#define FORMAT_T_R16_I			4
+#define FORMAT_T_R16_F			5
+#define FORMAT_T_A16B16G16R16		6
+#define FORMAT_T_X16B16G16R16		7
+#define FORMAT_T_A16B16G16R16_F		8
+#define FORMAT_T_A16Y16U16V16		9
+#define FORMAT_T_V16U16Y16A16		10
+#define FORMAT_T_A16Y16U16V16_F		11
+#define FORMAT_T_A8B8G8R8		12
+#define FORMAT_T_A8R8G8B8		13
+#define FORMAT_T_B8G8R8A8		14
+#define FORMAT_T_R8G8B8A8		15
+#define FORMAT_T_X8B8G8R8		16
+#define FORMAT_T_X8R8G8B8		17
+#define FORMAT_T_B8G8R8X8		18
+#define FORMAT_T_R8G8B8X8		19
+#define FORMAT_T_A2B10G10R10		20
+#define FORMAT_T_A2R10G10B10		21
+#define FORMAT_T_B10G10R10A2		22
+#define FORMAT_T_R10G10B10A2		23
+#define FORMAT_T_A2Y10U10V10		24
+#define FORMAT_T_V10U10Y10A2		25
+#define FORMAT_T_A8Y8U8V8			26
+#define FORMAT_T_V8U8Y8A8			27
+#define FORMAT_T_Y8___U8V8_N444		28
+#define FORMAT_T_Y8___V8U8_N444		29
+#define FORMAT_T_Y10___U10V10_N444	30
+#define FORMAT_T_Y10___V10U10_N444	31
+#define FORMAT_T_Y12___U12V12_N444	32
+#define FORMAT_T_Y12___V12U12_N444	33
+#define FORMAT_T_Y16___U16V16_N444	34
+#define FORMAT_T_Y16___V16U16_N444	35
+#define FORMAT_FEATURE			36
+/** @} */
+
+/**
+ * @ingroup Convolution
+ * @name Pixel mapping
+ * @brief Pixel mapping formats supported for image input in Convolution
+ * @{
+ */
+#define MAP_PITCH_LINEAR		0
+/** @} */
+
+/**
+ * @ingroup Convolution
+ * @name Weight formats
+ * @brief Weight data formats supported in Convolution
+ * @{
+ */
+#define WEIGHT_FORMAT_UNCOMPRESSED	0
+#define WEIGHT_FORMAT_COMPRESSED	1
+/** @} */
+
+/**
+ * @ingroup Convolution
+ * @name Mean data format
+ * @brief Mean data formats supported in Convolution
+ * @{
+ */
+#define MEAN_FORMAT_DISABLE     0
+#define MEAN_FORMAT_ENABLE      1
+/** @} */
+
+struct dla_cvt_param {
+	int16_t  scale;
+	uint8_t  truncate;
+	uint8_t  enable;
+
+	int32_t  offset;
+} __packed __aligned(4);
+
+struct dla_data_cube {
+	uint16_t type; /* dla_mem_type */
+	int16_t address; /* offset to the actual IOVA in task.address_list */
+
+	uint32_t offset; /* offset within address */
+	uint32_t size;
+
+	/* cube dimensions */
+	uint16_t width;
+	uint16_t height;
+
+	uint16_t channel;
+	uint16_t reserved0;
+
+	/* stride information */
+	uint32_t line_stride;
+	uint32_t surf_stride;
+
+	/* For Rubik only */
+	uint32_t plane_stride;
+} __packed __aligned(4);
+
+#define PIXEL_OVERRIDE_UINT 0
+#define PIXEL_OVERRIDE_INT  1
+
+struct dla_conv_surface_desc {
+	/* Data cube */
+	struct dla_data_cube weight_data;
+	struct dla_data_cube wmb_data;
+	struct dla_data_cube wgs_data;
+	struct dla_data_cube src_data;
+	struct dla_data_cube dst_data;
+
+	/**
+	 * u_addr = input_data.source_addr + offset_u
+	 * this field should be set when YUV is not interleave format
+	 *
+	 */
+	int64_t offset_u;
+
+	/* line stride for 2nd plane, must be 32bytes aligned */
+	uint32_t in_line_uv_stride;
+} __packed __aligned(4);
+
+struct dla_conv_op_desc {
+	/* Performance parameters */
+
+	/* dla_conv_mode */
+	uint8_t conv_mode;
+	uint8_t data_reuse;
+	uint8_t weight_reuse;
+	uint8_t skip_data_rls;
+
+	uint8_t skip_weight_rls;
+	uint8_t reserved0;
+	uint16_t entry_per_slice;
+
+	/* dla_data_format */
+	uint8_t data_format;
+	/* dla_pixel_mapping */
+	uint8_t pixel_mapping;
+	/* number of free slices before fetch */
+	uint16_t fetch_grain;
+
+	uint8_t reserved_b[8];
+
+	/* batch_num */
+	uint8_t batch;
+	/* dla_weight_format */
+	uint8_t weight_format;
+	uint8_t data_bank;
+	uint8_t weight_bank;
+
+	/* the offset in bytes of each data cube in a batch */
+	uint32_t batch_stride;
+
+	uint8_t post_extension;
+	uint8_t pixel_override;
+	/* number of slices need to be released */
+	uint16_t release;
+
+	 /* The input cube dimension for CSC */
+	uint16_t input_width_csc;
+	uint16_t input_height_csc;
+
+	uint16_t input_channel_csc;
+	uint16_t kernel_width_csc;
+
+	uint16_t kernel_height_csc;
+	uint16_t kernel_channel_csc;
+
+	/* The input cube dimension for CMAC */
+	uint16_t input_width_cmac;
+	uint16_t input_height_cmac;
+
+	/* actual size in bytes */
+	uint32_t bytes_per_kernel;
+
+	/* Algorithm parameters */
+
+	int16_t mean_ry; /* mean value for red in RGB or Y in YUV */
+	int16_t mean_gu; /* mean value for green in RGB or U in YUV */
+
+	int16_t mean_bv; /* mean value for blue in RGB or V in YUV */
+	int16_t mean_ax;
+
+	uint8_t mean_format; /* dla_mean_format */
+	uint8_t conv_stride_x;
+	uint8_t conv_stride_y;
+	uint8_t pad_x_left;
+
+	uint8_t pad_x_right;
+	uint8_t pad_y_top;
+	uint8_t pad_y_bottom;
+	uint8_t dilation_x;
+
+	uint8_t dilation_y;
+	uint8_t reserved2[2];
+
+	/* Precision parameters */
+	uint8_t pra_truncate;
+
+	uint8_t in_precision;
+	/* The output precision from CONV, it's the MAC processing precison */
+	uint8_t out_precision;
+	int16_t pad_val;
+
+	/* input converter parameters */
+	struct dla_cvt_param in_cvt;
+	/* output converter parameters, support truncate only */
+	struct dla_cvt_param out_cvt;
+
+} __packed __aligned(4);
+
+struct dla_conv_stat_desc {
+	uint32_t data_read_stall;
+	uint32_t weight_read_stall;
+	uint32_t data_read_latency;
+	uint32_t weight_read_latency;
+	uint32_t saturation_count;
+	uint32_t nan_data_num;
+	uint32_t nan_weight_num;
+	uint32_t inf_data_num;
+	uint32_t inf_weight_num;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+/**
+ * @ingroup SDP
+ * @name Activation functions
+ * @brief Activation functions supported in SDP
+ * @{
+ */
+#define ACTIVATION_NONE		0
+#define ACTIVATION_RELU		1
+#define ACTIVATION_LUT		2
+#define ACTIVATION_PRELU	3
+/** @} */
+
+/**
+ * @ingroup LUT
+ * @name LUT size
+ * @brief LUT sizes for linear and exponentila LUT
+ * @{
+ */
+#define LUT_LINEAR_EXP_TABLE_ENTRY_LOG2		6
+#define LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2	8
+/** @} */
+
+/**
+ * @ingroup LUT
+ * @name LUT types
+ * @brief DLA supports two types of LUT, linear and exonential
+ * @{
+ */
+#define LUT_LINEAR_EXP_TABLE		0
+#define LUT_LINEAR_ONLY_TABLE		1
+/** @} */
+
+/**
+ * @ingroup LUT
+ * @name LUT methods
+ * @brief DLA supports two types of LUT, linear and exonential
+ * @{
+ */
+#define LUT_METHOD_EXPONENTIAL		0
+#define LUT_METHOD_LINEAR		1
+/** @} */
+
+/**
+ * @ingroup LUT
+ * @name LUT
+ * @brief DLA supports two types of LUT, linear and exonential
+ * @{
+ */
+#define LUT_PRI_LINEAR_EXP		0
+#define LUT_PRI_LINEAR_ONLY		1
+/** @} */
+
+union dla_lut_offset {
+	/**
+	 * Number should be substracted on log domain before look up
+	 * exponetial table it has the same definition as hardware
+	 * thus input scaling should also take into account when
+	 * set this field.
+	 */
+	int8_t exp_offset;
+	/**
+	 * Number of bits should be right shift before looking
+	 * up linear table
+	 */
+	int8_t frac_bits;
+	uint16_t reserved0;
+};
+
+/**
+ * This struct is used to represent floating point values by INT
+ * suppose we have a float point number fp_x, it will be represented
+ * as:
+ *
+ * fp_x = scale_int_x>>(shifter_x)
+ *
+ * This is very useful for INT pipeline;
+ */
+struct dla_float_data {
+	int16_t scale;
+	int8_t shifter;
+	uint8_t reserved0;
+} __packed __aligned(4);
+
+/**
+ * For INT pipeline, we use the struct above to represent a floating number;
+ * For FP16 pipeline, we should store the FP16 encoded value into a uint16_t
+ * container
+ */
+union dla_slope {
+	struct dla_float_data data_i;
+
+	uint16_t data_f;
+};
+
+struct dla_lut_param {
+	/**
+	 * value of expression ((1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1) is 65,
+	 * ((1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1) is 257, and int16_t is of
+	 * 2Byte. And below two statement's combined memory size is 644 Byte.
+	 *
+	 * NOTE: below two declaration combined size should always be multiple
+	 * of 4.
+	 */
+	int16_t linear_exp_table[(1<<LUT_LINEAR_EXP_TABLE_ENTRY_LOG2)+1];
+	int16_t linear_only_table[(1<<LUT_LINEAR_ONLY_TABLE_ENTRY_LOG2)+1];
+
+	union dla_lut_offset linear_exp_offset;
+	union dla_lut_offset linear_only_offset;
+
+	/**
+	 * The start and end point of raw table,
+	 * valid when raw_method=LINEAR only
+	 */
+	uint64_t linear_exp_start;
+	uint64_t linear_exp_end;
+	uint64_t linear_only_start;
+	uint64_t linear_only_end;
+
+	union dla_slope linear_exp_underflow_slope;
+	union dla_slope linear_exp_overflow_slope;
+	union dla_slope linear_only_underflow_slope;
+	union dla_slope linear_only_overflow_slope;
+
+	/**
+	 * dla_lut_priority, when both lut are hit(or one overflow,
+	 * the other underflow), which one should be selected as output
+	 */
+	uint8_t hybrid_priority;
+	uint8_t underflow_priority;
+	uint8_t overflow_priority;
+	uint8_t method; /* dla_lut_method */
+} __packed __aligned(4);
+
+struct dla_sdp_surface_desc {
+	/* Data cube */
+	/* source input cube, available when SDP working on offline mode */
+	struct dla_data_cube src_data;
+
+	/* X1 input cube */
+	struct dla_data_cube x1_data;
+
+	/* X2 input cube */
+	struct dla_data_cube x2_data;
+
+	/* Y input cube */
+	struct dla_data_cube y_data;
+
+	/* Output cube */
+	struct dla_data_cube dst_data;
+} __packed __aligned(4);
+
+#define SDP_OP_NONE		0
+#define SDP_OP_MUL		1
+#define SDP_OP_ADD		2
+#define SDP_OP_BOTH		3
+
+#define SDP_ALU_OP_MAX		0
+#define SDP_ALU_OP_MIN		1
+#define SDP_ALU_OP_SUM		2
+#define SDP_ALU_OP_EQL		3
+
+#define SDP_OP_PER_LAYER	0
+#define SDP_OP_PER_KERNEL	1
+#define SDP_OP_PER_POINT	2
+
+struct dla_sdp_cvt {
+	struct dla_cvt_param alu_cvt;
+	struct dla_cvt_param mul_cvt;
+} __packed __aligned(4);
+
+struct dla_sdp_op {
+	uint8_t enable;
+	uint8_t alu_type; /* dla_sdp_alu_op_type */
+	uint8_t type; /* dla_sdp_op_type */
+	uint8_t mode; /* dla_sdp_op_mode */
+
+	uint8_t act; /* dla_act_type */
+	uint8_t shift_value; /* left shift */
+	uint8_t truncate;
+	uint8_t precision;
+
+	int32_t alu_operand;
+	int32_t mul_operand;
+
+	struct dla_sdp_cvt  cvt;
+} __packed __aligned(4);
+
+struct dla_sdp_op_desc {
+	/* Precision parameters */
+	/* dla_precision */
+	uint8_t src_precision;
+	uint8_t dst_precision;
+	int16_t lut_index;
+
+	struct dla_cvt_param out_cvt;
+
+	/* Performance parameters */
+	/* dla_conv_mode */
+	uint8_t conv_mode;
+	uint8_t batch_num;
+	uint16_t reserved0;
+
+	uint32_t batch_stride;	/* will be used when batch_num > 1 */
+
+	/* Algorithm parameters */
+	struct dla_sdp_op x1_op;
+	struct dla_sdp_op x2_op;
+	struct dla_sdp_op y_op;
+} __packed __aligned(4);
+
+struct dla_sdp_stat_desc {
+	uint32_t nan_input_num;
+	uint32_t inf_input_num;
+	uint32_t nan_output_num;
+	uint32_t wdma_write_stall;
+	uint32_t lut_underflow;
+	uint32_t lut_overflow;
+	uint32_t lut_hybrid;
+	uint32_t lut_le_hit;
+	uint32_t lut_lo_hit;
+	uint32_t saturation_count;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+#define POOL_MODE_AVG		0
+#define POOL_MODE_MAX		1
+#define POOL_MODE_MIN		2
+
+#define POOL_SIZE_1		0
+#define POOL_SIZE_2		1
+#define POOL_SIZE_3		2
+#define POOL_SIZE_4		3
+#define POOL_SIZE_5		4
+#define POOL_SIZE_6		5
+#define POOL_SIZE_7		6
+#define POOL_SIZE_8		7
+
+#define PDP_PAD_VAL_NUM	7
+
+struct dla_pdp_surface_desc {
+	/* Data cube */
+	struct dla_data_cube src_data;
+
+	struct dla_data_cube dst_data;
+} __packed __aligned(4);
+
+struct dla_pdp_op_desc {
+	/* Performance parameters */
+	uint16_t  partial_in_width_first;
+	uint16_t  partial_in_width_mid;
+
+	uint16_t  partial_in_width_last;
+	uint16_t  partial_width_first;
+
+	uint16_t  partial_width_mid;
+	uint16_t  partial_width_last;
+
+	uint8_t   split_num;
+
+	/* Algorithm parameters */
+	uint8_t  pool_mode; /* dla_pool_mode */
+	uint8_t  pool_width; /* dla_pool_width */
+	uint8_t  pool_height; /* dla_pool_height */
+
+	uint8_t  stride_x;
+	uint8_t  stride_y;
+
+	/**
+	 * The left/right padding size,
+	 * pad_right might be less than pad_left
+	 */
+	uint8_t  pad_left;
+	uint8_t  pad_right;
+
+	/* The top/bottom padding size */
+	uint8_t  pad_top;
+	uint8_t  pad_bottom;
+
+	/* Precision parameters */
+	uint8_t  precision; /* dla_precision */
+	uint8_t  reserved0;
+	/**
+	 * if input has non-zero "offset", this value should be set
+	 * There'll be 7 different paddding values, the relationship between
+	 * those versions are:
+	 * padding_value[0] = -offset*scaling;
+	 * padding_value[1] = 2*padding_value[0]
+	 * padding_value[2] = 3*padding_value[0]
+	 * ...
+	 * The purpose is to avoid ucode implement FP16
+	 * multiplier(for FP16 mode)
+	 */
+	int32_t  padding_value[PDP_PAD_VAL_NUM];
+} __packed __aligned(4);
+
+struct dla_pdp_stat_desc {
+	uint32_t inf_input_num;
+	uint32_t nan_input_num;
+	uint32_t nan_output_num;
+	uint32_t write_stall;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+struct dla_cdp_surface_desc {
+	/* Data cube */
+	struct dla_data_cube src_data;
+
+	struct dla_data_cube dst_data;
+} __packed __aligned(4);
+
+struct dla_cdp_op_desc {
+	/* Precision parameters */
+
+	/* dla_precision */
+	uint8_t  in_precision;
+	uint8_t  out_precision;
+	int16_t  lut_index;
+
+	struct dla_cvt_param in_cvt;
+	struct dla_cvt_param out_cvt;
+
+	/* Performance parameters */
+
+	/* Algorithm parameters */
+	uint8_t  local_size;
+	uint8_t  bypass_sqsum;
+	uint8_t  bypass_out_mul;
+	uint8_t  reserved0;
+} __packed __aligned(4);
+
+struct dla_cdp_stat_desc {
+	uint32_t nan_input_num;
+	uint32_t inf_input_num;
+	uint32_t nan_output_num;
+	uint32_t write_stall;
+	uint32_t lut_uflow;
+	uint32_t lut_oflow;
+	uint32_t lut_hybrid;
+	uint32_t lut_le_hit;
+	uint32_t lut_lo_hit;
+	uint32_t saturation_count;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+struct dla_rubik_surface_desc {
+	/* Data cube */
+	struct dla_data_cube src_data;
+
+	struct dla_data_cube dst_data;
+} __packed __aligned(4);
+
+/* rubik mode */
+#define RUBIK_MODE_CONTRACT	0
+#define RUBIK_MODE_SPLIT	1
+#define RUBIK_MODE_MERGE	2
+
+struct dla_rubik_op_desc {
+	/* Precision parameters */
+	uint8_t mode;
+	uint8_t precision;
+	uint8_t stride_x;
+	uint8_t stride_y;
+} __packed __aligned(4);
+
+struct dla_rubik_stat_desc {
+	uint32_t read_stall;
+	uint32_t write_stall;
+	uint32_t runtime;
+} __packed __aligned(4);
+
+union dla_surface_container {
+	struct dla_bdma_surface_desc bdma_surface;
+	struct dla_conv_surface_desc conv_surface;
+	struct dla_sdp_surface_desc sdp_surface;
+	struct dla_pdp_surface_desc pdp_surface;
+	struct dla_cdp_surface_desc cdp_surface;
+	struct dla_rubik_surface_desc rubik_surface;
+};
+
+union dla_operation_container {
+	struct dla_bdma_op_desc bdma_op;
+	struct dla_conv_op_desc conv_op;
+	struct dla_sdp_op_desc sdp_op;
+	struct dla_pdp_op_desc pdp_op;
+	struct dla_cdp_op_desc cdp_op;
+	struct dla_rubik_op_desc rubik_op;
+};
+
+union dla_stat_container {
+	struct dla_bdma_stat_desc bdma_stat;
+	struct dla_conv_stat_desc conv_stat;
+	struct dla_sdp_stat_desc sdp_stat;
+	struct dla_pdp_stat_desc pdp_stat;
+	struct dla_cdp_stat_desc cdp_stat;
+	struct dla_rubik_stat_desc rubik_stat;
+};
+
+/**
+ * status notifier structure
+ *
+ * @address: 64-bit timestamp representing the time at which
+ * the notifier was written
+ * @status_engine: status work captured from HW engine
+ * @subframe: NA
+ * @status_task: status word as configured from an action list
+ */
+struct dla_task_status {
+	uint64_t timestamp;
+
+	uint32_t status_engine;
+
+	uint16_t subframe;
+	uint16_t status_task;
+} __packed __aligned(4);
+
+#endif
diff --git a/drivers/nvdla/include/dla_sched.h b/drivers/nvdla/include/dla_sched.h
new file mode 100644
index 000000000000..7ed35487da16
--- /dev/null
+++ b/drivers/nvdla/include/dla_sched.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DLA_SCHED_H_
+#define __DLA_SCHED_H_
+
+struct dla_task {
+	/* platform specific data to communicate with portability layer */
+	void *task_data;
+	/* task state */
+	uint32_t state;
+	/* Task base address */
+	uint64_t base;
+	/* start address of a list of dla_operation_container */
+	uint64_t operation_desc_addr;
+	/* start address of a list of dla_surface_container */
+	uint64_t surface_desc_addr;
+	/* start address of a list of dla_common_op_desc */
+	uint64_t dependency_graph_addr;
+	/* start address of a list of dla_lut_param */
+	uint64_t lut_data_addr;
+	/*
+	 * start address of a list of dla_roi_desc,
+	 * the first one is dla_roi_array_desc
+	 * valid when network.dynamic_roi is true
+	 */
+	uint64_t roi_array_addr;
+	/* start address of a list of dla_surface_container */
+	uint64_t surface_addr;
+	/* start address of a list of dla_stat_container */
+	uint64_t stat_data_addr;
+} __packed __aligned(256);
+
+/**
+ * @brief			Configuration parameters supported by the engine
+ *
+ * atom_size			Memory smallest access size
+ * bdma_enable			Defines whether bdma is supported
+ * rubik_enable			Defines whether rubik is supported
+ * weight_compress_support	Defines whether weight data compression is supported
+ */
+struct dla_config {
+	uint32_t atom_size;
+	bool bdma_enable;
+	bool rubik_enable;
+	bool weight_compress_support;
+};
+
+#endif
diff --git a/drivers/nvdla/include/nvdla_interface.h b/drivers/nvdla/include/nvdla_interface.h
new file mode 100644
index 000000000000..7ad40b4c3db0
--- /dev/null
+++ b/drivers/nvdla/include/nvdla_interface.h
@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NVDLA_INTERFACE_H_
+#define __NVDLA_INTERFACE_H_
+
+#include <linux/types.h>
+
+/**
+ * @brief			Register driver to firmware
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * This function must be called once during boot to initialize DLA
+ * engine scheduler and register driver with firmware before submitting
+ * any task. Pass pointer to driver context in @param driver_context
+ * which is passed as param when firmware calls any function
+ * of portability layer. It also updates pointer to engine context
+ * which must be passed in any function call to firmware after this point.
+ *
+ * @param engine_context	Pointer to engine specific data
+ * @param driver_context	Pointer to driver specific data
+ *
+ * @return			0 on success and negative on error
+ */
+int32_t dla_register_driver(void **engine_context, void *driver_context);
+
+/**
+ * @brief			Interrupt handler
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * This function is called when DLA interrupt is received. Portability layer
+ * should register it's own handler using the mechanism supported by that platform
+ * and call this function from the handler. Call to this function must be
+ * protected by lock to prevent handling interrupt when firmware is programming
+ * layers in process context.
+ *
+ * @param engine_context	Engine specific data received in dla_register_driver
+ *
+ * @return			0 on success and negative on error
+ */
+int32_t dla_isr_handler(void *engine_context);
+
+/**
+ * @brief			Process events recorded in interrupt handler
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * Interrupt handler just records events and does not process those events.
+ * Portability layer must call this function in thread/process context after
+ * interrupt handler is done.
+ *
+ * @param engine_context	Engine specific data received in dla_register_driver
+ * @param task_complete		Pointer to parameter to indicate task complete,
+				firmare writes 1 to it if all layers are processed.
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_process_events(void *engine_context, uint32_t *task_complete);
+
+/**
+ * @brief			Clear task from firmware
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * This function resets engine scheduler state including op descriptor cache,
+ * error values, sub-engine status, events etc and clears previous task state
+ * from firmware. This function can be called by portability layer after
+ * task completion. It is not mandatory to call it but calling it will
+ * ensure clean state before next task execution.
+ *
+ * @param engine_context	Engine specific data received in dla_register_driver
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+void dla_clear_task(void *engine_context);
+
+/**
+ * @brief			Execute task
+ *
+ * Implementation in firmware, called by portability layer
+ *
+ * This function initializes sub-engines and starts task execution. Further
+ * programming and layer scheduling is triggered by events received from
+ * hardware.
+ *
+ * @param engine_context	Engine specific data received in dla_register_driver
+ * @param task_data		Task specific data to be passed when reading task info
+ * @param config_data		Configuration data to be passed
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_execute_task(void *engine_context, void *task_data, void *config_data);
+
+/**
+ * @brief			Register read
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Read DLA HW register. Portability layer is responsible to use correct
+ * base address and for any IO mapping if required.
+ *
+ * @param engine_context	Driver specific data received in dla_register_driver
+ * @param addr			Register offset
+ *
+ * @return			Register value
+ *
+ */
+uint32_t dla_reg_read(void *driver_context, uint32_t addr);
+
+/**
+ * @brief			Register write
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Write DLA HW registr. Portability layer is responsible to use correct
+ * base address and for any IO mapping if required.
+ *
+ * @param driver_context	Driver specific data received in dla_register_driver
+ * @param addr			Register offset
+ * @param reg			Value to write
+ *
+ */
+void dla_reg_write(void *driver_context, uint32_t addr, uint32_t reg);
+
+/**
+ * @brief			Read data from DMA mapped memory in local buffer
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * This function reads data from buffers passed by UMD in local memory.
+ * Addresses for buffers passed by are shared in address list and network
+ * descriptor contains index in address list for those buffers. Firmware
+ * reads this data from buffer shared by UMD into local buffer to consume
+ * the information.
+ *
+ * @param driver_context	Driver specific data received in dla_register_driver
+ * @param task_data		Task specific data received in dla_execute_task
+ * @param src			Index in address list
+ * @param dst			Pointer to local memory
+ * @param size			Size of data to copy
+ * @param offset		Offset from start of UMD buffer
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_data_read(void *driver_context, void *task_data,
+				uint64_t src, void *dst,
+				uint32_t size, uint64_t offset);
+
+/**
+ * @brief			Write data to DMA mapped memory from local buffer
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * This function writes data from local buffer to buffer passed by UMD.
+ * Addresses for buffers passed by are shared in address list and network
+ * descriptor contains index in address list for those buffers. Firmware
+ * writes this data to buffer shared by UMD from local buffer to update
+ * the information.
+ *
+ * @param driver_context	Driver specific data received in dla_register_driver
+ * @param task_data		Task specific data received in dla_execute_task
+ * @param src			Pointer to local memory
+ * @param dst			Index in address list
+ * @param size			Size of data to copy
+ * @param offset		Offset from start of UMD buffer
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_data_write(void *driver_context, void *task_data,
+				void *src, uint64_t dst,
+				uint32_t size, uint64_t offset);
+
+/* Destination for DMA buffer */
+#define DESTINATION_PROCESSOR	0
+#define DESTINATION_DMA		1
+
+/**
+ * @brief			Read DMA address
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Some buffers shared by UMD are accessed by processor responsible for
+ * programming DLA HW. It would be companion micro-controller in case of
+ * headed config while main CPU in case of headless config. Also, some
+ * buffers are accessed by DLA DMA engines inside sub-engines. This function
+ * should return proper address accessible by destination user depending
+ * on config.
+ *
+ * @param driver_context	Driver specific data received in dla_register_driver
+ * @param task_data		Task specific data received in dla_execute_task
+ * @param index			Index in address list
+ * @param dst_ptr		Pointer to update address
+ * @param destination		Destination user for DMA address
+ *
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t dla_get_dma_address(void *driver_context, void *task_data,
+					int16_t index, void *dst_ptr,
+					uint32_t destination);
+
+/**
+ * @brief			Read time value in micro-seconds
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Read system time in micro-seconds
+ *
+ * @return			Time value in micro-seconds
+ *
+ */
+int64_t dla_get_time_us(void);
+
+/**
+ * @brief			Print debug message
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Print debug message to console
+ *
+ * @param str			Format string and variable arguments
+ *
+ */
+void dla_debug(const char *str, ...);
+
+/**
+ * @brief			Print information message
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Print information message to console
+ *
+ * @param str			Format string and variable arguments
+ *
+ */
+void dla_info(const char *str, ...);
+
+/**
+ * @brief			Print warning message
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Print warning message to console
+ *
+ * @param str			Format string and variable arguments
+ *
+ */
+void dla_warn(const char *str, ...);
+
+/**
+ * @brief			Print error message
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Print error message to console
+ *
+ * @param str			Format string and variable arguments
+ *
+ */
+void dla_error(const char *str, ...);
+
+/**
+ * @brief			Fill memory region
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Fills the first len bytes of the memory area pointed to by src
+ * with the constant byte ch.
+ *
+ * @param src			Memory area address
+ * @param ch			Byte to fill
+ * @param len			Length of memory area to fill
+ *
+ * @return			Memory area address
+ *
+ */
+void *dla_memset(void *src, int ch, uint64_t len);
+
+/**
+ * @brief			Copy memory
+ *
+ * Implementation in portability layer, called by firmware
+ *
+ * Copies len bytes from memory area src to memory area dest.
+ *
+ * @param dest			Destination memory area address
+ * @param src			Source memory area address
+ * @param len			Length of memory area to copy
+ *
+ * @return			Destination memory area address
+ *
+ */
+void *dla_memcpy(void *dest, const void *src, uint64_t len);
+
+#endif
diff --git a/drivers/nvdla/include/nvdla_ioctl.h b/drivers/nvdla/include/nvdla_ioctl.h
new file mode 100644
index 000000000000..3c8ec3a6cd51
--- /dev/null
+++ b/drivers/nvdla/include/nvdla_ioctl.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LINUX_NVDLA_IOCTL_H
+#define __LINUX_NVDLA_IOCTL_H
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#if !defined(__KERNEL__)
+#define __user
+#endif
+
+/**
+ * struct nvdla_mem_handle structure for memory handles
+ *
+ * @handle		handle to DMA buffer allocated in userspace
+ * @reserved		Reserved for padding
+ * @offset		offset in bytes from start address of buffer
+ *
+ */
+struct nvdla_mem_handle {
+	__u32 handle;
+	__u32 reserved;
+	__u64 offset;
+};
+
+/**
+ * struct nvdla_ioctl_submit_task structure for single task information
+ *
+ * @num_addresses		total number of entries in address_list
+ * @reserved			Reserved for padding
+ * @address_list		pointer to array of struct nvdla_mem_handle
+ *
+ */
+struct nvdla_ioctl_submit_task {
+#define NVDLA_MAX_BUFFERS_PER_TASK (6144)
+	__u32 num_addresses;
+#define NVDLA_NO_TIMEOUT    (0xffffffff)
+	__u32 timeout;
+	__u64 address_list;
+};
+
+/**
+ * struct nvdla_submit_args structure for task submit
+ *
+ * @tasks		pointer to array of struct nvdla_ioctl_submit_task
+ * @num_tasks		number of entries in tasks
+ * @flags		flags for task submit, no flags defined yet
+ * @version		version of task structure
+ *
+ */
+struct nvdla_submit_args {
+	__u64 tasks;
+	__u16 num_tasks;
+#define NVDLA_MAX_TASKS_PER_SUBMIT	24
+#define NVDLA_SUBMIT_FLAGS_ATOMIC	(1 << 0)
+	__u16 flags;
+	__u32 version;
+};
+
+/**
+ * struct nvdla_gem_create_args for allocating DMA buffer through GEM
+ *
+ * @handle		handle updated by kernel after allocation
+ * @flags		implementation specific flags
+ * @size		size of buffer to allocate
+ */
+struct nvdla_gem_create_args {
+	__u32 handle;
+	__u32 flags;
+	__u64 size;
+};
+
+/**
+ * struct nvdla_gem_map_offset_args for mapping DMA buffer
+ *
+ * @handle		handle of the buffer
+ * @reserved		reserved for padding
+ * @offset		offset updated by kernel after mapping
+ */
+struct nvdla_gem_map_offset_args {
+	__u32 handle;
+	__u32 reserved;
+	__u64 offset;
+};
+
+/**
+ * struct nvdla_gem_destroy_args for destroying DMA buffer
+ *
+ * @handle		handle of the buffer
+ */
+struct nvdla_gem_destroy_args {
+	__u32 handle;
+};
+
+#define DRM_NVDLA_SUBMIT		0x00
+#define DRM_NVDLA_GEM_CREATE		0x01
+#define DRM_NVDLA_GEM_MMAP		0x02
+#define DRM_NVDLA_GEM_DESTROY		0x03
+
+#define DRM_IOCTL_NVDLA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_SUBMIT, struct nvdla_submit_args)
+#define DRM_IOCTL_NVDLA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_GEM_CREATE, struct nvdla_gem_create_args)
+#define DRM_IOCTL_NVDLA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_GEM_MMAP, struct nvdla_gem_map_offset_args)
+#define DRM_IOCTL_NVDLA_GEM_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_NVDLA_GEM_DESTROY, struct nvdla_gem_destroy_args)
+
+#endif
diff --git a/drivers/nvdla/include/nvdla_linux.h b/drivers/nvdla/include/nvdla_linux.h
new file mode 100644
index 000000000000..2fc543dfa1c4
--- /dev/null
+++ b/drivers/nvdla/include/nvdla_linux.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LINUX_NVDLA_LINUX_H_
+#define __LINUX_NVDLA_LINUX_H_
+
+#include <linux/completion.h>
+#include <linux/device.h>
+#include <linux/kref.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+/**
+ * @brief			Task information submitted from user space
+ *
+ * ref				Reference count for task
+ * num_addresses		Number of addresses in address list
+ * nvdla_dev			Pointer to NVDLA device
+ * address_list			Address list
+ * file				DRM file instance
+ */
+struct nvdla_task {
+	struct kref ref;
+	uint32_t num_addresses;
+	struct nvdla_device *nvdla_dev;
+	struct nvdla_mem_handle *address_list;
+	struct drm_file *file;
+};
+
+/**
+ * @brief			Configuration parameters supported by the engine
+ *
+ * atom_size			Memory smallest access size
+ * bdma_enable			Defines whether bdma is supported
+ * rubik_enable			Defines whether rubik is supported
+ * weight_compress_support	Defines whether weight data compression is supported
+ */
+struct nvdla_config
+{
+	uint32_t atom_size;
+	bool bdma_enable;
+	bool rubik_enable;
+	bool weight_compress_support;
+};
+
+/**
+ * @brief			NVDLA device
+ *
+ * irq				Interrupt number associated with this device
+ * ref				Reference count for device
+ * base				IO mapped base address for device
+ * nvdla_lock			Spinlock used for synchronization
+ * drm				DRM device instance
+ * task				Pointer to task in execution
+ * config_data			Pointer to the configuration data
+ * pdev				Pointer to NVDLA platform device
+ * event_notifier		Completion object used to wait for events from HW
+ * engine_context		Private data passed from engine in dla_engine_init
+ */
+struct nvdla_device {
+	int32_t irq;
+	struct kref ref;
+	void __iomem *base;
+	spinlock_t nvdla_lock;
+	struct drm_device *drm;
+	struct nvdla_task *task;
+	struct nvdla_config *config_data;
+	struct platform_device *pdev;
+	struct completion event_notifier;
+
+	void *engine_context;
+};
+
+/**
+ * @brief			Submit task
+ *
+ * This function submits task to NVDLA engine.
+ *
+ * @param nvdla_dev		Pointer to NVDLA device
+ * @param task			Pointer to task
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t nvdla_task_submit(struct nvdla_device *nvdla_dev, struct nvdla_task *task);
+
+/**
+ * @brief			Get DMA address
+ *
+ * This function gets DMA address for given fd
+ *
+ * @param dev			DRM device instance
+ * @param file			DRM file instance
+ * @param fd			File desriptor for DMA buffer
+ * @param addr			Pointer to update DMA address
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t nvdla_gem_dma_addr(struct drm_device *dev, struct drm_file *file,
+					uint32_t fd, dma_addr_t *addr);
+
+/**
+ * @brief			DRM probe
+ *
+ * Probe function for DRM device
+ *
+ * @param nvdla_dev		NVDLA device pointer
+ * @return			0 on success and negative on error
+ *
+ */
+int32_t nvdla_drm_probe(struct nvdla_device *nvdla_dev);
+
+/**
+ * @brief			DRM remove
+ *
+ * Remove function for DRM device
+ *
+ * @param nvdla_dev		NVDLA device pointer
+ *
+ */
+void nvdla_drm_remove(struct nvdla_device *nvdla_dev);
+
+#endif
diff --git a/drivers/nvdla/include/opendla.h b/drivers/nvdla/include/opendla.h
new file mode 100644
index 000000000000..2b4ecd39d732
--- /dev/null
+++ b/drivers/nvdla/include/opendla.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __OPENDLA_H_
+#define __OPENDLA_H_
+
+#define DLA_2_CONFIG
+
+#ifdef DLA_2_CONFIG
+#include <opendla_small.h>
+#else
+#include <opendla_initial.h>
+#endif
+
+#endif
diff --git a/drivers/nvdla/include/opendla_initial.h b/drivers/nvdla/include/opendla_initial.h
new file mode 100644
index 000000000000..71335438f5d4
--- /dev/null
+++ b/drivers/nvdla/include/opendla_initial.h
@@ -0,0 +1,16743 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARNVDLA_H_
+#define __ARNVDLA_H_
+
+// Register GLB_S_NVDLA_HW_VERSION_0
+#define GLB_S_NVDLA_HW_VERSION_0                           (_MK_ADDR_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_SECURE                                    (0x0)
+#define GLB_S_NVDLA_HW_VERSION_0_DUAL                                      (0x0)
+#define GLB_S_NVDLA_HW_VERSION_0_SCR                                         (0)
+#define GLB_S_NVDLA_HW_VERSION_0_WORD_COUNT                                (0x1)
+#define GLB_S_NVDLA_HW_VERSION_0_RESET_VAL            (_MK_MASK_CONST(0x303031))
+#define GLB_S_NVDLA_HW_VERSION_0_RESET_MASK           (_MK_MASK_CONST(0xffffff))
+#define GLB_S_NVDLA_HW_VERSION_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_READ_MASK            (_MK_MASK_CONST(0xffffff))
+#define GLB_S_NVDLA_HW_VERSION_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT                (_MK_SHIFT_CONST(0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_FIELD \
+	(_MK_FIELD_CONST(0xff, GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_RANGE                               (7:0)
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_WOFFSET                             (0x0)
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_DEFAULT            (_MK_MASK_CONST(0x31))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_DEFAULT_MASK       (_MK_MASK_CONST(0xff))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT                (_MK_SHIFT_CONST(8))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_FIELD \
+	(_MK_FIELD_CONST(0xffff, GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_RANGE                              (23:8)
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_WOFFSET                             (0x0)
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_DEFAULT          (_MK_MASK_CONST(0x3030))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register GLB_S_INTR_MASK_0
+#define GLB_S_INTR_MASK_0                                  (_MK_ADDR_CONST(0x4))
+#define GLB_S_INTR_MASK_0_SECURE                                           (0x0)
+#define GLB_S_INTR_MASK_0_DUAL                                             (0x0)
+#define GLB_S_INTR_MASK_0_SCR                                                (0)
+#define GLB_S_INTR_MASK_0_WORD_COUNT                                       (0x1)
+#define GLB_S_INTR_MASK_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RESET_MASK                  (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_MASK_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_READ_MASK                   (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_MASK_0_WRITE_MASK                  (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT              (_MK_SHIFT_CONST(0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_RANGE                             (0:0)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT              (_MK_SHIFT_CONST(1))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_RANGE                             (1:1)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT              (_MK_SHIFT_CONST(2))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_RANGE                             (2:2)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT              (_MK_SHIFT_CONST(3))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_RANGE                             (3:3)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT              (_MK_SHIFT_CONST(4))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_RANGE                             (4:4)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT              (_MK_SHIFT_CONST(5))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_RANGE                             (5:5)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_WOFFSET                           (0x0)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT             (_MK_SHIFT_CONST(6))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_RANGE                            (6:6)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_WOFFSET                          (0x0)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT             (_MK_SHIFT_CONST(7))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_RANGE                            (7:7)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_WOFFSET                          (0x0)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT            (_MK_SHIFT_CONST(8))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_RANGE                           (8:8)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_WOFFSET                         (0x0)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT            (_MK_SHIFT_CONST(9))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_RANGE                           (9:9)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_WOFFSET                         (0x0)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT        (_MK_SHIFT_CONST(16))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_RANGE                      (16:16)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_WOFFSET                      (0x0)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT        (_MK_SHIFT_CONST(17))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_RANGE                      (17:17)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_WOFFSET                      (0x0)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT         (_MK_SHIFT_CONST(18))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_RANGE                       (18:18)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_WOFFSET                       (0x0)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT         (_MK_SHIFT_CONST(19))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_RANGE                       (19:19)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_WOFFSET                       (0x0)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT            (_MK_SHIFT_CONST(20))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_RANGE                          (20:20)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_WOFFSET                          (0x0)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT            (_MK_SHIFT_CONST(21))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_RANGE                          (21:21)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_WOFFSET                          (0x0)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register GLB_S_INTR_SET_0
+#define GLB_S_INTR_SET_0                                   (_MK_ADDR_CONST(0x8))
+#define GLB_S_INTR_SET_0_SECURE                                            (0x0)
+#define GLB_S_INTR_SET_0_DUAL                                              (0x0)
+#define GLB_S_INTR_SET_0_SCR                                                 (0)
+#define GLB_S_INTR_SET_0_WORD_COUNT                                        (0x1)
+#define GLB_S_INTR_SET_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RESET_MASK                   (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_SET_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_READ_MASK                         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_WRITE_MASK                   (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT                (_MK_SHIFT_CONST(0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_RANGE                               (0:0)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT                (_MK_SHIFT_CONST(1))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_RANGE                               (1:1)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT                (_MK_SHIFT_CONST(2))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_RANGE                               (2:2)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT                (_MK_SHIFT_CONST(3))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_RANGE                               (3:3)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT                (_MK_SHIFT_CONST(4))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_RANGE                               (4:4)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT                (_MK_SHIFT_CONST(5))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_RANGE                               (5:5)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_WOFFSET                             (0x0)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_DEFAULT             (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT               (_MK_SHIFT_CONST(6))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_RANGE                              (6:6)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_WOFFSET                            (0x0)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_DEFAULT            (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT               (_MK_SHIFT_CONST(7))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_RANGE                              (7:7)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_WOFFSET                            (0x0)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_DEFAULT            (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT              (_MK_SHIFT_CONST(8))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_RANGE                             (8:8)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_WOFFSET                           (0x0)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT              (_MK_SHIFT_CONST(9))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_RANGE                             (9:9)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_WOFFSET                           (0x0)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_DEFAULT           (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT          (_MK_SHIFT_CONST(16))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_RANGE                        (16:16)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_WOFFSET                        (0x0)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT          (_MK_SHIFT_CONST(17))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_RANGE                        (17:17)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_WOFFSET                        (0x0)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_DEFAULT        (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT           (_MK_SHIFT_CONST(18))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_RANGE                         (18:18)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_WOFFSET                         (0x0)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT           (_MK_SHIFT_CONST(19))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_RANGE                         (19:19)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_WOFFSET                         (0x0)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT              (_MK_SHIFT_CONST(20))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_RANGE                            (20:20)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_WOFFSET                            (0x0)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_DEFAULT            (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT              (_MK_SHIFT_CONST(21))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_RANGE                            (21:21)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_WOFFSET                            (0x0)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_DEFAULT            (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register GLB_S_INTR_STATUS_0
+#define GLB_S_INTR_STATUS_0                                (_MK_ADDR_CONST(0xc))
+#define GLB_S_INTR_STATUS_0_SECURE                                         (0x0)
+#define GLB_S_INTR_STATUS_0_DUAL                                           (0x0)
+#define GLB_S_INTR_STATUS_0_SCR                                              (0)
+#define GLB_S_INTR_STATUS_0_WORD_COUNT                                     (0x1)
+#define GLB_S_INTR_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RESET_MASK                (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_READ_MASK                 (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_STATUS_0_WRITE_MASK                (_MK_MASK_CONST(0x3f03ff))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT          (_MK_SHIFT_CONST(0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_RANGE                         (0:0)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT          (_MK_SHIFT_CONST(1))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_RANGE                         (1:1)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT          (_MK_SHIFT_CONST(2))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_RANGE                         (2:2)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT          (_MK_SHIFT_CONST(3))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_RANGE                         (3:3)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT          (_MK_SHIFT_CONST(4))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_RANGE                         (4:4)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT          (_MK_SHIFT_CONST(5))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_RANGE                         (5:5)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_WOFFSET                       (0x0)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_DEFAULT       (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT         (_MK_SHIFT_CONST(6))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_RANGE                        (6:6)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_WOFFSET                      (0x0)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT         (_MK_SHIFT_CONST(7))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_RANGE                        (7:7)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_WOFFSET                      (0x0)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT        (_MK_SHIFT_CONST(8))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_RANGE                       (8:8)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_WOFFSET                     (0x0)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_DEFAULT     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT        (_MK_SHIFT_CONST(9))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_RANGE                       (9:9)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_WOFFSET                     (0x0)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_DEFAULT     (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT    (_MK_SHIFT_CONST(16))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_RANGE                  (16:16)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_WOFFSET                  (0x0)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT    (_MK_SHIFT_CONST(17))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_RANGE                  (17:17)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_WOFFSET                  (0x0)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT     (_MK_SHIFT_CONST(18))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_RANGE                   (18:18)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_WOFFSET                   (0x0)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT     (_MK_SHIFT_CONST(19))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_RANGE                   (19:19)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_WOFFSET                   (0x0)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT        (_MK_SHIFT_CONST(20))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_RANGE                      (20:20)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_WOFFSET                      (0x0)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT        (_MK_SHIFT_CONST(21))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_FIELD \
+	(_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_RANGE                      (21:21)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_WOFFSET                      (0x0)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_DEFAULT      (_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_RD_WEIGHT_0_0
+#define MCIF_CFG_RD_WEIGHT_0_0                          (_MK_ADDR_CONST(0x2000))
+#define MCIF_CFG_RD_WEIGHT_0_0_SECURE                                      (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_DUAL                                        (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_SCR                                           (0)
+#define MCIF_CFG_RD_WEIGHT_0_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_RD_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_RD_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_RANGE                        (7:0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_WOFFSET                      (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_RANGE                        (15:8)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_WOFFSET                       (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_RANGE                       (23:16)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_WOFFSET                       (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_RANGE                       (31:24)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_WOFFSET                       (0x0)
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_RD_WEIGHT_1_0
+#define MCIF_CFG_RD_WEIGHT_1_0                          (_MK_ADDR_CONST(0x2004))
+#define MCIF_CFG_RD_WEIGHT_1_0_SECURE                                      (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_DUAL                                        (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_SCR                                           (0)
+#define MCIF_CFG_RD_WEIGHT_1_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_RD_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_RD_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT        (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_RANGE                       (7:0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT        (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_RANGE                      (15:8)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT       (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_RANGE                     (23:16)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT    (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_RANGE                  (31:24)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_WOFFSET                  (0x0)
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_RD_WEIGHT_2_0
+#define MCIF_CFG_RD_WEIGHT_2_0                          (_MK_ADDR_CONST(0x2008))
+#define MCIF_CFG_RD_WEIGHT_2_0_SECURE                                      (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_DUAL                                        (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_SCR                                           (0)
+#define MCIF_CFG_RD_WEIGHT_2_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_RD_WEIGHT_2_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_RD_WEIGHT_2_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_2_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT      (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_RANGE                     (7:0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_WOFFSET                   (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_RANGE                        (15:8)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_WOFFSET                       (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_RANGE                     (23:16)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_RANGE                     (31:24)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_WOFFSET                     (0x0)
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_WR_WEIGHT_0_0
+#define MCIF_CFG_WR_WEIGHT_0_0                          (_MK_ADDR_CONST(0x200c))
+#define MCIF_CFG_WR_WEIGHT_0_0_SECURE                                      (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_DUAL                                        (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_SCR                                           (0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_WR_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_WR_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_RANGE                        (7:0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_WOFFSET                      (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_RANGE                        (15:8)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_WOFFSET                       (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_RANGE                       (23:16)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_WOFFSET                       (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_RANGE                       (31:24)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_WOFFSET                       (0x0)
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_WR_WEIGHT_1_0
+#define MCIF_CFG_WR_WEIGHT_1_0                          (_MK_ADDR_CONST(0x2010))
+#define MCIF_CFG_WR_WEIGHT_1_0_SECURE                                      (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_DUAL                                        (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_SCR                                           (0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WORD_COUNT                                  (0x1)
+#define MCIF_CFG_WR_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define MCIF_CFG_WR_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_RANGE                         (7:0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_WOFFSET                       (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT        (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_RANGE                      (15:8)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_WOFFSET                     (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_RANGE                     (23:16)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_WOFFSET                     (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_RANGE                     (31:24)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_WOFFSET                     (0x0)
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_CFG_OUTSTANDING_CNT_0
+#define MCIF_CFG_OUTSTANDING_CNT_0                      (_MK_ADDR_CONST(0x2014))
+#define MCIF_CFG_OUTSTANDING_CNT_0_SECURE                                  (0x0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_DUAL                                    (0x0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_SCR                                       (0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_WORD_COUNT                              (0x1)
+#define MCIF_CFG_OUTSTANDING_CNT_0_RESET_VAL            (_MK_MASK_CONST(0xffff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RESET_MASK           (_MK_MASK_CONST(0xffff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_READ_MASK            (_MK_MASK_CONST(0xffff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WRITE_MASK           (_MK_MASK_CONST(0xffff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT          (_MK_SHIFT_CONST(0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_RANGE                         (7:0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_WOFFSET                       (0x0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT          (_MK_SHIFT_CONST(8))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD \
+	(_MK_FIELD_CONST(0xff, MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_RANGE                        (15:8)
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_WOFFSET                       (0x0)
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register MCIF_STATUS_0
+#define MCIF_STATUS_0                                   (_MK_ADDR_CONST(0x2018))
+#define MCIF_STATUS_0_SECURE                                               (0x0)
+#define MCIF_STATUS_0_DUAL                                                 (0x0)
+#define MCIF_STATUS_0_SCR                                                    (0)
+#define MCIF_STATUS_0_WORD_COUNT                                           (0x1)
+#define MCIF_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x100))
+#define MCIF_STATUS_0_RESET_MASK                         (_MK_MASK_CONST(0x100))
+#define MCIF_STATUS_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_READ_MASK                          (_MK_MASK_CONST(0x100))
+#define MCIF_STATUS_0_WRITE_MASK                           (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_IDLE_SHIFT                            (_MK_SHIFT_CONST(8))
+#define MCIF_STATUS_0_IDLE_FIELD \
+	(_MK_FIELD_CONST(0x1, MCIF_STATUS_0_IDLE_SHIFT))
+#define MCIF_STATUS_0_IDLE_RANGE                                           (8:8)
+#define MCIF_STATUS_0_IDLE_WOFFSET                                         (0x0)
+#define MCIF_STATUS_0_IDLE_DEFAULT                         (_MK_MASK_CONST(0x1))
+#define MCIF_STATUS_0_IDLE_DEFAULT_MASK                    (_MK_MASK_CONST(0x1))
+#define MCIF_STATUS_0_IDLE_SW_DEFAULT                      (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_IDLE_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_IDLE_PARITY_PROTECTION               (_MK_MASK_CONST(0x0))
+#define MCIF_STATUS_0_IDLE_PLATFORM_DEPENDENT              (_MK_MASK_CONST(0x1))
+#define MCIF_STATUS_0_IDLE_INIT_ENUM                                       (YES)
+#define MCIF_STATUS_0_IDLE_NO                                (_MK_ENUM_CONST(0))
+#define MCIF_STATUS_0_IDLE_YES                               (_MK_ENUM_CONST(1))
+
+
+// Register CVIF_CFG_RD_WEIGHT_0_0
+#define CVIF_CFG_RD_WEIGHT_0_0                          (_MK_ADDR_CONST(0x3000))
+#define CVIF_CFG_RD_WEIGHT_0_0_SECURE                                      (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_DUAL                                        (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_SCR                                           (0)
+#define CVIF_CFG_RD_WEIGHT_0_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_RD_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_RD_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_RANGE                        (7:0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_WOFFSET                      (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_RANGE                        (15:8)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_WOFFSET                       (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_RANGE                       (23:16)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_WOFFSET                       (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_RANGE                       (31:24)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_WOFFSET                       (0x0)
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_RD_WEIGHT_1_0
+#define CVIF_CFG_RD_WEIGHT_1_0                          (_MK_ADDR_CONST(0x3004))
+#define CVIF_CFG_RD_WEIGHT_1_0_SECURE                                      (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_DUAL                                        (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_SCR                                           (0)
+#define CVIF_CFG_RD_WEIGHT_1_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_RD_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_RD_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT        (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_RANGE                       (7:0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT        (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_RANGE                      (15:8)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT       (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_RANGE                     (23:16)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT    (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_RANGE                  (31:24)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_WOFFSET                  (0x0)
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_RD_WEIGHT_2_0
+#define CVIF_CFG_RD_WEIGHT_2_0                          (_MK_ADDR_CONST(0x3008))
+#define CVIF_CFG_RD_WEIGHT_2_0_SECURE                                      (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_DUAL                                        (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_SCR                                           (0)
+#define CVIF_CFG_RD_WEIGHT_2_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_RD_WEIGHT_2_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_RD_WEIGHT_2_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_2_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT      (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_RANGE                     (7:0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_WOFFSET                   (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_RANGE                        (15:8)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_WOFFSET                       (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_RANGE                     (23:16)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_RANGE                     (31:24)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_WOFFSET                     (0x0)
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_WR_WEIGHT_0_0
+#define CVIF_CFG_WR_WEIGHT_0_0                          (_MK_ADDR_CONST(0x300c))
+#define CVIF_CFG_WR_WEIGHT_0_0_SECURE                                      (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_DUAL                                        (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_SCR                                           (0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_WR_WEIGHT_0_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_WR_WEIGHT_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT         (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_RANGE                        (7:0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_WOFFSET                      (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT      (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT          (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_RANGE                        (15:8)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_WOFFSET                       (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT         (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_RANGE                       (23:16)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_WOFFSET                       (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT         (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_RANGE                       (31:24)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_WOFFSET                       (0x0)
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_WR_WEIGHT_1_0
+#define CVIF_CFG_WR_WEIGHT_1_0                          (_MK_ADDR_CONST(0x3010))
+#define CVIF_CFG_WR_WEIGHT_1_0_SECURE                                      (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_DUAL                                        (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_SCR                                           (0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WORD_COUNT                                  (0x1)
+#define CVIF_CFG_WR_WEIGHT_1_0_RESET_VAL             (_MK_MASK_CONST(0x1010101))
+#define CVIF_CFG_WR_WEIGHT_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT          (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_RANGE                         (7:0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_WOFFSET                       (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT       (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT        (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_RANGE                      (15:8)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_WOFFSET                     (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT       (_MK_SHIFT_CONST(16))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_RANGE                     (23:16)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_WOFFSET                     (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT       (_MK_SHIFT_CONST(24))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_RANGE                     (31:24)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_WOFFSET                     (0x0)
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT     (_MK_MASK_CONST(0x1))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_CFG_OUTSTANDING_CNT_0
+#define CVIF_CFG_OUTSTANDING_CNT_0                      (_MK_ADDR_CONST(0x3014))
+#define CVIF_CFG_OUTSTANDING_CNT_0_SECURE                                  (0x0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_DUAL                                    (0x0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_SCR                                       (0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_WORD_COUNT                              (0x1)
+#define CVIF_CFG_OUTSTANDING_CNT_0_RESET_VAL            (_MK_MASK_CONST(0xffff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RESET_MASK           (_MK_MASK_CONST(0xffff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_READ_MASK            (_MK_MASK_CONST(0xffff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WRITE_MASK           (_MK_MASK_CONST(0xffff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT          (_MK_SHIFT_CONST(0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_RANGE                         (7:0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_WOFFSET                       (0x0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT          (_MK_SHIFT_CONST(8))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD \
+	(_MK_FIELD_CONST(0xff, CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_RANGE                        (15:8)
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_WOFFSET                       (0x0)
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT      (_MK_MASK_CONST(0xff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CVIF_STATUS_0
+#define CVIF_STATUS_0                                   (_MK_ADDR_CONST(0x3018))
+#define CVIF_STATUS_0_SECURE                                               (0x0)
+#define CVIF_STATUS_0_DUAL                                                 (0x0)
+#define CVIF_STATUS_0_SCR                                                    (0)
+#define CVIF_STATUS_0_WORD_COUNT                                           (0x1)
+#define CVIF_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x100))
+#define CVIF_STATUS_0_RESET_MASK                         (_MK_MASK_CONST(0x100))
+#define CVIF_STATUS_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_READ_MASK                          (_MK_MASK_CONST(0x100))
+#define CVIF_STATUS_0_WRITE_MASK                           (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_IDLE_SHIFT                            (_MK_SHIFT_CONST(8))
+#define CVIF_STATUS_0_IDLE_FIELD \
+	(_MK_FIELD_CONST(0x1, CVIF_STATUS_0_IDLE_SHIFT))
+#define CVIF_STATUS_0_IDLE_RANGE                                           (8:8)
+#define CVIF_STATUS_0_IDLE_WOFFSET                                         (0x0)
+#define CVIF_STATUS_0_IDLE_DEFAULT                         (_MK_MASK_CONST(0x1))
+#define CVIF_STATUS_0_IDLE_DEFAULT_MASK                    (_MK_MASK_CONST(0x1))
+#define CVIF_STATUS_0_IDLE_SW_DEFAULT                      (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_IDLE_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_IDLE_PARITY_PROTECTION               (_MK_MASK_CONST(0x0))
+#define CVIF_STATUS_0_IDLE_PLATFORM_DEPENDENT              (_MK_MASK_CONST(0x1))
+#define CVIF_STATUS_0_IDLE_INIT_ENUM                                       (YES)
+#define CVIF_STATUS_0_IDLE_NO                                (_MK_ENUM_CONST(0))
+#define CVIF_STATUS_0_IDLE_YES                               (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_SRC_ADDR_LOW_0
+#define BDMA_CFG_SRC_ADDR_LOW_0                         (_MK_ADDR_CONST(0x4000))
+#define BDMA_CFG_SRC_ADDR_LOW_0_SECURE                                     (0x0)
+#define BDMA_CFG_SRC_ADDR_LOW_0_DUAL                                       (0x0)
+#define BDMA_CFG_SRC_ADDR_LOW_0_SCR                                          (0)
+#define BDMA_CFG_SRC_ADDR_LOW_0_WORD_COUNT                                 (0x1)
+#define BDMA_CFG_SRC_ADDR_LOW_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT                   (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_RANGE                                 (31:5)
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_WOFFSET                                (0x0)
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_DEFAULT_MASK     (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_SRC_ADDR_HIGH_0
+#define BDMA_CFG_SRC_ADDR_HIGH_0                        (_MK_ADDR_CONST(0x4004))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_SECURE                                    (0x0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_DUAL                                      (0x0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_SCR                                         (0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_WORD_COUNT                                (0x1)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT                   (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_RANGE                                 (31:0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_WOFFSET                                (0x0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_DEFAULT_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_DST_ADDR_LOW_0
+#define BDMA_CFG_DST_ADDR_LOW_0                         (_MK_ADDR_CONST(0x4008))
+#define BDMA_CFG_DST_ADDR_LOW_0_SECURE                                     (0x0)
+#define BDMA_CFG_DST_ADDR_LOW_0_DUAL                                       (0x0)
+#define BDMA_CFG_DST_ADDR_LOW_0_SCR                                          (0)
+#define BDMA_CFG_DST_ADDR_LOW_0_WORD_COUNT                                 (0x1)
+#define BDMA_CFG_DST_ADDR_LOW_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_ADDR_LOW_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_ADDR_LOW_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT                   (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_RANGE                                 (31:5)
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_WOFFSET                                (0x0)
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_DEFAULT_MASK     (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_DST_ADDR_HIGH_0
+#define BDMA_CFG_DST_ADDR_HIGH_0                        (_MK_ADDR_CONST(0x400c))
+#define BDMA_CFG_DST_ADDR_HIGH_0_SECURE                                    (0x0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_DUAL                                      (0x0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_SCR                                         (0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_WORD_COUNT                                (0x1)
+#define BDMA_CFG_DST_ADDR_HIGH_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_DST_ADDR_HIGH_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_DST_ADDR_HIGH_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT                   (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_RANGE                                 (31:0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_WOFFSET                                (0x0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_DEFAULT_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_LINE_0
+#define BDMA_CFG_LINE_0                                 (_MK_ADDR_CONST(0x4010))
+#define BDMA_CFG_LINE_0_SECURE                                             (0x0)
+#define BDMA_CFG_LINE_0_DUAL                                               (0x0)
+#define BDMA_CFG_LINE_0_SCR                                                  (0)
+#define BDMA_CFG_LINE_0_WORD_COUNT                                         (0x1)
+#define BDMA_CFG_LINE_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_RESET_MASK                      (_MK_MASK_CONST(0x1fff))
+#define BDMA_CFG_LINE_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_READ_MASK                       (_MK_MASK_CONST(0x1fff))
+#define BDMA_CFG_LINE_0_WRITE_MASK                      (_MK_MASK_CONST(0x1fff))
+#define BDMA_CFG_LINE_0_SIZE_SHIFT                          (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_LINE_0_SIZE_FIELD \
+	(_MK_FIELD_CONST(0x1fff, BDMA_CFG_LINE_0_SIZE_SHIFT))
+#define BDMA_CFG_LINE_0_SIZE_RANGE                                        (12:0)
+#define BDMA_CFG_LINE_0_SIZE_WOFFSET                                       (0x0)
+#define BDMA_CFG_LINE_0_SIZE_DEFAULT                       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SIZE_DEFAULT_MASK               (_MK_MASK_CONST(0x1fff))
+#define BDMA_CFG_LINE_0_SIZE_SW_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SIZE_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SIZE_PARITY_PROTECTION             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_0_SIZE_PLATFORM_DEPENDENT            (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_CMD_0
+#define BDMA_CFG_CMD_0                                  (_MK_ADDR_CONST(0x4014))
+#define BDMA_CFG_CMD_0_SECURE                                              (0x0)
+#define BDMA_CFG_CMD_0_DUAL                                                (0x0)
+#define BDMA_CFG_CMD_0_SCR                                                   (0)
+#define BDMA_CFG_CMD_0_WORD_COUNT                                          (0x1)
+#define BDMA_CFG_CMD_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_RESET_MASK                          (_MK_MASK_CONST(0x3))
+#define BDMA_CFG_CMD_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_READ_MASK                           (_MK_MASK_CONST(0x3))
+#define BDMA_CFG_CMD_0_WRITE_MASK                          (_MK_MASK_CONST(0x3))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT                   (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_RANGE                                  (0:0)
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_WOFFSET                                (0x0)
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_CVSRAM                   (_MK_ENUM_CONST(0))
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_MC                       (_MK_ENUM_CONST(1))
+
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT                   (_MK_SHIFT_CONST(1))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_RANGE                                  (1:1)
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_WOFFSET                                (0x0)
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_CVSRAM                   (_MK_ENUM_CONST(0))
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_MC                       (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_LINE_REPEAT_0
+#define BDMA_CFG_LINE_REPEAT_0                          (_MK_ADDR_CONST(0x4018))
+#define BDMA_CFG_LINE_REPEAT_0_SECURE                                      (0x0)
+#define BDMA_CFG_LINE_REPEAT_0_DUAL                                        (0x0)
+#define BDMA_CFG_LINE_REPEAT_0_SCR                                           (0)
+#define BDMA_CFG_LINE_REPEAT_0_WORD_COUNT                                  (0x1)
+#define BDMA_CFG_LINE_REPEAT_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_RESET_MASK             (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_LINE_REPEAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_READ_MASK              (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_LINE_REPEAT_0_WRITE_MASK             (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_FIELD \
+	(_MK_FIELD_CONST(0xffffff, BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_RANGE                               (23:0)
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_WOFFSET                              (0x0)
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_DEFAULT_MASK    (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_SRC_LINE_0
+#define BDMA_CFG_SRC_LINE_0                             (_MK_ADDR_CONST(0x401c))
+#define BDMA_CFG_SRC_LINE_0_SECURE                                         (0x0)
+#define BDMA_CFG_SRC_LINE_0_DUAL                                           (0x0)
+#define BDMA_CFG_SRC_LINE_0_SCR                                              (0)
+#define BDMA_CFG_SRC_LINE_0_WORD_COUNT                                     (0x1)
+#define BDMA_CFG_SRC_LINE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_LINE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_LINE_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_RANGE                                  (31:5)
+#define BDMA_CFG_SRC_LINE_0_STRIDE_WOFFSET                                 (0x0)
+#define BDMA_CFG_SRC_LINE_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_LINE_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_DST_LINE_0
+#define BDMA_CFG_DST_LINE_0                             (_MK_ADDR_CONST(0x4020))
+#define BDMA_CFG_DST_LINE_0_SECURE                                         (0x0)
+#define BDMA_CFG_DST_LINE_0_DUAL                                           (0x0)
+#define BDMA_CFG_DST_LINE_0_SCR                                              (0)
+#define BDMA_CFG_DST_LINE_0_WORD_COUNT                                     (0x1)
+#define BDMA_CFG_DST_LINE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_LINE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_LINE_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_DST_LINE_0_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_LINE_0_STRIDE_SHIFT))
+#define BDMA_CFG_DST_LINE_0_STRIDE_RANGE                                  (31:5)
+#define BDMA_CFG_DST_LINE_0_STRIDE_WOFFSET                                 (0x0)
+#define BDMA_CFG_DST_LINE_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_DST_LINE_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_LINE_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_SURF_REPEAT_0
+#define BDMA_CFG_SURF_REPEAT_0                          (_MK_ADDR_CONST(0x4024))
+#define BDMA_CFG_SURF_REPEAT_0_SECURE                                      (0x0)
+#define BDMA_CFG_SURF_REPEAT_0_DUAL                                        (0x0)
+#define BDMA_CFG_SURF_REPEAT_0_SCR                                           (0)
+#define BDMA_CFG_SURF_REPEAT_0_WORD_COUNT                                  (0x1)
+#define BDMA_CFG_SURF_REPEAT_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_RESET_MASK             (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_SURF_REPEAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_READ_MASK              (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_SURF_REPEAT_0_WRITE_MASK             (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_FIELD \
+	(_MK_FIELD_CONST(0xffffff, BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_RANGE                               (23:0)
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_WOFFSET                              (0x0)
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_DEFAULT_MASK    (_MK_MASK_CONST(0xffffff))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_SRC_SURF_0
+#define BDMA_CFG_SRC_SURF_0                             (_MK_ADDR_CONST(0x4028))
+#define BDMA_CFG_SRC_SURF_0_SECURE                                         (0x0)
+#define BDMA_CFG_SRC_SURF_0_DUAL                                           (0x0)
+#define BDMA_CFG_SRC_SURF_0_SCR                                              (0)
+#define BDMA_CFG_SRC_SURF_0_WORD_COUNT                                     (0x1)
+#define BDMA_CFG_SRC_SURF_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_SURF_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_SURF_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_RANGE                                  (31:5)
+#define BDMA_CFG_SRC_SURF_0_STRIDE_WOFFSET                                 (0x0)
+#define BDMA_CFG_SRC_SURF_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_SRC_SURF_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_DST_SURF_0
+#define BDMA_CFG_DST_SURF_0                             (_MK_ADDR_CONST(0x402c))
+#define BDMA_CFG_DST_SURF_0_SECURE                                         (0x0)
+#define BDMA_CFG_DST_SURF_0_DUAL                                           (0x0)
+#define BDMA_CFG_DST_SURF_0_SCR                                              (0)
+#define BDMA_CFG_DST_SURF_0_WORD_COUNT                                     (0x1)
+#define BDMA_CFG_DST_SURF_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_RESET_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_SURF_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_READ_MASK               (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_SURF_0_WRITE_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_SHIFT                    (_MK_SHIFT_CONST(5))
+#define BDMA_CFG_DST_SURF_0_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_SURF_0_STRIDE_SHIFT))
+#define BDMA_CFG_DST_SURF_0_STRIDE_RANGE                                  (31:5)
+#define BDMA_CFG_DST_SURF_0_STRIDE_WOFFSET                                 (0x0)
+#define BDMA_CFG_DST_SURF_0_STRIDE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_DEFAULT_MASK      (_MK_MASK_CONST(0x7ffffff))
+#define BDMA_CFG_DST_SURF_0_STRIDE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_DST_SURF_0_STRIDE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_CFG_OP_0
+#define BDMA_CFG_OP_0                                   (_MK_ADDR_CONST(0x4030))
+#define BDMA_CFG_OP_0_SECURE                                               (0x0)
+#define BDMA_CFG_OP_0_DUAL                                                 (0x0)
+#define BDMA_CFG_OP_0_SCR                                                    (0)
+#define BDMA_CFG_OP_0_WORD_COUNT                                           (0x1)
+#define BDMA_CFG_OP_0_RESET_VAL                            (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_RESET_MASK                           (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_READ_MASK                            (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_WRITE_MASK                           (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_EN_SHIFT                              (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_OP_0_EN_FIELD    (_MK_FIELD_CONST(0x1, BDMA_CFG_OP_0_EN_SHIFT))
+#define BDMA_CFG_OP_0_EN_RANGE                                             (0:0)
+#define BDMA_CFG_OP_0_EN_WOFFSET                                           (0x0)
+#define BDMA_CFG_OP_0_EN_DEFAULT                           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_EN_DEFAULT_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_EN_SW_DEFAULT                        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_EN_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_EN_PARITY_PROTECTION                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_OP_0_EN_PLATFORM_DEPENDENT                (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_OP_0_EN_DISABLE                             (_MK_ENUM_CONST(0))
+#define BDMA_CFG_OP_0_EN_ENABLE                              (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_LAUNCH0_0
+#define BDMA_CFG_LAUNCH0_0                              (_MK_ADDR_CONST(0x4034))
+#define BDMA_CFG_LAUNCH0_0_SECURE                                          (0x0)
+#define BDMA_CFG_LAUNCH0_0_DUAL                                            (0x0)
+#define BDMA_CFG_LAUNCH0_0_SCR                                               (0)
+#define BDMA_CFG_LAUNCH0_0_WORD_COUNT                                      (0x1)
+#define BDMA_CFG_LAUNCH0_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_READ_MASK                       (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT                (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_RANGE                               (0:0)
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_WOFFSET                             (0x0)
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_NO                    (_MK_ENUM_CONST(0))
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_YES                   (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_LAUNCH1_0
+#define BDMA_CFG_LAUNCH1_0                              (_MK_ADDR_CONST(0x4038))
+#define BDMA_CFG_LAUNCH1_0_SECURE                                          (0x0)
+#define BDMA_CFG_LAUNCH1_0_DUAL                                            (0x0)
+#define BDMA_CFG_LAUNCH1_0_SCR                                               (0)
+#define BDMA_CFG_LAUNCH1_0_WORD_COUNT                                      (0x1)
+#define BDMA_CFG_LAUNCH1_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_READ_MASK                       (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT                (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_RANGE                               (0:0)
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_WOFFSET                             (0x0)
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_DEFAULT             (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_NO                    (_MK_ENUM_CONST(0))
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_YES                   (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_CFG_STATUS_0
+#define BDMA_CFG_STATUS_0                               (_MK_ADDR_CONST(0x403c))
+#define BDMA_CFG_STATUS_0_SECURE                                           (0x0)
+#define BDMA_CFG_STATUS_0_DUAL                                             (0x0)
+#define BDMA_CFG_STATUS_0_SCR                                                (0)
+#define BDMA_CFG_STATUS_0_WORD_COUNT                                       (0x1)
+#define BDMA_CFG_STATUS_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT              (_MK_SHIFT_CONST(0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_RANGE                             (0:0)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_WOFFSET                           (0x0)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_DEFAULT           (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_INIT_ENUM                          (NO)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_NO                  (_MK_ENUM_CONST(0))
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_YES                 (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_STATUS_0
+#define BDMA_STATUS_0                                   (_MK_ADDR_CONST(0x4040))
+#define BDMA_STATUS_0_SECURE                                               (0x0)
+#define BDMA_STATUS_0_DUAL                                                 (0x0)
+#define BDMA_STATUS_0_SCR                                                    (0)
+#define BDMA_STATUS_0_WORD_COUNT                                           (0x1)
+#define BDMA_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x114))
+#define BDMA_STATUS_0_RESET_MASK                         (_MK_MASK_CONST(0x7ff))
+#define BDMA_STATUS_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_READ_MASK                          (_MK_MASK_CONST(0x7ff))
+#define BDMA_STATUS_0_WRITE_MASK                           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_FREE_SLOT_SHIFT                       (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_0_FREE_SLOT_FIELD \
+	(_MK_FIELD_CONST(0xff, BDMA_STATUS_0_FREE_SLOT_SHIFT))
+#define BDMA_STATUS_0_FREE_SLOT_RANGE                                      (7:0)
+#define BDMA_STATUS_0_FREE_SLOT_WOFFSET                                    (0x0)
+#define BDMA_STATUS_0_FREE_SLOT_DEFAULT                   (_MK_MASK_CONST(0x14))
+#define BDMA_STATUS_0_FREE_SLOT_DEFAULT_MASK              (_MK_MASK_CONST(0xff))
+#define BDMA_STATUS_0_FREE_SLOT_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_FREE_SLOT_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_FREE_SLOT_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_FREE_SLOT_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+
+#define BDMA_STATUS_0_IDLE_SHIFT                            (_MK_SHIFT_CONST(8))
+#define BDMA_STATUS_0_IDLE_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_STATUS_0_IDLE_SHIFT))
+#define BDMA_STATUS_0_IDLE_RANGE                                           (8:8)
+#define BDMA_STATUS_0_IDLE_WOFFSET                                         (0x0)
+#define BDMA_STATUS_0_IDLE_DEFAULT                         (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_IDLE_DEFAULT_MASK                    (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_IDLE_SW_DEFAULT                      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_IDLE_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_IDLE_PARITY_PROTECTION               (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_IDLE_PLATFORM_DEPENDENT              (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_IDLE_INIT_ENUM                                       (YES)
+#define BDMA_STATUS_0_IDLE_NO                                (_MK_ENUM_CONST(0))
+#define BDMA_STATUS_0_IDLE_YES                               (_MK_ENUM_CONST(1))
+
+#define BDMA_STATUS_0_GRP0_BUSY_SHIFT                       (_MK_SHIFT_CONST(9))
+#define BDMA_STATUS_0_GRP0_BUSY_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP0_BUSY_SHIFT))
+#define BDMA_STATUS_0_GRP0_BUSY_RANGE                                      (9:9)
+#define BDMA_STATUS_0_GRP0_BUSY_WOFFSET                                    (0x0)
+#define BDMA_STATUS_0_GRP0_BUSY_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP0_BUSY_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_GRP0_BUSY_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP0_BUSY_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP0_BUSY_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP0_BUSY_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_GRP0_BUSY_INIT_ENUM                                   (NO)
+#define BDMA_STATUS_0_GRP0_BUSY_NO                           (_MK_ENUM_CONST(0))
+#define BDMA_STATUS_0_GRP0_BUSY_YES                          (_MK_ENUM_CONST(1))
+
+#define BDMA_STATUS_0_GRP1_BUSY_SHIFT                      (_MK_SHIFT_CONST(10))
+#define BDMA_STATUS_0_GRP1_BUSY_FIELD \
+	(_MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP1_BUSY_SHIFT))
+#define BDMA_STATUS_0_GRP1_BUSY_RANGE                                    (10:10)
+#define BDMA_STATUS_0_GRP1_BUSY_WOFFSET                                    (0x0)
+#define BDMA_STATUS_0_GRP1_BUSY_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP1_BUSY_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_GRP1_BUSY_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP1_BUSY_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP1_BUSY_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_0_GRP1_BUSY_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define BDMA_STATUS_0_GRP1_BUSY_INIT_ENUM                                   (NO)
+#define BDMA_STATUS_0_GRP1_BUSY_NO                           (_MK_ENUM_CONST(0))
+#define BDMA_STATUS_0_GRP1_BUSY_YES                          (_MK_ENUM_CONST(1))
+
+
+// Register BDMA_STATUS_GRP0_READ_STALL_0
+#define BDMA_STATUS_GRP0_READ_STALL_0                   (_MK_ADDR_CONST(0x4044))
+#define BDMA_STATUS_GRP0_READ_STALL_0_SECURE                               (0x0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_DUAL                                 (0x0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_SCR                                    (0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_WORD_COUNT                           (0x1)
+#define BDMA_STATUS_GRP0_READ_STALL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_READ_STALL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_READ_STALL_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT           (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_RANGE                         (31:0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_WOFFSET                        (0x0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_STATUS_GRP0_WRITE_STALL_0
+#define BDMA_STATUS_GRP0_WRITE_STALL_0                  (_MK_ADDR_CONST(0x4048))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_SECURE                              (0x0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_DUAL                                (0x0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_SCR                                   (0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_WORD_COUNT                          (0x1)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_WRITE_MASK          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT          (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_RANGE                        (31:0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_WOFFSET                       (0x0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_STATUS_GRP1_READ_STALL_0
+#define BDMA_STATUS_GRP1_READ_STALL_0                   (_MK_ADDR_CONST(0x404c))
+#define BDMA_STATUS_GRP1_READ_STALL_0_SECURE                               (0x0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_DUAL                                 (0x0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_SCR                                    (0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_WORD_COUNT                           (0x1)
+#define BDMA_STATUS_GRP1_READ_STALL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_READ_STALL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_READ_STALL_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT           (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_RANGE                         (31:0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_WOFFSET                        (0x0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register BDMA_STATUS_GRP1_WRITE_STALL_0
+#define BDMA_STATUS_GRP1_WRITE_STALL_0                  (_MK_ADDR_CONST(0x4050))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_SECURE                              (0x0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_DUAL                                (0x0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_SCR                                   (0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_WORD_COUNT                          (0x1)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_WRITE_MASK          (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT          (_MK_SHIFT_CONST(0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_RANGE                        (31:0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_WOFFSET                       (0x0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_S_STATUS_0
+#define CDMA_S_STATUS_0                                 (_MK_ADDR_CONST(0x5000))
+#define CDMA_S_STATUS_0_SECURE                                             (0x0)
+#define CDMA_S_STATUS_0_DUAL                                               (0x0)
+#define CDMA_S_STATUS_0_SCR                                                  (0)
+#define CDMA_S_STATUS_0_WORD_COUNT                                         (0x1)
+#define CDMA_S_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_RESET_MASK                     (_MK_MASK_CONST(0x30003))
+#define CDMA_S_STATUS_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_READ_MASK                      (_MK_MASK_CONST(0x30003))
+#define CDMA_S_STATUS_0_WRITE_MASK                         (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CDMA_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_0_SHIFT))
+#define CDMA_S_STATUS_0_STATUS_0_RANGE                                     (1:0)
+#define CDMA_S_STATUS_0_STATUS_0_WOFFSET                                   (0x0)
+#define CDMA_S_STATUS_0_STATUS_0_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
+#define CDMA_S_STATUS_0_STATUS_0_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CDMA_S_STATUS_0_STATUS_0_INIT_ENUM                                (IDLE)
+#define CDMA_S_STATUS_0_STATUS_0_IDLE                        (_MK_ENUM_CONST(0))
+#define CDMA_S_STATUS_0_STATUS_0_RUNNING                     (_MK_ENUM_CONST(1))
+#define CDMA_S_STATUS_0_STATUS_0_PENDING                     (_MK_ENUM_CONST(2))
+
+#define CDMA_S_STATUS_0_STATUS_1_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CDMA_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_1_SHIFT))
+#define CDMA_S_STATUS_0_STATUS_1_RANGE                                   (17:16)
+#define CDMA_S_STATUS_0_STATUS_1_WOFFSET                                   (0x0)
+#define CDMA_S_STATUS_0_STATUS_1_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
+#define CDMA_S_STATUS_0_STATUS_1_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CDMA_S_STATUS_0_STATUS_1_INIT_ENUM                                (IDLE)
+#define CDMA_S_STATUS_0_STATUS_1_IDLE                        (_MK_ENUM_CONST(0))
+#define CDMA_S_STATUS_0_STATUS_1_RUNNING                     (_MK_ENUM_CONST(1))
+#define CDMA_S_STATUS_0_STATUS_1_PENDING                     (_MK_ENUM_CONST(2))
+
+
+// Register CDMA_S_POINTER_0
+#define CDMA_S_POINTER_0                                (_MK_ADDR_CONST(0x5004))
+#define CDMA_S_POINTER_0_SECURE                                            (0x0)
+#define CDMA_S_POINTER_0_DUAL                                              (0x0)
+#define CDMA_S_POINTER_0_SCR                                                 (0)
+#define CDMA_S_POINTER_0_WORD_COUNT                                        (0x1)
+#define CDMA_S_POINTER_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_RESET_MASK                    (_MK_MASK_CONST(0x10001))
+#define CDMA_S_POINTER_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_READ_MASK                     (_MK_MASK_CONST(0x10001))
+#define CDMA_S_POINTER_0_WRITE_MASK                        (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_PRODUCER_SHIFT                     (_MK_SHIFT_CONST(0))
+#define CDMA_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_PRODUCER_SHIFT))
+#define CDMA_S_POINTER_0_PRODUCER_RANGE                                    (0:0)
+#define CDMA_S_POINTER_0_PRODUCER_WOFFSET                                  (0x0)
+#define CDMA_S_POINTER_0_PRODUCER_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_PRODUCER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_PRODUCER_INIT_ENUM                            (GROUP_0)
+#define CDMA_S_POINTER_0_PRODUCER_GROUP_0                    (_MK_ENUM_CONST(0))
+#define CDMA_S_POINTER_0_PRODUCER_GROUP_1                    (_MK_ENUM_CONST(1))
+
+#define CDMA_S_POINTER_0_CONSUMER_SHIFT                    (_MK_SHIFT_CONST(16))
+#define CDMA_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_CONSUMER_SHIFT))
+#define CDMA_S_POINTER_0_CONSUMER_RANGE                                  (16:16)
+#define CDMA_S_POINTER_0_CONSUMER_WOFFSET                                  (0x0)
+#define CDMA_S_POINTER_0_CONSUMER_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_CONSUMER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+#define CDMA_S_POINTER_0_CONSUMER_INIT_ENUM                            (GROUP_0)
+#define CDMA_S_POINTER_0_CONSUMER_GROUP_0                    (_MK_ENUM_CONST(0))
+#define CDMA_S_POINTER_0_CONSUMER_GROUP_1                    (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_S_ARBITER_0
+#define CDMA_S_ARBITER_0                                (_MK_ADDR_CONST(0x5008))
+#define CDMA_S_ARBITER_0_SECURE                                            (0x0)
+#define CDMA_S_ARBITER_0_DUAL                                              (0x0)
+#define CDMA_S_ARBITER_0_SCR                                                 (0)
+#define CDMA_S_ARBITER_0_WORD_COUNT                                        (0x1)
+#define CDMA_S_ARBITER_0_RESET_VAL                     (_MK_MASK_CONST(0x3000f))
+#define CDMA_S_ARBITER_0_RESET_MASK                    (_MK_MASK_CONST(0xf000f))
+#define CDMA_S_ARBITER_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_READ_MASK                     (_MK_MASK_CONST(0xf000f))
+#define CDMA_S_ARBITER_0_WRITE_MASK                    (_MK_MASK_CONST(0xf000f))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_FIELD \
+	(_MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_RANGE                                  (3:0)
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_WOFFSET                                (0x0)
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_DEFAULT                (_MK_MASK_CONST(0xf))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_DEFAULT_MASK           (_MK_MASK_CONST(0xf))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+#define CDMA_S_ARBITER_0_ARB_WMB_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CDMA_S_ARBITER_0_ARB_WMB_FIELD \
+	(_MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WMB_SHIFT))
+#define CDMA_S_ARBITER_0_ARB_WMB_RANGE                                   (19:16)
+#define CDMA_S_ARBITER_0_ARB_WMB_WOFFSET                                   (0x0)
+#define CDMA_S_ARBITER_0_ARB_WMB_DEFAULT                   (_MK_MASK_CONST(0x3))
+#define CDMA_S_ARBITER_0_ARB_WMB_DEFAULT_MASK              (_MK_MASK_CONST(0xf))
+#define CDMA_S_ARBITER_0_ARB_WMB_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WMB_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WMB_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDMA_S_ARBITER_0_ARB_WMB_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_S_CBUF_FLUSH_STATUS_0
+#define CDMA_S_CBUF_FLUSH_STATUS_0                      (_MK_ADDR_CONST(0x500c))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_SECURE                                  (0x0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_DUAL                                    (0x0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_SCR                                       (0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_WORD_COUNT                              (0x1)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_RESET_MASK              (_MK_MASK_CONST(0x1))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_READ_MASK               (_MK_MASK_CONST(0x1))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_WRITE_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_RANGE                        (0:0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_WOFFSET                      (0x0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_OP_ENABLE_0
+#define CDMA_D_OP_ENABLE_0                              (_MK_ADDR_CONST(0x5010))
+#define CDMA_D_OP_ENABLE_0_SECURE                                          (0x0)
+#define CDMA_D_OP_ENABLE_0_DUAL                                            (0x0)
+#define CDMA_D_OP_ENABLE_0_SCR                                               (0)
+#define CDMA_D_OP_ENABLE_0_WORD_COUNT                                      (0x1)
+#define CDMA_D_OP_ENABLE_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_READ_MASK                       (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_OP_EN_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CDMA_D_OP_ENABLE_0_OP_EN_RANGE                                     (0:0)
+#define CDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                                   (0x0)
+#define CDMA_D_OP_ENABLE_0_OP_EN_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                             (DISABLE)
+#define CDMA_D_OP_ENABLE_0_OP_EN_DISABLE                     (_MK_ENUM_CONST(0))
+#define CDMA_D_OP_ENABLE_0_OP_EN_ENABLE                      (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_MISC_CFG_0
+#define CDMA_D_MISC_CFG_0                               (_MK_ADDR_CONST(0x5014))
+#define CDMA_D_MISC_CFG_0_SECURE                                           (0x0)
+#define CDMA_D_MISC_CFG_0_DUAL                                             (0x0)
+#define CDMA_D_MISC_CFG_0_SCR                                                (0)
+#define CDMA_D_MISC_CFG_0_WORD_COUNT                                       (0x1)
+#define CDMA_D_MISC_CFG_0_RESET_VAL                     (_MK_MASK_CONST(0x1100))
+#define CDMA_D_MISC_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x11113301))
+#define CDMA_D_MISC_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x11113301))
+#define CDMA_D_MISC_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x11113301))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_RANGE                                  (0:0)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_WOFFSET                                (0x0)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                           (DIRECT)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_DIRECT                   (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_CONV_MODE_WINOGRAD                 (_MK_ENUM_CONST(1))
+
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT                (_MK_SHIFT_CONST(8))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_RANGE                               (9:8)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_WOFFSET                             (0x0)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_DEFAULT             (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_DEFAULT_MASK        (_MK_MASK_CONST(0x3))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_INIT_ENUM                         (INT16)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT8                  (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT16                 (_MK_ENUM_CONST(1))
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_FP16                  (_MK_ENUM_CONST(2))
+
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT             (_MK_SHIFT_CONST(12))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_RANGE                           (13:12)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                           (0x0)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_DEFAULT           (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK      (_MK_MASK_CONST(0x3))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                       (INT16)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT8                (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT16               (_MK_ENUM_CONST(1))
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FP16                (_MK_ENUM_CONST(2))
+
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT                 (_MK_SHIFT_CONST(16))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_RANGE                               (16:16)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_WOFFSET                               (0x0)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_INIT_ENUM                         (DISABLE)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_DISABLE                 (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_ENABLE                  (_MK_ENUM_CONST(1))
+
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT               (_MK_SHIFT_CONST(20))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_RANGE                             (20:20)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_WOFFSET                             (0x0)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_INIT_ENUM                       (DISABLE)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE               (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE                (_MK_ENUM_CONST(1))
+
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT              (_MK_SHIFT_CONST(24))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_RANGE                            (24:24)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_WOFFSET                            (0x0)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_INIT_ENUM                      (DISABLE)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE              (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE               (_MK_ENUM_CONST(1))
+
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT            (_MK_SHIFT_CONST(28))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_RANGE                          (28:28)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_WOFFSET                          (0x0)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_INIT_ENUM                    (DISABLE)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE            (_MK_ENUM_CONST(0))
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE             (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_DATAIN_FORMAT_0
+#define CDMA_D_DATAIN_FORMAT_0                          (_MK_ADDR_CONST(0x5018))
+#define CDMA_D_DATAIN_FORMAT_0_SECURE                                      (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_DUAL                                        (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_SCR                                           (0)
+#define CDMA_D_DATAIN_FORMAT_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_DATAIN_FORMAT_0_RESET_VAL                 (_MK_MASK_CONST(0xc00))
+#define CDMA_D_DATAIN_FORMAT_0_RESET_MASK             (_MK_MASK_CONST(0x113f01))
+#define CDMA_D_DATAIN_FORMAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_READ_MASK              (_MK_MASK_CONST(0x113f01))
+#define CDMA_D_DATAIN_FORMAT_0_WRITE_MASK             (_MK_MASK_CONST(0x113f01))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_RANGE                         (0:0)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_WOFFSET                       (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_INIT_ENUM                 (FEATURE)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE         (_MK_ENUM_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL           (_MK_ENUM_CONST(1))
+
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT           (_MK_SHIFT_CONST(8))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x3f, CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_RANGE                         (13:8)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_WOFFSET                        (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_DEFAULT        (_MK_MASK_CONST(0xc))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_INIT_ENUM               (T_A8B8G8R8)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8             (_MK_ENUM_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10            (_MK_ENUM_CONST(1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R12            (_MK_ENUM_CONST(2))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16            (_MK_ENUM_CONST(3))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_I          (_MK_ENUM_CONST(4))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_F          (_MK_ENUM_CONST(5))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16 \
+	(_MK_ENUM_CONST(6))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X16B16G16R16 \
+	(_MK_ENUM_CONST(7))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16_F \
+	(_MK_ENUM_CONST(8))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16 \
+	(_MK_ENUM_CONST(9))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V16U16Y16A16 \
+	(_MK_ENUM_CONST(10))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16_F \
+	(_MK_ENUM_CONST(11))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8B8G8R8      (_MK_ENUM_CONST(12))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8R8G8B8      (_MK_ENUM_CONST(13))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8A8      (_MK_ENUM_CONST(14))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8A8      (_MK_ENUM_CONST(15))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8B8G8R8      (_MK_ENUM_CONST(16))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8R8G8B8      (_MK_ENUM_CONST(17))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8X8      (_MK_ENUM_CONST(18))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8X8      (_MK_ENUM_CONST(19))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2B10G10R10 \
+	(_MK_ENUM_CONST(20))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2R10G10B10 \
+	(_MK_ENUM_CONST(21))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B10G10R10A2 \
+	(_MK_ENUM_CONST(22))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10G10B10A2 \
+	(_MK_ENUM_CONST(23))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2Y10U10V10 \
+	(_MK_ENUM_CONST(24))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V10U10Y10A2 \
+	(_MK_ENUM_CONST(25))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8Y8U8V8      (_MK_ENUM_CONST(26))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V8U8Y8A8      (_MK_ENUM_CONST(27))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___U8V8_N444 \
+	(_MK_ENUM_CONST(28))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___V8U8_N444 \
+	(_MK_ENUM_CONST(29))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___U10V10_N444 \
+	(_MK_ENUM_CONST(30))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___V10U10_N444 \
+	(_MK_ENUM_CONST(31))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___U12V12_N444 \
+	(_MK_ENUM_CONST(32))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___V12U12_N444 \
+	(_MK_ENUM_CONST(33))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___U16V16_N444 \
+	(_MK_ENUM_CONST(34))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___V16U16_N444 \
+	(_MK_ENUM_CONST(35))
+
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT         (_MK_SHIFT_CONST(16))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RANGE                       (16:16)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_WOFFSET                       (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_INIT_ENUM            (PITCH_LINEAR)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PITCH_LINEAR    (_MK_ENUM_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RESERVED_LINEAR \
+	(_MK_ENUM_CONST(1))
+
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_RANGE                 (20:20)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_WOFFSET                 (0x0)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_INIT_ENUM      (UNSIGNED_INT)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_UNSIGNED_INT \
+	(_MK_ENUM_CONST(0))
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SIGNED_INT \
+	(_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_DATAIN_SIZE_0_0
+#define CDMA_D_DATAIN_SIZE_0_0                          (_MK_ADDR_CONST(0x501c))
+#define CDMA_D_DATAIN_SIZE_0_0_SECURE                                      (0x0)
+#define CDMA_D_DATAIN_SIZE_0_0_DUAL                                        (0x0)
+#define CDMA_D_DATAIN_SIZE_0_0_SCR                                           (0)
+#define CDMA_D_DATAIN_SIZE_0_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_DATAIN_SIZE_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_RESET_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_READ_MASK            (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_WRITE_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT           (_MK_SHIFT_CONST(0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_RANGE                         (12:0)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_WOFFSET                        (0x0)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT         (_MK_SHIFT_CONST(16))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_RANGE                       (28:16)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_WOFFSET                       (0x0)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DATAIN_SIZE_1_0
+#define CDMA_D_DATAIN_SIZE_1_0                          (_MK_ADDR_CONST(0x5020))
+#define CDMA_D_DATAIN_SIZE_1_0_SECURE                                      (0x0)
+#define CDMA_D_DATAIN_SIZE_1_0_DUAL                                        (0x0)
+#define CDMA_D_DATAIN_SIZE_1_0_SCR                                           (0)
+#define CDMA_D_DATAIN_SIZE_1_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_DATAIN_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_RANGE                       (12:0)
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_WOFFSET                      (0x0)
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DATAIN_SIZE_EXT_0_0
+#define CDMA_D_DATAIN_SIZE_EXT_0_0                      (_MK_ADDR_CONST(0x5024))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_SECURE                                  (0x0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DUAL                                    (0x0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_SCR                                       (0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_WORD_COUNT                              (0x1)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_RESET_MASK       (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_READ_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_WRITE_MASK       (_MK_MASK_CONST(0x1fff1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_RANGE                 (12:0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_WOFFSET                (0x0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_RANGE               (28:16)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_WOFFSET               (0x0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PIXEL_OFFSET_0
+#define CDMA_D_PIXEL_OFFSET_0                           (_MK_ADDR_CONST(0x5028))
+#define CDMA_D_PIXEL_OFFSET_0_SECURE                                       (0x0)
+#define CDMA_D_PIXEL_OFFSET_0_DUAL                                         (0x0)
+#define CDMA_D_PIXEL_OFFSET_0_SCR                                            (0)
+#define CDMA_D_PIXEL_OFFSET_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_PIXEL_OFFSET_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_RESET_MASK               (_MK_MASK_CONST(0x7001f))
+#define CDMA_D_PIXEL_OFFSET_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_READ_MASK                (_MK_MASK_CONST(0x7001f))
+#define CDMA_D_PIXEL_OFFSET_0_WRITE_MASK               (_MK_MASK_CONST(0x7001f))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_RANGE                         (4:0)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_WOFFSET                       (0x0)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT         (_MK_SHIFT_CONST(16))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0x7, CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_RANGE                       (18:16)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_WOFFSET                       (0x0)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_RAM_TYPE_0
+#define CDMA_D_DAIN_RAM_TYPE_0                          (_MK_ADDR_CONST(0x502c))
+#define CDMA_D_DAIN_RAM_TYPE_0_SECURE                                      (0x0)
+#define CDMA_D_DAIN_RAM_TYPE_0_DUAL                                        (0x0)
+#define CDMA_D_DAIN_RAM_TYPE_0_SCR                                           (0)
+#define CDMA_D_DAIN_RAM_TYPE_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_DAIN_RAM_TYPE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT        (_MK_SHIFT_CONST(0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_RANGE                       (0:0)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_WOFFSET                     (0x0)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_INIT_ENUM                  (CVIF)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF          (_MK_ENUM_CONST(0))
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF          (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_DAIN_ADDR_HIGH_0_0
+#define CDMA_D_DAIN_ADDR_HIGH_0_0                       (_MK_ADDR_CONST(0x5030))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_SECURE                                   (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DUAL                                     (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_SCR                                        (0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_WORD_COUNT                               (0x1)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_RESET_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_READ_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_RANGE                (31:0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_WOFFSET               (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_ADDR_LOW_0_0
+#define CDMA_D_DAIN_ADDR_LOW_0_0                        (_MK_ADDR_CONST(0x5034))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_SECURE                                    (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DUAL                                      (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_SCR                                         (0)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_WORD_COUNT                                (0x1)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT    (_MK_SHIFT_CONST(5))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_RANGE                  (31:5)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_WOFFSET                 (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_ADDR_HIGH_1_0
+#define CDMA_D_DAIN_ADDR_HIGH_1_0                       (_MK_ADDR_CONST(0x5038))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_SECURE                                   (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DUAL                                     (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_SCR                                        (0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_WORD_COUNT                               (0x1)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_RESET_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_READ_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_RANGE                (31:0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_WOFFSET               (0x0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_ADDR_LOW_1_0
+#define CDMA_D_DAIN_ADDR_LOW_1_0                        (_MK_ADDR_CONST(0x503c))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_SECURE                                    (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DUAL                                      (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_SCR                                         (0)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_WORD_COUNT                                (0x1)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT    (_MK_SHIFT_CONST(5))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_RANGE                  (31:5)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_WOFFSET                 (0x0)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_LINE_STRIDE_0
+#define CDMA_D_LINE_STRIDE_0                            (_MK_ADDR_CONST(0x5040))
+#define CDMA_D_LINE_STRIDE_0_SECURE                                        (0x0)
+#define CDMA_D_LINE_STRIDE_0_DUAL                                          (0x0)
+#define CDMA_D_LINE_STRIDE_0_SCR                                             (0)
+#define CDMA_D_LINE_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_LINE_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_RESET_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_READ_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_STRIDE_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_RANGE                            (31:5)
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_WOFFSET                           (0x0)
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_LINE_UV_STRIDE_0
+#define CDMA_D_LINE_UV_STRIDE_0                         (_MK_ADDR_CONST(0x5044))
+#define CDMA_D_LINE_UV_STRIDE_0_SECURE                                     (0x0)
+#define CDMA_D_LINE_UV_STRIDE_0_DUAL                                       (0x0)
+#define CDMA_D_LINE_UV_STRIDE_0_SCR                                          (0)
+#define CDMA_D_LINE_UV_STRIDE_0_WORD_COUNT                                 (0x1)
+#define CDMA_D_LINE_UV_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_UV_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_UV_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT        (_MK_SHIFT_CONST(5))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_RANGE                      (31:5)
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_WOFFSET                     (0x0)
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_SURF_STRIDE_0
+#define CDMA_D_SURF_STRIDE_0                            (_MK_ADDR_CONST(0x5048))
+#define CDMA_D_SURF_STRIDE_0_SECURE                                        (0x0)
+#define CDMA_D_SURF_STRIDE_0_DUAL                                          (0x0)
+#define CDMA_D_SURF_STRIDE_0_SCR                                             (0)
+#define CDMA_D_SURF_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_SURF_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_RESET_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_SURF_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_READ_MASK              (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_SURF_STRIDE_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_RANGE                            (31:5)
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_WOFFSET                           (0x0)
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_DAIN_MAP_0
+#define CDMA_D_DAIN_MAP_0                               (_MK_ADDR_CONST(0x504c))
+#define CDMA_D_DAIN_MAP_0_SECURE                                           (0x0)
+#define CDMA_D_DAIN_MAP_0_DUAL                                             (0x0)
+#define CDMA_D_DAIN_MAP_0_SCR                                                (0)
+#define CDMA_D_DAIN_MAP_0_WORD_COUNT                                       (0x1)
+#define CDMA_D_DAIN_MAP_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_RESET_MASK                   (_MK_MASK_CONST(0x10001))
+#define CDMA_D_DAIN_MAP_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_READ_MASK                    (_MK_MASK_CONST(0x10001))
+#define CDMA_D_DAIN_MAP_0_WRITE_MASK                   (_MK_MASK_CONST(0x10001))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_RANGE                                (0:0)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_WOFFSET                              (0x0)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_INIT_ENUM                          (FALSE)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FALSE                  (_MK_ENUM_CONST(0))
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_TRUE                   (_MK_ENUM_CONST(1))
+
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT                (_MK_SHIFT_CONST(16))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_RANGE                              (16:16)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_WOFFSET                              (0x0)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_INIT_ENUM                          (FALSE)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FALSE                  (_MK_ENUM_CONST(0))
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_TRUE                   (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_RESERVED_X_CFG_0
+#define CDMA_D_RESERVED_X_CFG_0                         (_MK_ADDR_CONST(0x5050))
+#define CDMA_D_RESERVED_X_CFG_0_SECURE                                     (0x0)
+#define CDMA_D_RESERVED_X_CFG_0_DUAL                                       (0x0)
+#define CDMA_D_RESERVED_X_CFG_0_SCR                                          (0)
+#define CDMA_D_RESERVED_X_CFG_0_WORD_COUNT                                 (0x1)
+#define CDMA_D_RESERVED_X_CFG_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RESET_MASK           (_MK_MASK_CONST(0x3ff03ff))
+#define CDMA_D_RESERVED_X_CFG_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_READ_MASK            (_MK_MASK_CONST(0x3ff03ff))
+#define CDMA_D_RESERVED_X_CFG_0_WRITE_MASK           (_MK_MASK_CONST(0x3ff03ff))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_FIELD \
+	(_MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_RANGE                         (9:0)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_WOFFSET                       (0x0)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT      (_MK_SHIFT_CONST(16))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_RANGE                    (25:16)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_WOFFSET                    (0x0)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_RESERVED_Y_CFG_0
+#define CDMA_D_RESERVED_Y_CFG_0                         (_MK_ADDR_CONST(0x5054))
+#define CDMA_D_RESERVED_Y_CFG_0_SECURE                                     (0x0)
+#define CDMA_D_RESERVED_Y_CFG_0_DUAL                                       (0x0)
+#define CDMA_D_RESERVED_Y_CFG_0_SCR                                          (0)
+#define CDMA_D_RESERVED_Y_CFG_0_WORD_COUNT                                 (0x1)
+#define CDMA_D_RESERVED_Y_CFG_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RESET_MASK            (_MK_MASK_CONST(0x1f0007))
+#define CDMA_D_RESERVED_Y_CFG_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_READ_MASK             (_MK_MASK_CONST(0x1f0007))
+#define CDMA_D_RESERVED_Y_CFG_0_WRITE_MASK            (_MK_MASK_CONST(0x1f0007))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT            (_MK_SHIFT_CONST(0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x7, CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_RANGE                           (2:0)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_WOFFSET                         (0x0)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_DEFAULT_MASK    (_MK_MASK_CONST(0x7))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT          (_MK_SHIFT_CONST(16))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_RANGE                        (20:16)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_WOFFSET                        (0x0)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_BATCH_NUMBER_0
+#define CDMA_D_BATCH_NUMBER_0                           (_MK_ADDR_CONST(0x5058))
+#define CDMA_D_BATCH_NUMBER_0_SECURE                                       (0x0)
+#define CDMA_D_BATCH_NUMBER_0_DUAL                                         (0x0)
+#define CDMA_D_BATCH_NUMBER_0_SCR                                            (0)
+#define CDMA_D_BATCH_NUMBER_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_BATCH_NUMBER_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_RESET_MASK                  (_MK_MASK_CONST(0x1f))
+#define CDMA_D_BATCH_NUMBER_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_READ_MASK                   (_MK_MASK_CONST(0x1f))
+#define CDMA_D_BATCH_NUMBER_0_WRITE_MASK                  (_MK_MASK_CONST(0x1f))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_RANGE                                (4:0)
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_WOFFSET                              (0x0)
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_BATCH_STRIDE_0
+#define CDMA_D_BATCH_STRIDE_0                           (_MK_ADDR_CONST(0x505c))
+#define CDMA_D_BATCH_STRIDE_0_SECURE                                       (0x0)
+#define CDMA_D_BATCH_STRIDE_0_DUAL                                         (0x0)
+#define CDMA_D_BATCH_STRIDE_0_SCR                                            (0)
+#define CDMA_D_BATCH_STRIDE_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_BATCH_STRIDE_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_BATCH_STRIDE_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_BATCH_STRIDE_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT            (_MK_SHIFT_CONST(5))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_RANGE                          (31:5)
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_WOFFSET                         (0x0)
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_ENTRY_PER_SLICE_0
+#define CDMA_D_ENTRY_PER_SLICE_0                        (_MK_ADDR_CONST(0x5060))
+#define CDMA_D_ENTRY_PER_SLICE_0_SECURE                                    (0x0)
+#define CDMA_D_ENTRY_PER_SLICE_0_DUAL                                      (0x0)
+#define CDMA_D_ENTRY_PER_SLICE_0_SCR                                         (0)
+#define CDMA_D_ENTRY_PER_SLICE_0_WORD_COUNT                                (0x1)
+#define CDMA_D_ENTRY_PER_SLICE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_RESET_MASK              (_MK_MASK_CONST(0xfff))
+#define CDMA_D_ENTRY_PER_SLICE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_READ_MASK               (_MK_MASK_CONST(0xfff))
+#define CDMA_D_ENTRY_PER_SLICE_0_WRITE_MASK              (_MK_MASK_CONST(0xfff))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT              (_MK_SHIFT_CONST(0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD \
+	(_MK_FIELD_CONST(0xfff, CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_RANGE                            (11:0)
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_WOFFSET                           (0x0)
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT_MASK    (_MK_MASK_CONST(0xfff))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_FETCH_GRAIN_0
+#define CDMA_D_FETCH_GRAIN_0                            (_MK_ADDR_CONST(0x5064))
+#define CDMA_D_FETCH_GRAIN_0_SECURE                                        (0x0)
+#define CDMA_D_FETCH_GRAIN_0_DUAL                                          (0x0)
+#define CDMA_D_FETCH_GRAIN_0_SCR                                             (0)
+#define CDMA_D_FETCH_GRAIN_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_FETCH_GRAIN_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_RESET_MASK                  (_MK_MASK_CONST(0xfff))
+#define CDMA_D_FETCH_GRAIN_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_READ_MASK                   (_MK_MASK_CONST(0xfff))
+#define CDMA_D_FETCH_GRAIN_0_WRITE_MASK                  (_MK_MASK_CONST(0xfff))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_FIELD \
+	(_MK_FIELD_CONST(0xfff, CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_RANGE                                 (11:0)
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_WOFFSET                                (0x0)
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_DEFAULT_MASK         (_MK_MASK_CONST(0xfff))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_FORMAT_0
+#define CDMA_D_WEIGHT_FORMAT_0                          (_MK_ADDR_CONST(0x5068))
+#define CDMA_D_WEIGHT_FORMAT_0_SECURE                                      (0x0)
+#define CDMA_D_WEIGHT_FORMAT_0_DUAL                                        (0x0)
+#define CDMA_D_WEIGHT_FORMAT_0_SCR                                           (0)
+#define CDMA_D_WEIGHT_FORMAT_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WEIGHT_FORMAT_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_RANGE                         (0:0)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_WOFFSET                       (0x0)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_INIT_ENUM            (UNCOMPRESSED)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED    (_MK_ENUM_CONST(0))
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED      (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_WEIGHT_SIZE_0_0
+#define CDMA_D_WEIGHT_SIZE_0_0                          (_MK_ADDR_CONST(0x506c))
+#define CDMA_D_WEIGHT_SIZE_0_0_SECURE                                      (0x0)
+#define CDMA_D_WEIGHT_SIZE_0_0_DUAL                                        (0x0)
+#define CDMA_D_WEIGHT_SIZE_0_0_SCR                                           (0)
+#define CDMA_D_WEIGHT_SIZE_0_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WEIGHT_SIZE_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_RESET_MASK              (_MK_MASK_CONST(0x3ffff))
+#define CDMA_D_WEIGHT_SIZE_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_READ_MASK               (_MK_MASK_CONST(0x3ffff))
+#define CDMA_D_WEIGHT_SIZE_0_0_WRITE_MASK              (_MK_MASK_CONST(0x3ffff))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT        (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_FIELD \
+	(_MK_FIELD_CONST(0x3ffff, \
+	CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_RANGE                      (17:0)
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_WOFFSET                     (0x0)
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ffff))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_SIZE_1_0
+#define CDMA_D_WEIGHT_SIZE_1_0                          (_MK_ADDR_CONST(0x5070))
+#define CDMA_D_WEIGHT_SIZE_1_0_SECURE                                      (0x0)
+#define CDMA_D_WEIGHT_SIZE_1_0_DUAL                                        (0x0)
+#define CDMA_D_WEIGHT_SIZE_1_0_SCR                                           (0)
+#define CDMA_D_WEIGHT_SIZE_1_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WEIGHT_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_WEIGHT_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_WEIGHT_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_RANGE                        (12:0)
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_WOFFSET                       (0x0)
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_RAM_TYPE_0
+#define CDMA_D_WEIGHT_RAM_TYPE_0                        (_MK_ADDR_CONST(0x5074))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_SECURE                                    (0x0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_DUAL                                      (0x0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_SCR                                         (0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WORD_COUNT                                (0x1)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT      (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_RANGE                     (0:0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_WOFFSET                   (0x0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_INIT_ENUM                (CVIF)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_CVIF        (_MK_ENUM_CONST(0))
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_MCIF        (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_WEIGHT_ADDR_HIGH_0
+#define CDMA_D_WEIGHT_ADDR_HIGH_0                       (_MK_ADDR_CONST(0x5078))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_SECURE                                   (0x0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_DUAL                                     (0x0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_SCR                                        (0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WORD_COUNT                               (0x1)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_RESET_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_READ_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT    (_MK_SHIFT_CONST(0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_RANGE                  (31:0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_WOFFSET                 (0x0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_ADDR_LOW_0
+#define CDMA_D_WEIGHT_ADDR_LOW_0                        (_MK_ADDR_CONST(0x507c))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_SECURE                                    (0x0)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_DUAL                                      (0x0)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_SCR                                         (0)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WORD_COUNT                                (0x1)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT      (_MK_SHIFT_CONST(5))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_RANGE                    (31:5)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_WOFFSET                   (0x0)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WEIGHT_BYTES_0
+#define CDMA_D_WEIGHT_BYTES_0                           (_MK_ADDR_CONST(0x5080))
+#define CDMA_D_WEIGHT_BYTES_0_SECURE                                       (0x0)
+#define CDMA_D_WEIGHT_BYTES_0_DUAL                                         (0x0)
+#define CDMA_D_WEIGHT_BYTES_0_SCR                                            (0)
+#define CDMA_D_WEIGHT_BYTES_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_WEIGHT_BYTES_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_RESET_MASK            (_MK_MASK_CONST(0xffffff80))
+#define CDMA_D_WEIGHT_BYTES_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_READ_MASK             (_MK_MASK_CONST(0xffffff80))
+#define CDMA_D_WEIGHT_BYTES_0_WRITE_MASK            (_MK_MASK_CONST(0xffffff80))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT            (_MK_SHIFT_CONST(7))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD \
+	(_MK_FIELD_CONST(0x1ffffff, \
+	CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_RANGE                          (31:7)
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_WOFFSET                         (0x0)
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1ffffff))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WGS_ADDR_HIGH_0
+#define CDMA_D_WGS_ADDR_HIGH_0                          (_MK_ADDR_CONST(0x5084))
+#define CDMA_D_WGS_ADDR_HIGH_0_SECURE                                      (0x0)
+#define CDMA_D_WGS_ADDR_HIGH_0_DUAL                                        (0x0)
+#define CDMA_D_WGS_ADDR_HIGH_0_SCR                                           (0)
+#define CDMA_D_WGS_ADDR_HIGH_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WGS_ADDR_HIGH_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WGS_ADDR_HIGH_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WGS_ADDR_HIGH_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_RANGE                        (31:0)
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_WOFFSET                       (0x0)
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WGS_ADDR_LOW_0
+#define CDMA_D_WGS_ADDR_LOW_0                           (_MK_ADDR_CONST(0x5088))
+#define CDMA_D_WGS_ADDR_LOW_0_SECURE                                       (0x0)
+#define CDMA_D_WGS_ADDR_LOW_0_DUAL                                         (0x0)
+#define CDMA_D_WGS_ADDR_LOW_0_SCR                                            (0)
+#define CDMA_D_WGS_ADDR_LOW_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_WGS_ADDR_LOW_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WGS_ADDR_LOW_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WGS_ADDR_LOW_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT            (_MK_SHIFT_CONST(5))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_RANGE                          (31:5)
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_WOFFSET                         (0x0)
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WMB_ADDR_HIGH_0
+#define CDMA_D_WMB_ADDR_HIGH_0                          (_MK_ADDR_CONST(0x508c))
+#define CDMA_D_WMB_ADDR_HIGH_0_SECURE                                      (0x0)
+#define CDMA_D_WMB_ADDR_HIGH_0_DUAL                                        (0x0)
+#define CDMA_D_WMB_ADDR_HIGH_0_SCR                                           (0)
+#define CDMA_D_WMB_ADDR_HIGH_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_WMB_ADDR_HIGH_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WMB_ADDR_HIGH_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WMB_ADDR_HIGH_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_RANGE                        (31:0)
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_WOFFSET                       (0x0)
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WMB_ADDR_LOW_0
+#define CDMA_D_WMB_ADDR_LOW_0                           (_MK_ADDR_CONST(0x5090))
+#define CDMA_D_WMB_ADDR_LOW_0_SECURE                                       (0x0)
+#define CDMA_D_WMB_ADDR_LOW_0_DUAL                                         (0x0)
+#define CDMA_D_WMB_ADDR_LOW_0_SCR                                            (0)
+#define CDMA_D_WMB_ADDR_LOW_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_WMB_ADDR_LOW_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WMB_ADDR_LOW_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WMB_ADDR_LOW_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT            (_MK_SHIFT_CONST(5))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_RANGE                          (31:5)
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_WOFFSET                         (0x0)
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_WMB_BYTES_0
+#define CDMA_D_WMB_BYTES_0                              (_MK_ADDR_CONST(0x5094))
+#define CDMA_D_WMB_BYTES_0_SECURE                                          (0x0)
+#define CDMA_D_WMB_BYTES_0_DUAL                                            (0x0)
+#define CDMA_D_WMB_BYTES_0_SCR                                               (0)
+#define CDMA_D_WMB_BYTES_0_WORD_COUNT                                      (0x1)
+#define CDMA_D_WMB_BYTES_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_RESET_MASK                (_MK_MASK_CONST(0xfffff80))
+#define CDMA_D_WMB_BYTES_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_READ_MASK                 (_MK_MASK_CONST(0xfffff80))
+#define CDMA_D_WMB_BYTES_0_WRITE_MASK                (_MK_MASK_CONST(0xfffff80))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT                  (_MK_SHIFT_CONST(7))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_FIELD \
+	(_MK_FIELD_CONST(0x1fffff, CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_RANGE                                (27:7)
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_WOFFSET                               (0x0)
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_DEFAULT_MASK     (_MK_MASK_CONST(0x1fffff))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_MEAN_FORMAT_0
+#define CDMA_D_MEAN_FORMAT_0                            (_MK_ADDR_CONST(0x5098))
+#define CDMA_D_MEAN_FORMAT_0_SECURE                                        (0x0)
+#define CDMA_D_MEAN_FORMAT_0_DUAL                                          (0x0)
+#define CDMA_D_MEAN_FORMAT_0_SCR                                             (0)
+#define CDMA_D_MEAN_FORMAT_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_MEAN_FORMAT_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_READ_MASK                     (_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT              (_MK_SHIFT_CONST(0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_RANGE                             (0:0)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_WOFFSET                           (0x0)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_INIT_ENUM                     (DISABLE)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DISABLE             (_MK_ENUM_CONST(0))
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_ENABLE              (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_MEAN_GLOBAL_0_0
+#define CDMA_D_MEAN_GLOBAL_0_0                          (_MK_ADDR_CONST(0x509c))
+#define CDMA_D_MEAN_GLOBAL_0_0_SECURE                                      (0x0)
+#define CDMA_D_MEAN_GLOBAL_0_0_DUAL                                        (0x0)
+#define CDMA_D_MEAN_GLOBAL_0_0_SCR                                           (0)
+#define CDMA_D_MEAN_GLOBAL_0_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_MEAN_GLOBAL_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT                (_MK_SHIFT_CONST(0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_RANGE                              (15:0)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_WOFFSET                             (0x0)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT               (_MK_SHIFT_CONST(16))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_RANGE                             (31:16)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_WOFFSET                             (0x0)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_MEAN_GLOBAL_1_0
+#define CDMA_D_MEAN_GLOBAL_1_0                          (_MK_ADDR_CONST(0x50a0))
+#define CDMA_D_MEAN_GLOBAL_1_0_SECURE                                      (0x0)
+#define CDMA_D_MEAN_GLOBAL_1_0_DUAL                                        (0x0)
+#define CDMA_D_MEAN_GLOBAL_1_0_SCR                                           (0)
+#define CDMA_D_MEAN_GLOBAL_1_0_WORD_COUNT                                  (0x1)
+#define CDMA_D_MEAN_GLOBAL_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT                (_MK_SHIFT_CONST(0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_RANGE                              (15:0)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_WOFFSET                             (0x0)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT               (_MK_SHIFT_CONST(16))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_RANGE                             (31:16)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_WOFFSET                             (0x0)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CVT_CFG_0
+#define CDMA_D_CVT_CFG_0                                (_MK_ADDR_CONST(0x50a4))
+#define CDMA_D_CVT_CFG_0_SECURE                                            (0x0)
+#define CDMA_D_CVT_CFG_0_DUAL                                              (0x0)
+#define CDMA_D_CVT_CFG_0_SCR                                                 (0)
+#define CDMA_D_CVT_CFG_0_WORD_COUNT                                        (0x1)
+#define CDMA_D_CVT_CFG_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x3f1))
+#define CDMA_D_CVT_CFG_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x3f1))
+#define CDMA_D_CVT_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x3f1))
+#define CDMA_D_CVT_CFG_0_CVT_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_CVT_CFG_0_CVT_EN_SHIFT))
+#define CDMA_D_CVT_CFG_0_CVT_EN_RANGE                                      (0:0)
+#define CDMA_D_CVT_CFG_0_CVT_EN_WOFFSET                                    (0x0)
+#define CDMA_D_CVT_CFG_0_CVT_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define CDMA_D_CVT_CFG_0_CVT_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CDMA_D_CVT_CFG_0_CVT_EN_INIT_ENUM                              (DISABLE)
+#define CDMA_D_CVT_CFG_0_CVT_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define CDMA_D_CVT_CFG_0_CVT_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT                 (_MK_SHIFT_CONST(4))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3f, CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_RANGE                                (9:4)
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_WOFFSET                              (0x0)
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_DEFAULT_MASK        (_MK_MASK_CONST(0x3f))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CVT_OFFSET_0
+#define CDMA_D_CVT_OFFSET_0                             (_MK_ADDR_CONST(0x50a8))
+#define CDMA_D_CVT_OFFSET_0_SECURE                                         (0x0)
+#define CDMA_D_CVT_OFFSET_0_DUAL                                           (0x0)
+#define CDMA_D_CVT_OFFSET_0_SCR                                              (0)
+#define CDMA_D_CVT_OFFSET_0_WORD_COUNT                                     (0x1)
+#define CDMA_D_CVT_OFFSET_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_RESET_MASK                  (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_OFFSET_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_READ_MASK                   (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_OFFSET_0_WRITE_MASK                  (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT                (_MK_SHIFT_CONST(0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_RANGE                              (15:0)
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_WOFFSET                             (0x0)
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT_MASK     (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CVT_SCALE_0
+#define CDMA_D_CVT_SCALE_0                              (_MK_ADDR_CONST(0x50ac))
+#define CDMA_D_CVT_SCALE_0_SECURE                                          (0x0)
+#define CDMA_D_CVT_SCALE_0_DUAL                                            (0x0)
+#define CDMA_D_CVT_SCALE_0_SCR                                               (0)
+#define CDMA_D_CVT_SCALE_0_WORD_COUNT                                      (0x1)
+#define CDMA_D_CVT_SCALE_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_RESET_MASK                   (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_SCALE_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_READ_MASK                    (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_SCALE_0_WRITE_MASK                   (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_RANGE                                (15:0)
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_WOFFSET                               (0x0)
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_DEFAULT_MASK       (_MK_MASK_CONST(0xffff))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CONV_STRIDE_0
+#define CDMA_D_CONV_STRIDE_0                            (_MK_ADDR_CONST(0x50b0))
+#define CDMA_D_CONV_STRIDE_0_SECURE                                        (0x0)
+#define CDMA_D_CONV_STRIDE_0_DUAL                                          (0x0)
+#define CDMA_D_CONV_STRIDE_0_SCR                                             (0)
+#define CDMA_D_CONV_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_CONV_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_RESET_MASK                (_MK_MASK_CONST(0x70007))
+#define CDMA_D_CONV_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_READ_MASK                 (_MK_MASK_CONST(0x70007))
+#define CDMA_D_CONV_STRIDE_0_WRITE_MASK                (_MK_MASK_CONST(0x70007))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT            (_MK_SHIFT_CONST(0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_RANGE                           (2:0)
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_WOFFSET                         (0x0)
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_DEFAULT_MASK    (_MK_MASK_CONST(0x7))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT           (_MK_SHIFT_CONST(16))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_RANGE                         (18:16)
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_WOFFSET                         (0x0)
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_DEFAULT_MASK    (_MK_MASK_CONST(0x7))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_ZERO_PADDING_0
+#define CDMA_D_ZERO_PADDING_0                           (_MK_ADDR_CONST(0x50b4))
+#define CDMA_D_ZERO_PADDING_0_SECURE                                       (0x0)
+#define CDMA_D_ZERO_PADDING_0_DUAL                                         (0x0)
+#define CDMA_D_ZERO_PADDING_0_SCR                                            (0)
+#define CDMA_D_ZERO_PADDING_0_WORD_COUNT                                   (0x1)
+#define CDMA_D_ZERO_PADDING_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_RESET_MASK            (_MK_MASK_CONST(0x3f1f3f1f))
+#define CDMA_D_ZERO_PADDING_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_READ_MASK             (_MK_MASK_CONST(0x3f1f3f1f))
+#define CDMA_D_ZERO_PADDING_0_WRITE_MASK            (_MK_MASK_CONST(0x3f1f3f1f))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT                (_MK_SHIFT_CONST(0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_RANGE                               (4:0)
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_WOFFSET                             (0x0)
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT_MASK       (_MK_MASK_CONST(0x1f))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT               (_MK_SHIFT_CONST(8))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_FIELD \
+	(_MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_RANGE                             (13:8)
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_WOFFSET                            (0x0)
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_DEFAULT_MASK      (_MK_MASK_CONST(0x3f))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT                (_MK_SHIFT_CONST(16))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_RANGE                              (20:16)
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_WOFFSET                              (0x0)
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT             (_MK_SHIFT_CONST(24))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_FIELD \
+	(_MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_RANGE                           (29:24)
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_WOFFSET                           (0x0)
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_DEFAULT_MASK     (_MK_MASK_CONST(0x3f))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_ZERO_PADDING_VALUE_0
+#define CDMA_D_ZERO_PADDING_VALUE_0                     (_MK_ADDR_CONST(0x50b8))
+#define CDMA_D_ZERO_PADDING_VALUE_0_SECURE                                 (0x0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_DUAL                                   (0x0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_SCR                                      (0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_WORD_COUNT                             (0x1)
+#define CDMA_D_ZERO_PADDING_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define CDMA_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define CDMA_D_ZERO_PADDING_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_RANGE                       (15:0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_WOFFSET                      (0x0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_BANK_0
+#define CDMA_D_BANK_0                                   (_MK_ADDR_CONST(0x50bc))
+#define CDMA_D_BANK_0_SECURE                                               (0x0)
+#define CDMA_D_BANK_0_DUAL                                                 (0x0)
+#define CDMA_D_BANK_0_SCR                                                    (0)
+#define CDMA_D_BANK_0_WORD_COUNT                                           (0x1)
+#define CDMA_D_BANK_0_RESET_VAL                            (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_RESET_MASK                       (_MK_MASK_CONST(0xf000f))
+#define CDMA_D_BANK_0_SW_DEFAULT_VAL                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_SW_DEFAULT_MASK                      (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_READ_MASK                        (_MK_MASK_CONST(0xf000f))
+#define CDMA_D_BANK_0_WRITE_MASK                       (_MK_MASK_CONST(0xf000f))
+#define CDMA_D_BANK_0_DATA_BANK_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CDMA_D_BANK_0_DATA_BANK_FIELD \
+	(_MK_FIELD_CONST(0xf, CDMA_D_BANK_0_DATA_BANK_SHIFT))
+#define CDMA_D_BANK_0_DATA_BANK_RANGE                                      (3:0)
+#define CDMA_D_BANK_0_DATA_BANK_WOFFSET                                    (0x0)
+#define CDMA_D_BANK_0_DATA_BANK_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_DATA_BANK_DEFAULT_MASK               (_MK_MASK_CONST(0xf))
+#define CDMA_D_BANK_0_DATA_BANK_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_DATA_BANK_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_DATA_BANK_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_DATA_BANK_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+
+#define CDMA_D_BANK_0_WEIGHT_BANK_SHIFT                    (_MK_SHIFT_CONST(16))
+#define CDMA_D_BANK_0_WEIGHT_BANK_FIELD \
+	(_MK_FIELD_CONST(0xf, CDMA_D_BANK_0_WEIGHT_BANK_SHIFT))
+#define CDMA_D_BANK_0_WEIGHT_BANK_RANGE                                  (19:16)
+#define CDMA_D_BANK_0_WEIGHT_BANK_WOFFSET                                  (0x0)
+#define CDMA_D_BANK_0_WEIGHT_BANK_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_WEIGHT_BANK_DEFAULT_MASK             (_MK_MASK_CONST(0xf))
+#define CDMA_D_BANK_0_WEIGHT_BANK_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_WEIGHT_BANK_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_WEIGHT_BANK_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CDMA_D_BANK_0_WEIGHT_BANK_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_NAN_FLUSH_TO_ZERO_0
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0                      (_MK_ADDR_CONST(0x50c0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SECURE                                  (0x0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_DUAL                                    (0x0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SCR                                       (0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_WORD_COUNT                              (0x1)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_RESET_MASK              (_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_READ_MASK               (_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_WRITE_MASK              (_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT        (_MK_SHIFT_CONST(0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_RANGE                       (0:0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_WOFFSET                     (0x0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_INIT_ENUM               (DISABLE)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE       (_MK_ENUM_CONST(0))
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE        (_MK_ENUM_CONST(1))
+
+
+// Register CDMA_D_NAN_INPUT_DATA_NUM_0
+#define CDMA_D_NAN_INPUT_DATA_NUM_0                     (_MK_ADDR_CONST(0x50c4))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_SECURE                                 (0x0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_DUAL                                   (0x0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_SCR                                      (0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_WORD_COUNT                             (0x1)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT      (_MK_SHIFT_CONST(0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_RANGE                    (31:0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_WOFFSET                   (0x0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_NAN_INPUT_WEIGHT_NUM_0
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0                   (_MK_ADDR_CONST(0x50c8))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SECURE                               (0x0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_DUAL                                 (0x0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SCR                                    (0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_WORD_COUNT                           (0x1)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_RANGE                (31:0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_WOFFSET               (0x0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_INF_INPUT_DATA_NUM_0
+#define CDMA_D_INF_INPUT_DATA_NUM_0                     (_MK_ADDR_CONST(0x50cc))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_SECURE                                 (0x0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_DUAL                                   (0x0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_SCR                                      (0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_WORD_COUNT                             (0x1)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT      (_MK_SHIFT_CONST(0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_RANGE                    (31:0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_WOFFSET                   (0x0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_INF_INPUT_WEIGHT_NUM_0
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0                   (_MK_ADDR_CONST(0x50d0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SECURE                               (0x0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_DUAL                                 (0x0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SCR                                    (0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_WORD_COUNT                           (0x1)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_RANGE                (31:0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_WOFFSET               (0x0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_ENABLE_0
+#define CDMA_D_PERF_ENABLE_0                            (_MK_ADDR_CONST(0x50d4))
+#define CDMA_D_PERF_ENABLE_0_SECURE                                        (0x0)
+#define CDMA_D_PERF_ENABLE_0_DUAL                                          (0x0)
+#define CDMA_D_PERF_ENABLE_0_SCR                                             (0)
+#define CDMA_D_PERF_ENABLE_0_WORD_COUNT                                    (0x1)
+#define CDMA_D_PERF_ENABLE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
+#define CDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_READ_MASK                     (_MK_MASK_CONST(0x1))
+#define CDMA_D_PERF_ENABLE_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_RANGE                                  (0:0)
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_WOFFSET                                (0x0)
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_DAT_READ_STALL_0
+#define CDMA_D_PERF_DAT_READ_STALL_0                    (_MK_ADDR_CONST(0x50d8))
+#define CDMA_D_PERF_DAT_READ_STALL_0_SECURE                                (0x0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_DUAL                                  (0x0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_SCR                                     (0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_WORD_COUNT                            (0x1)
+#define CDMA_D_PERF_DAT_READ_STALL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_STALL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_STALL_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT     (_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_RANGE                   (31:0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_WOFFSET                  (0x0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_WT_READ_STALL_0
+#define CDMA_D_PERF_WT_READ_STALL_0                     (_MK_ADDR_CONST(0x50dc))
+#define CDMA_D_PERF_WT_READ_STALL_0_SECURE                                 (0x0)
+#define CDMA_D_PERF_WT_READ_STALL_0_DUAL                                   (0x0)
+#define CDMA_D_PERF_WT_READ_STALL_0_SCR                                      (0)
+#define CDMA_D_PERF_WT_READ_STALL_0_WORD_COUNT                             (0x1)
+#define CDMA_D_PERF_WT_READ_STALL_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_STALL_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_STALL_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT       (_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_RANGE                     (31:0)
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_WOFFSET                    (0x0)
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_DAT_READ_LATENCY_0
+#define CDMA_D_PERF_DAT_READ_LATENCY_0                  (_MK_ADDR_CONST(0x50e0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_SECURE                              (0x0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DUAL                                (0x0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_SCR                                   (0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_WORD_COUNT                          (0x1)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_WRITE_MASK          (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_RANGE               (31:0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_WOFFSET              (0x0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_PERF_WT_READ_LATENCY_0
+#define CDMA_D_PERF_WT_READ_LATENCY_0                   (_MK_ADDR_CONST(0x50e4))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_SECURE                               (0x0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_DUAL                                 (0x0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_SCR                                    (0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WORD_COUNT                           (0x1)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_RANGE                 (31:0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_WOFFSET                (0x0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDMA_D_CYA_0
+#define CDMA_D_CYA_0                                    (_MK_ADDR_CONST(0x50e8))
+#define CDMA_D_CYA_0_SECURE                                                (0x0)
+#define CDMA_D_CYA_0_DUAL                                                  (0x0)
+#define CDMA_D_CYA_0_SCR                                                     (0)
+#define CDMA_D_CYA_0_WORD_COUNT                                            (0x1)
+#define CDMA_D_CYA_0_RESET_VAL                             (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_RESET_MASK                     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_CYA_0_SW_DEFAULT_VAL                        (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_SW_DEFAULT_MASK                       (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_READ_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_CYA_0_WRITE_MASK                     (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_CYA_0_CYA_SHIFT                              (_MK_SHIFT_CONST(0))
+#define CDMA_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, CDMA_D_CYA_0_CYA_SHIFT))
+#define CDMA_D_CYA_0_CYA_RANGE                                            (31:0)
+#define CDMA_D_CYA_0_CYA_WOFFSET                                           (0x0)
+#define CDMA_D_CYA_0_CYA_DEFAULT                           (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_CYA_DEFAULT_MASK               (_MK_MASK_CONST(0xffffffff))
+#define CDMA_D_CYA_0_CYA_SW_DEFAULT                        (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_CYA_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_CYA_PARITY_PROTECTION                 (_MK_MASK_CONST(0x0))
+#define CDMA_D_CYA_0_CYA_PLATFORM_DEPENDENT                (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_S_STATUS_0
+#define CSC_S_STATUS_0                                  (_MK_ADDR_CONST(0x6000))
+#define CSC_S_STATUS_0_SECURE                                              (0x0)
+#define CSC_S_STATUS_0_DUAL                                                (0x0)
+#define CSC_S_STATUS_0_SCR                                                   (0)
+#define CSC_S_STATUS_0_WORD_COUNT                                          (0x1)
+#define CSC_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
+#define CSC_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
+#define CSC_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CSC_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_0_SHIFT))
+#define CSC_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
+#define CSC_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
+#define CSC_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define CSC_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CSC_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
+#define CSC_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
+#define CSC_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
+#define CSC_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
+
+#define CSC_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
+#define CSC_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_1_SHIFT))
+#define CSC_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
+#define CSC_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
+#define CSC_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define CSC_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CSC_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CSC_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
+#define CSC_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
+#define CSC_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
+#define CSC_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
+
+
+// Register CSC_S_POINTER_0
+#define CSC_S_POINTER_0                                 (_MK_ADDR_CONST(0x6004))
+#define CSC_S_POINTER_0_SECURE                                             (0x0)
+#define CSC_S_POINTER_0_DUAL                                               (0x0)
+#define CSC_S_POINTER_0_SCR                                                  (0)
+#define CSC_S_POINTER_0_WORD_COUNT                                         (0x1)
+#define CSC_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
+#define CSC_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
+#define CSC_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CSC_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_S_POINTER_0_PRODUCER_SHIFT))
+#define CSC_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
+#define CSC_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
+#define CSC_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
+#define CSC_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define CSC_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+#define CSC_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CSC_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_S_POINTER_0_CONSUMER_SHIFT))
+#define CSC_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
+#define CSC_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
+#define CSC_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CSC_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CSC_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
+#define CSC_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define CSC_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_OP_ENABLE_0
+#define CSC_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0x6008))
+#define CSC_D_OP_ENABLE_0_SECURE                                           (0x0)
+#define CSC_D_OP_ENABLE_0_DUAL                                             (0x0)
+#define CSC_D_OP_ENABLE_0_SCR                                                (0)
+#define CSC_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
+#define CSC_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CSC_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CSC_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
+#define CSC_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
+#define CSC_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CSC_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CSC_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
+#define CSC_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define CSC_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_MISC_CFG_0
+#define CSC_D_MISC_CFG_0                                (_MK_ADDR_CONST(0x600c))
+#define CSC_D_MISC_CFG_0_SECURE                                            (0x0)
+#define CSC_D_MISC_CFG_0_DUAL                                              (0x0)
+#define CSC_D_MISC_CFG_0_SCR                                                 (0)
+#define CSC_D_MISC_CFG_0_WORD_COUNT                                        (0x1)
+#define CSC_D_MISC_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x1100))
+#define CSC_D_MISC_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x11113301))
+#define CSC_D_MISC_CFG_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x11113301))
+#define CSC_D_MISC_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x11113301))
+#define CSC_D_MISC_CFG_0_CONV_MODE_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CSC_D_MISC_CFG_0_CONV_MODE_RANGE                                   (0:0)
+#define CSC_D_MISC_CFG_0_CONV_MODE_WOFFSET                                 (0x0)
+#define CSC_D_MISC_CFG_0_CONV_MODE_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                            (DIRECT)
+#define CSC_D_MISC_CFG_0_CONV_MODE_DIRECT                    (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_CONV_MODE_WINOGRAD                  (_MK_ENUM_CONST(1))
+
+#define CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT                 (_MK_SHIFT_CONST(8))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_RANGE                                (9:8)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_WOFFSET                              (0x0)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_DEFAULT              (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_INIT_ENUM                          (INT16)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_INT8                   (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_INT16                  (_MK_ENUM_CONST(1))
+#define CSC_D_MISC_CFG_0_IN_PRECISION_FP16                   (_MK_ENUM_CONST(2))
+
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT              (_MK_SHIFT_CONST(12))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_RANGE                            (13:12)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                            (0x0)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT            (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK       (_MK_MASK_CONST(0x3))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                        (INT16)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT8                 (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT16                (_MK_ENUM_CONST(1))
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_FP16                 (_MK_ENUM_CONST(2))
+
+#define CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT                  (_MK_SHIFT_CONST(16))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_RANGE                                (16:16)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_WOFFSET                                (0x0)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_INIT_ENUM                          (DISABLE)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_DISABLE                  (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_DATA_REUSE_ENABLE                   (_MK_ENUM_CONST(1))
+
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT                (_MK_SHIFT_CONST(20))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_RANGE                              (20:20)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_WOFFSET                              (0x0)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_INIT_ENUM                        (DISABLE)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE                (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE                 (_MK_ENUM_CONST(1))
+
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT               (_MK_SHIFT_CONST(24))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_RANGE                             (24:24)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_WOFFSET                             (0x0)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_INIT_ENUM                       (DISABLE)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE               (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE                (_MK_ENUM_CONST(1))
+
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT             (_MK_SHIFT_CONST(28))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_RANGE                           (28:28)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_WOFFSET                           (0x0)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_INIT_ENUM                     (DISABLE)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE             (_MK_ENUM_CONST(0))
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE              (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_DATAIN_FORMAT_0
+#define CSC_D_DATAIN_FORMAT_0                           (_MK_ADDR_CONST(0x6010))
+#define CSC_D_DATAIN_FORMAT_0_SECURE                                       (0x0)
+#define CSC_D_DATAIN_FORMAT_0_DUAL                                         (0x0)
+#define CSC_D_DATAIN_FORMAT_0_SCR                                            (0)
+#define CSC_D_DATAIN_FORMAT_0_WORD_COUNT                                   (0x1)
+#define CSC_D_DATAIN_FORMAT_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_RESET_MASK                   (_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_READ_MASK                    (_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_WRITE_MASK                   (_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT           (_MK_SHIFT_CONST(0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_RANGE                          (0:0)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_WOFFSET                        (0x0)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_INIT_ENUM                  (FEATURE)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE          (_MK_ENUM_CONST(0))
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL            (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_DATAIN_SIZE_EXT_0_0
+#define CSC_D_DATAIN_SIZE_EXT_0_0                       (_MK_ADDR_CONST(0x6014))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_SECURE                                   (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DUAL                                     (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_SCR                                        (0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_WORD_COUNT                               (0x1)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_RESET_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_READ_MASK         (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT    (_MK_SHIFT_CONST(0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_RANGE                  (12:0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_WOFFSET                 (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_RANGE                (28:16)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_WOFFSET                (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_DATAIN_SIZE_EXT_1_0
+#define CSC_D_DATAIN_SIZE_EXT_1_0                       (_MK_ADDR_CONST(0x6018))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_SECURE                                   (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DUAL                                     (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_SCR                                        (0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_WORD_COUNT                               (0x1)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_RESET_MASK            (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_READ_MASK             (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_WRITE_MASK            (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_RANGE                (12:0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_WOFFSET               (0x0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_BATCH_NUMBER_0
+#define CSC_D_BATCH_NUMBER_0                            (_MK_ADDR_CONST(0x601c))
+#define CSC_D_BATCH_NUMBER_0_SECURE                                        (0x0)
+#define CSC_D_BATCH_NUMBER_0_DUAL                                          (0x0)
+#define CSC_D_BATCH_NUMBER_0_SCR                                             (0)
+#define CSC_D_BATCH_NUMBER_0_WORD_COUNT                                    (0x1)
+#define CSC_D_BATCH_NUMBER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_RESET_MASK                   (_MK_MASK_CONST(0x1f))
+#define CSC_D_BATCH_NUMBER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_READ_MASK                    (_MK_MASK_CONST(0x1f))
+#define CSC_D_BATCH_NUMBER_0_WRITE_MASK                   (_MK_MASK_CONST(0x1f))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_RANGE                                 (4:0)
+#define CSC_D_BATCH_NUMBER_0_BATCHES_WOFFSET                               (0x0)
+#define CSC_D_BATCH_NUMBER_0_BATCHES_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_DEFAULT_MASK         (_MK_MASK_CONST(0x1f))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CSC_D_BATCH_NUMBER_0_BATCHES_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_POST_Y_EXTENSION_0
+#define CSC_D_POST_Y_EXTENSION_0                        (_MK_ADDR_CONST(0x6020))
+#define CSC_D_POST_Y_EXTENSION_0_SECURE                                    (0x0)
+#define CSC_D_POST_Y_EXTENSION_0_DUAL                                      (0x0)
+#define CSC_D_POST_Y_EXTENSION_0_SCR                                         (0)
+#define CSC_D_POST_Y_EXTENSION_0_WORD_COUNT                                (0x1)
+#define CSC_D_POST_Y_EXTENSION_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_RESET_MASK                (_MK_MASK_CONST(0x3))
+#define CSC_D_POST_Y_EXTENSION_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_READ_MASK                 (_MK_MASK_CONST(0x3))
+#define CSC_D_POST_Y_EXTENSION_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT          (_MK_SHIFT_CONST(0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_RANGE                         (1:0)
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_WOFFSET                       (0x0)
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_ENTRY_PER_SLICE_0
+#define CSC_D_ENTRY_PER_SLICE_0                         (_MK_ADDR_CONST(0x6024))
+#define CSC_D_ENTRY_PER_SLICE_0_SECURE                                     (0x0)
+#define CSC_D_ENTRY_PER_SLICE_0_DUAL                                       (0x0)
+#define CSC_D_ENTRY_PER_SLICE_0_SCR                                          (0)
+#define CSC_D_ENTRY_PER_SLICE_0_WORD_COUNT                                 (0x1)
+#define CSC_D_ENTRY_PER_SLICE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_RESET_MASK               (_MK_MASK_CONST(0xfff))
+#define CSC_D_ENTRY_PER_SLICE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_READ_MASK                (_MK_MASK_CONST(0xfff))
+#define CSC_D_ENTRY_PER_SLICE_0_WRITE_MASK               (_MK_MASK_CONST(0xfff))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT               (_MK_SHIFT_CONST(0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD \
+	(_MK_FIELD_CONST(0xfff, CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_RANGE                             (11:0)
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_WOFFSET                            (0x0)
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_DEFAULT_MASK     (_MK_MASK_CONST(0xfff))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_WEIGHT_FORMAT_0
+#define CSC_D_WEIGHT_FORMAT_0                           (_MK_ADDR_CONST(0x6028))
+#define CSC_D_WEIGHT_FORMAT_0_SECURE                                       (0x0)
+#define CSC_D_WEIGHT_FORMAT_0_DUAL                                         (0x0)
+#define CSC_D_WEIGHT_FORMAT_0_SCR                                            (0)
+#define CSC_D_WEIGHT_FORMAT_0_WORD_COUNT                                   (0x1)
+#define CSC_D_WEIGHT_FORMAT_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_RESET_MASK                   (_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_READ_MASK                    (_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_WRITE_MASK                   (_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT           (_MK_SHIFT_CONST(0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD \
+	(_MK_FIELD_CONST(0x1, CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_RANGE                          (0:0)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_WOFFSET                        (0x0)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_INIT_ENUM             (UNCOMPRESSED)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED     (_MK_ENUM_CONST(0))
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED       (_MK_ENUM_CONST(1))
+
+
+// Register CSC_D_WEIGHT_SIZE_EXT_0_0
+#define CSC_D_WEIGHT_SIZE_EXT_0_0                       (_MK_ADDR_CONST(0x602c))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_SECURE                                   (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_DUAL                                     (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_SCR                                        (0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WORD_COUNT                               (0x1)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_RESET_MASK          (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_READ_MASK           (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WRITE_MASK          (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT    (_MK_SHIFT_CONST(0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_RANGE                   (4:0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_WOFFSET                 (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_RANGE                (20:16)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_WOFFSET                (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_WEIGHT_SIZE_EXT_1_0
+#define CSC_D_WEIGHT_SIZE_EXT_1_0                       (_MK_ADDR_CONST(0x6030))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_SECURE                                   (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_DUAL                                     (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_SCR                                        (0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WORD_COUNT                               (0x1)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_RESET_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_READ_MASK         (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_RANGE                (12:0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_WOFFSET               (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT      (_MK_SHIFT_CONST(16))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_RANGE                    (28:16)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_WOFFSET                    (0x0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_WEIGHT_BYTES_0
+#define CSC_D_WEIGHT_BYTES_0                            (_MK_ADDR_CONST(0x6034))
+#define CSC_D_WEIGHT_BYTES_0_SECURE                                        (0x0)
+#define CSC_D_WEIGHT_BYTES_0_DUAL                                          (0x0)
+#define CSC_D_WEIGHT_BYTES_0_SCR                                             (0)
+#define CSC_D_WEIGHT_BYTES_0_WORD_COUNT                                    (0x1)
+#define CSC_D_WEIGHT_BYTES_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_RESET_MASK             (_MK_MASK_CONST(0xffffff80))
+#define CSC_D_WEIGHT_BYTES_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_READ_MASK              (_MK_MASK_CONST(0xffffff80))
+#define CSC_D_WEIGHT_BYTES_0_WRITE_MASK             (_MK_MASK_CONST(0xffffff80))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT             (_MK_SHIFT_CONST(7))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD \
+	(_MK_FIELD_CONST(0x1ffffff, CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_RANGE                           (31:7)
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_WOFFSET                          (0x0)
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1ffffff))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_WMB_BYTES_0
+#define CSC_D_WMB_BYTES_0                               (_MK_ADDR_CONST(0x6038))
+#define CSC_D_WMB_BYTES_0_SECURE                                           (0x0)
+#define CSC_D_WMB_BYTES_0_DUAL                                             (0x0)
+#define CSC_D_WMB_BYTES_0_SCR                                                (0)
+#define CSC_D_WMB_BYTES_0_WORD_COUNT                                       (0x1)
+#define CSC_D_WMB_BYTES_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_RESET_MASK                 (_MK_MASK_CONST(0xfffff80))
+#define CSC_D_WMB_BYTES_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_READ_MASK                  (_MK_MASK_CONST(0xfffff80))
+#define CSC_D_WMB_BYTES_0_WRITE_MASK                 (_MK_MASK_CONST(0xfffff80))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT                   (_MK_SHIFT_CONST(7))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_FIELD \
+	(_MK_FIELD_CONST(0x1fffff, CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_RANGE                                 (27:7)
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_WOFFSET                                (0x0)
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_DEFAULT_MASK      (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_DATAOUT_SIZE_0_0
+#define CSC_D_DATAOUT_SIZE_0_0                          (_MK_ADDR_CONST(0x603c))
+#define CSC_D_DATAOUT_SIZE_0_0_SECURE                                      (0x0)
+#define CSC_D_DATAOUT_SIZE_0_0_DUAL                                        (0x0)
+#define CSC_D_DATAOUT_SIZE_0_0_SCR                                           (0)
+#define CSC_D_DATAOUT_SIZE_0_0_WORD_COUNT                                  (0x1)
+#define CSC_D_DATAOUT_SIZE_0_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_RESET_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_READ_MASK            (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_WRITE_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT          (_MK_SHIFT_CONST(0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_RANGE                        (12:0)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_WOFFSET                       (0x0)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT        (_MK_SHIFT_CONST(16))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_RANGE                      (28:16)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_WOFFSET                      (0x0)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_DATAOUT_SIZE_1_0
+#define CSC_D_DATAOUT_SIZE_1_0                          (_MK_ADDR_CONST(0x6040))
+#define CSC_D_DATAOUT_SIZE_1_0_SECURE                                      (0x0)
+#define CSC_D_DATAOUT_SIZE_1_0_DUAL                                        (0x0)
+#define CSC_D_DATAOUT_SIZE_1_0_SCR                                           (0)
+#define CSC_D_DATAOUT_SIZE_1_0_WORD_COUNT                                  (0x1)
+#define CSC_D_DATAOUT_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_RANGE                      (12:0)
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_WOFFSET                     (0x0)
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_ATOMICS_0
+#define CSC_D_ATOMICS_0                                 (_MK_ADDR_CONST(0x6044))
+#define CSC_D_ATOMICS_0_SECURE                                             (0x0)
+#define CSC_D_ATOMICS_0_DUAL                                               (0x0)
+#define CSC_D_ATOMICS_0_SCR                                                  (0)
+#define CSC_D_ATOMICS_0_WORD_COUNT                                         (0x1)
+#define CSC_D_ATOMICS_0_RESET_VAL                          (_MK_MASK_CONST(0x1))
+#define CSC_D_ATOMICS_0_RESET_MASK                    (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_ATOMICS_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_READ_MASK                     (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_ATOMICS_0_WRITE_MASK                    (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_ATOMICS_0_ATOMICS_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CSC_D_ATOMICS_0_ATOMICS_FIELD \
+	(_MK_FIELD_CONST(0x1fffff, CSC_D_ATOMICS_0_ATOMICS_SHIFT))
+#define CSC_D_ATOMICS_0_ATOMICS_RANGE                                     (20:0)
+#define CSC_D_ATOMICS_0_ATOMICS_WOFFSET                                    (0x0)
+#define CSC_D_ATOMICS_0_ATOMICS_DEFAULT                    (_MK_MASK_CONST(0x1))
+#define CSC_D_ATOMICS_0_ATOMICS_DEFAULT_MASK          (_MK_MASK_CONST(0x1fffff))
+#define CSC_D_ATOMICS_0_ATOMICS_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_ATOMICS_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_ATOMICS_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CSC_D_ATOMICS_0_ATOMICS_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_RELEASE_0
+#define CSC_D_RELEASE_0                                 (_MK_ADDR_CONST(0x6048))
+#define CSC_D_RELEASE_0_SECURE                                             (0x0)
+#define CSC_D_RELEASE_0_DUAL                                               (0x0)
+#define CSC_D_RELEASE_0_SCR                                                  (0)
+#define CSC_D_RELEASE_0_WORD_COUNT                                         (0x1)
+#define CSC_D_RELEASE_0_RESET_VAL                          (_MK_MASK_CONST(0x1))
+#define CSC_D_RELEASE_0_RESET_MASK                       (_MK_MASK_CONST(0xfff))
+#define CSC_D_RELEASE_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_READ_MASK                        (_MK_MASK_CONST(0xfff))
+#define CSC_D_RELEASE_0_WRITE_MASK                       (_MK_MASK_CONST(0xfff))
+#define CSC_D_RELEASE_0_RLS_SLICES_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CSC_D_RELEASE_0_RLS_SLICES_FIELD \
+	(_MK_FIELD_CONST(0xfff, CSC_D_RELEASE_0_RLS_SLICES_SHIFT))
+#define CSC_D_RELEASE_0_RLS_SLICES_RANGE                                  (11:0)
+#define CSC_D_RELEASE_0_RLS_SLICES_WOFFSET                                 (0x0)
+#define CSC_D_RELEASE_0_RLS_SLICES_DEFAULT                 (_MK_MASK_CONST(0x1))
+#define CSC_D_RELEASE_0_RLS_SLICES_DEFAULT_MASK          (_MK_MASK_CONST(0xfff))
+#define CSC_D_RELEASE_0_RLS_SLICES_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_RLS_SLICES_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_RLS_SLICES_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CSC_D_RELEASE_0_RLS_SLICES_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_CONV_STRIDE_EXT_0
+#define CSC_D_CONV_STRIDE_EXT_0                         (_MK_ADDR_CONST(0x604c))
+#define CSC_D_CONV_STRIDE_EXT_0_SECURE                                     (0x0)
+#define CSC_D_CONV_STRIDE_EXT_0_DUAL                                       (0x0)
+#define CSC_D_CONV_STRIDE_EXT_0_SCR                                          (0)
+#define CSC_D_CONV_STRIDE_EXT_0_WORD_COUNT                                 (0x1)
+#define CSC_D_CONV_STRIDE_EXT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_RESET_MASK             (_MK_MASK_CONST(0x70007))
+#define CSC_D_CONV_STRIDE_EXT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_READ_MASK              (_MK_MASK_CONST(0x70007))
+#define CSC_D_CONV_STRIDE_EXT_0_WRITE_MASK             (_MK_MASK_CONST(0x70007))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT     (_MK_SHIFT_CONST(0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_FIELD \
+	(_MK_FIELD_CONST(0x7, \
+	CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_RANGE                    (2:0)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_WOFFSET                  (0x0)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT    (_MK_SHIFT_CONST(16))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_FIELD \
+	(_MK_FIELD_CONST(0x7, \
+	CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_RANGE                  (18:16)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_WOFFSET                  (0x0)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_DILATION_EXT_0
+#define CSC_D_DILATION_EXT_0                            (_MK_ADDR_CONST(0x6050))
+#define CSC_D_DILATION_EXT_0_SECURE                                        (0x0)
+#define CSC_D_DILATION_EXT_0_DUAL                                          (0x0)
+#define CSC_D_DILATION_EXT_0_SCR                                             (0)
+#define CSC_D_DILATION_EXT_0_WORD_COUNT                                    (0x1)
+#define CSC_D_DILATION_EXT_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_RESET_MASK               (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_DILATION_EXT_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_READ_MASK                (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_DILATION_EXT_0_WRITE_MASK               (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT           (_MK_SHIFT_CONST(0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_RANGE                          (4:0)
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_WOFFSET                        (0x0)
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT          (_MK_SHIFT_CONST(16))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_RANGE                        (20:16)
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_WOFFSET                        (0x0)
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_ZERO_PADDING_0
+#define CSC_D_ZERO_PADDING_0                            (_MK_ADDR_CONST(0x6054))
+#define CSC_D_ZERO_PADDING_0_SECURE                                        (0x0)
+#define CSC_D_ZERO_PADDING_0_DUAL                                          (0x0)
+#define CSC_D_ZERO_PADDING_0_SCR                                             (0)
+#define CSC_D_ZERO_PADDING_0_WORD_COUNT                                    (0x1)
+#define CSC_D_ZERO_PADDING_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_RESET_MASK               (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_ZERO_PADDING_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_READ_MASK                (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_ZERO_PADDING_0_WRITE_MASK               (_MK_MASK_CONST(0x1f001f))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_RANGE                                (4:0)
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_WOFFSET                              (0x0)
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT                 (_MK_SHIFT_CONST(16))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_FIELD \
+	(_MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_RANGE                               (20:16)
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_WOFFSET                               (0x0)
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_DEFAULT_MASK         (_MK_MASK_CONST(0x1f))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_ZERO_PADDING_VALUE_0
+#define CSC_D_ZERO_PADDING_VALUE_0                      (_MK_ADDR_CONST(0x6058))
+#define CSC_D_ZERO_PADDING_VALUE_0_SECURE                                  (0x0)
+#define CSC_D_ZERO_PADDING_VALUE_0_DUAL                                    (0x0)
+#define CSC_D_ZERO_PADDING_VALUE_0_SCR                                       (0)
+#define CSC_D_ZERO_PADDING_VALUE_0_WORD_COUNT                              (0x1)
+#define CSC_D_ZERO_PADDING_VALUE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_RESET_MASK           (_MK_MASK_CONST(0xffff))
+#define CSC_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_READ_MASK            (_MK_MASK_CONST(0xffff))
+#define CSC_D_ZERO_PADDING_VALUE_0_WRITE_MASK           (_MK_MASK_CONST(0xffff))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT          (_MK_SHIFT_CONST(0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD \
+	(_MK_FIELD_CONST(0xffff, CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_RANGE                        (15:0)
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_WOFFSET                       (0x0)
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_BANK_0
+#define CSC_D_BANK_0                                    (_MK_ADDR_CONST(0x605c))
+#define CSC_D_BANK_0_SECURE                                                (0x0)
+#define CSC_D_BANK_0_DUAL                                                  (0x0)
+#define CSC_D_BANK_0_SCR                                                     (0)
+#define CSC_D_BANK_0_WORD_COUNT                                            (0x1)
+#define CSC_D_BANK_0_RESET_VAL                             (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_RESET_MASK                        (_MK_MASK_CONST(0xf000f))
+#define CSC_D_BANK_0_SW_DEFAULT_VAL                        (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_SW_DEFAULT_MASK                       (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_READ_MASK                         (_MK_MASK_CONST(0xf000f))
+#define CSC_D_BANK_0_WRITE_MASK                        (_MK_MASK_CONST(0xf000f))
+#define CSC_D_BANK_0_DATA_BANK_SHIFT                        (_MK_SHIFT_CONST(0))
+#define CSC_D_BANK_0_DATA_BANK_FIELD \
+	(_MK_FIELD_CONST(0xf, CSC_D_BANK_0_DATA_BANK_SHIFT))
+#define CSC_D_BANK_0_DATA_BANK_RANGE                                       (3:0)
+#define CSC_D_BANK_0_DATA_BANK_WOFFSET                                     (0x0)
+#define CSC_D_BANK_0_DATA_BANK_DEFAULT                     (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_DATA_BANK_DEFAULT_MASK                (_MK_MASK_CONST(0xf))
+#define CSC_D_BANK_0_DATA_BANK_SW_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_DATA_BANK_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_DATA_BANK_PARITY_PROTECTION           (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_DATA_BANK_PLATFORM_DEPENDENT          (_MK_MASK_CONST(0x1))
+
+#define CSC_D_BANK_0_WEIGHT_BANK_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CSC_D_BANK_0_WEIGHT_BANK_FIELD \
+	(_MK_FIELD_CONST(0xf, CSC_D_BANK_0_WEIGHT_BANK_SHIFT))
+#define CSC_D_BANK_0_WEIGHT_BANK_RANGE                                   (19:16)
+#define CSC_D_BANK_0_WEIGHT_BANK_WOFFSET                                   (0x0)
+#define CSC_D_BANK_0_WEIGHT_BANK_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_WEIGHT_BANK_DEFAULT_MASK              (_MK_MASK_CONST(0xf))
+#define CSC_D_BANK_0_WEIGHT_BANK_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_WEIGHT_BANK_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_WEIGHT_BANK_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CSC_D_BANK_0_WEIGHT_BANK_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_PRA_CFG_0
+#define CSC_D_PRA_CFG_0                                 (_MK_ADDR_CONST(0x6060))
+#define CSC_D_PRA_CFG_0_SECURE                                             (0x0)
+#define CSC_D_PRA_CFG_0_DUAL                                               (0x0)
+#define CSC_D_PRA_CFG_0_SCR                                                  (0)
+#define CSC_D_PRA_CFG_0_WORD_COUNT                                         (0x1)
+#define CSC_D_PRA_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_RESET_MASK                         (_MK_MASK_CONST(0x3))
+#define CSC_D_PRA_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_READ_MASK                          (_MK_MASK_CONST(0x3))
+#define CSC_D_PRA_CFG_0_WRITE_MASK                         (_MK_MASK_CONST(0x3))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3, CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_RANGE                                 (1:0)
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_WOFFSET                               (0x0)
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+
+
+// Register CSC_D_CYA_0
+#define CSC_D_CYA_0                                     (_MK_ADDR_CONST(0x6064))
+#define CSC_D_CYA_0_SECURE                                                 (0x0)
+#define CSC_D_CYA_0_DUAL                                                   (0x0)
+#define CSC_D_CYA_0_SCR                                                      (0)
+#define CSC_D_CYA_0_WORD_COUNT                                             (0x1)
+#define CSC_D_CYA_0_RESET_VAL                              (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_RESET_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CSC_D_CYA_0_SW_DEFAULT_VAL                         (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_SW_DEFAULT_MASK                        (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_READ_MASK                       (_MK_MASK_CONST(0xffffffff))
+#define CSC_D_CYA_0_WRITE_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CSC_D_CYA_0_CYA_SHIFT                               (_MK_SHIFT_CONST(0))
+#define CSC_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, CSC_D_CYA_0_CYA_SHIFT))
+#define CSC_D_CYA_0_CYA_RANGE                                             (31:0)
+#define CSC_D_CYA_0_CYA_WOFFSET                                            (0x0)
+#define CSC_D_CYA_0_CYA_DEFAULT                            (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_CYA_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff))
+#define CSC_D_CYA_0_CYA_SW_DEFAULT                         (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_CYA_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_CYA_PARITY_PROTECTION                  (_MK_MASK_CONST(0x0))
+#define CSC_D_CYA_0_CYA_PLATFORM_DEPENDENT                 (_MK_MASK_CONST(0x1))
+
+
+// Register CMAC_A_S_STATUS_0
+#define CMAC_A_S_STATUS_0                               (_MK_ADDR_CONST(0x7000))
+#define CMAC_A_S_STATUS_0_SECURE                                           (0x0)
+#define CMAC_A_S_STATUS_0_DUAL                                             (0x0)
+#define CMAC_A_S_STATUS_0_SCR                                                (0)
+#define CMAC_A_S_STATUS_0_WORD_COUNT                                       (0x1)
+#define CMAC_A_S_STATUS_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_RESET_MASK                   (_MK_MASK_CONST(0x30003))
+#define CMAC_A_S_STATUS_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_READ_MASK                    (_MK_MASK_CONST(0x30003))
+#define CMAC_A_S_STATUS_0_WRITE_MASK                       (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CMAC_A_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_0_SHIFT))
+#define CMAC_A_S_STATUS_0_STATUS_0_RANGE                                   (1:0)
+#define CMAC_A_S_STATUS_0_STATUS_0_WOFFSET                                 (0x0)
+#define CMAC_A_S_STATUS_0_STATUS_0_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
+#define CMAC_A_S_STATUS_0_STATUS_0_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_STATUS_0_STATUS_0_INIT_ENUM                              (IDLE)
+#define CMAC_A_S_STATUS_0_STATUS_0_IDLE                      (_MK_ENUM_CONST(0))
+#define CMAC_A_S_STATUS_0_STATUS_0_RUNNING                   (_MK_ENUM_CONST(1))
+#define CMAC_A_S_STATUS_0_STATUS_0_PENDING                   (_MK_ENUM_CONST(2))
+
+#define CMAC_A_S_STATUS_0_STATUS_1_SHIFT                   (_MK_SHIFT_CONST(16))
+#define CMAC_A_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_1_SHIFT))
+#define CMAC_A_S_STATUS_0_STATUS_1_RANGE                                 (17:16)
+#define CMAC_A_S_STATUS_0_STATUS_1_WOFFSET                                 (0x0)
+#define CMAC_A_S_STATUS_0_STATUS_1_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_1_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
+#define CMAC_A_S_STATUS_0_STATUS_1_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_1_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_STATUS_0_STATUS_1_INIT_ENUM                              (IDLE)
+#define CMAC_A_S_STATUS_0_STATUS_1_IDLE                      (_MK_ENUM_CONST(0))
+#define CMAC_A_S_STATUS_0_STATUS_1_RUNNING                   (_MK_ENUM_CONST(1))
+#define CMAC_A_S_STATUS_0_STATUS_1_PENDING                   (_MK_ENUM_CONST(2))
+
+
+// Register CMAC_A_S_POINTER_0
+#define CMAC_A_S_POINTER_0                              (_MK_ADDR_CONST(0x7004))
+#define CMAC_A_S_POINTER_0_SECURE                                          (0x0)
+#define CMAC_A_S_POINTER_0_DUAL                                            (0x0)
+#define CMAC_A_S_POINTER_0_SCR                                               (0)
+#define CMAC_A_S_POINTER_0_WORD_COUNT                                      (0x1)
+#define CMAC_A_S_POINTER_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_RESET_MASK                  (_MK_MASK_CONST(0x10001))
+#define CMAC_A_S_POINTER_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_READ_MASK                   (_MK_MASK_CONST(0x10001))
+#define CMAC_A_S_POINTER_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_PRODUCER_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CMAC_A_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_PRODUCER_SHIFT))
+#define CMAC_A_S_POINTER_0_PRODUCER_RANGE                                  (0:0)
+#define CMAC_A_S_POINTER_0_PRODUCER_WOFFSET                                (0x0)
+#define CMAC_A_S_POINTER_0_PRODUCER_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_PRODUCER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_PRODUCER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_PRODUCER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_PRODUCER_INIT_ENUM                          (GROUP_0)
+#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_0                  (_MK_ENUM_CONST(0))
+#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_1                  (_MK_ENUM_CONST(1))
+
+#define CMAC_A_S_POINTER_0_CONSUMER_SHIFT                  (_MK_SHIFT_CONST(16))
+#define CMAC_A_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_CONSUMER_SHIFT))
+#define CMAC_A_S_POINTER_0_CONSUMER_RANGE                                (16:16)
+#define CMAC_A_S_POINTER_0_CONSUMER_WOFFSET                                (0x0)
+#define CMAC_A_S_POINTER_0_CONSUMER_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_CONSUMER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_CONSUMER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_CONSUMER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CMAC_A_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CMAC_A_S_POINTER_0_CONSUMER_INIT_ENUM                          (GROUP_0)
+#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_0                  (_MK_ENUM_CONST(0))
+#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_1                  (_MK_ENUM_CONST(1))
+
+
+// Register CMAC_A_D_OP_ENABLE_0
+#define CMAC_A_D_OP_ENABLE_0                            (_MK_ADDR_CONST(0x7008))
+#define CMAC_A_D_OP_ENABLE_0_SECURE                                        (0x0)
+#define CMAC_A_D_OP_ENABLE_0_DUAL                                          (0x0)
+#define CMAC_A_D_OP_ENABLE_0_SCR                                             (0)
+#define CMAC_A_D_OP_ENABLE_0_WORD_COUNT                                    (0x1)
+#define CMAC_A_D_OP_ENABLE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_READ_MASK                     (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_RANGE                                   (0:0)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_WOFFSET                                 (0x0)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_INIT_ENUM                           (DISABLE)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_DISABLE                   (_MK_ENUM_CONST(0))
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_ENABLE                    (_MK_ENUM_CONST(1))
+
+
+// Register CMAC_A_D_MISC_CFG_0
+#define CMAC_A_D_MISC_CFG_0                             (_MK_ADDR_CONST(0x700c))
+#define CMAC_A_D_MISC_CFG_0_SECURE                                         (0x0)
+#define CMAC_A_D_MISC_CFG_0_DUAL                                           (0x0)
+#define CMAC_A_D_MISC_CFG_0_SCR                                              (0)
+#define CMAC_A_D_MISC_CFG_0_WORD_COUNT                                     (0x1)
+#define CMAC_A_D_MISC_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x1000))
+#define CMAC_A_D_MISC_CFG_0_RESET_MASK                  (_MK_MASK_CONST(0x3001))
+#define CMAC_A_D_MISC_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_READ_MASK                   (_MK_MASK_CONST(0x3001))
+#define CMAC_A_D_MISC_CFG_0_WRITE_MASK                  (_MK_MASK_CONST(0x3001))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_RANGE                                (0:0)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WOFFSET                              (0x0)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                         (DIRECT)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DIRECT                 (_MK_ENUM_CONST(0))
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WINOGRAD               (_MK_ENUM_CONST(1))
+
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT           (_MK_SHIFT_CONST(12))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_RANGE                         (13:12)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                         (0x0)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_DEFAULT         (_MK_MASK_CONST(0x1))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK    (_MK_MASK_CONST(0x3))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                     (INT16)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT8              (_MK_ENUM_CONST(0))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT16             (_MK_ENUM_CONST(1))
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FP16              (_MK_ENUM_CONST(2))
+
+
+// Register CMAC_B_S_STATUS_0
+#define CMAC_B_S_STATUS_0                               (_MK_ADDR_CONST(0x8000))
+#define CMAC_B_S_STATUS_0_SECURE                                           (0x0)
+#define CMAC_B_S_STATUS_0_DUAL                                             (0x0)
+#define CMAC_B_S_STATUS_0_SCR                                                (0)
+#define CMAC_B_S_STATUS_0_WORD_COUNT                                       (0x1)
+#define CMAC_B_S_STATUS_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_RESET_MASK                   (_MK_MASK_CONST(0x30003))
+#define CMAC_B_S_STATUS_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_READ_MASK                    (_MK_MASK_CONST(0x30003))
+#define CMAC_B_S_STATUS_0_WRITE_MASK                       (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CMAC_B_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_0_SHIFT))
+#define CMAC_B_S_STATUS_0_STATUS_0_RANGE                                   (1:0)
+#define CMAC_B_S_STATUS_0_STATUS_0_WOFFSET                                 (0x0)
+#define CMAC_B_S_STATUS_0_STATUS_0_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
+#define CMAC_B_S_STATUS_0_STATUS_0_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_STATUS_0_STATUS_0_INIT_ENUM                              (IDLE)
+#define CMAC_B_S_STATUS_0_STATUS_0_IDLE                      (_MK_ENUM_CONST(0))
+#define CMAC_B_S_STATUS_0_STATUS_0_RUNNING                   (_MK_ENUM_CONST(1))
+#define CMAC_B_S_STATUS_0_STATUS_0_PENDING                   (_MK_ENUM_CONST(2))
+
+#define CMAC_B_S_STATUS_0_STATUS_1_SHIFT                   (_MK_SHIFT_CONST(16))
+#define CMAC_B_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_1_SHIFT))
+#define CMAC_B_S_STATUS_0_STATUS_1_RANGE                                 (17:16)
+#define CMAC_B_S_STATUS_0_STATUS_1_WOFFSET                                 (0x0)
+#define CMAC_B_S_STATUS_0_STATUS_1_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_1_DEFAULT_MASK            (_MK_MASK_CONST(0x3))
+#define CMAC_B_S_STATUS_0_STATUS_1_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_1_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_STATUS_0_STATUS_1_INIT_ENUM                              (IDLE)
+#define CMAC_B_S_STATUS_0_STATUS_1_IDLE                      (_MK_ENUM_CONST(0))
+#define CMAC_B_S_STATUS_0_STATUS_1_RUNNING                   (_MK_ENUM_CONST(1))
+#define CMAC_B_S_STATUS_0_STATUS_1_PENDING                   (_MK_ENUM_CONST(2))
+
+
+// Register CMAC_B_S_POINTER_0
+#define CMAC_B_S_POINTER_0                              (_MK_ADDR_CONST(0x8004))
+#define CMAC_B_S_POINTER_0_SECURE                                          (0x0)
+#define CMAC_B_S_POINTER_0_DUAL                                            (0x0)
+#define CMAC_B_S_POINTER_0_SCR                                               (0)
+#define CMAC_B_S_POINTER_0_WORD_COUNT                                      (0x1)
+#define CMAC_B_S_POINTER_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_RESET_MASK                  (_MK_MASK_CONST(0x10001))
+#define CMAC_B_S_POINTER_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_READ_MASK                   (_MK_MASK_CONST(0x10001))
+#define CMAC_B_S_POINTER_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_PRODUCER_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CMAC_B_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_PRODUCER_SHIFT))
+#define CMAC_B_S_POINTER_0_PRODUCER_RANGE                                  (0:0)
+#define CMAC_B_S_POINTER_0_PRODUCER_WOFFSET                                (0x0)
+#define CMAC_B_S_POINTER_0_PRODUCER_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_PRODUCER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_PRODUCER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_PRODUCER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_PRODUCER_INIT_ENUM                          (GROUP_0)
+#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_0                  (_MK_ENUM_CONST(0))
+#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_1                  (_MK_ENUM_CONST(1))
+
+#define CMAC_B_S_POINTER_0_CONSUMER_SHIFT                  (_MK_SHIFT_CONST(16))
+#define CMAC_B_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_CONSUMER_SHIFT))
+#define CMAC_B_S_POINTER_0_CONSUMER_RANGE                                (16:16)
+#define CMAC_B_S_POINTER_0_CONSUMER_WOFFSET                                (0x0)
+#define CMAC_B_S_POINTER_0_CONSUMER_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_CONSUMER_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_CONSUMER_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_CONSUMER_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CMAC_B_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CMAC_B_S_POINTER_0_CONSUMER_INIT_ENUM                          (GROUP_0)
+#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_0                  (_MK_ENUM_CONST(0))
+#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_1                  (_MK_ENUM_CONST(1))
+
+
+// Register CMAC_B_D_OP_ENABLE_0
+#define CMAC_B_D_OP_ENABLE_0                            (_MK_ADDR_CONST(0x8008))
+#define CMAC_B_D_OP_ENABLE_0_SECURE                                        (0x0)
+#define CMAC_B_D_OP_ENABLE_0_DUAL                                          (0x0)
+#define CMAC_B_D_OP_ENABLE_0_SCR                                             (0)
+#define CMAC_B_D_OP_ENABLE_0_WORD_COUNT                                    (0x1)
+#define CMAC_B_D_OP_ENABLE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_RESET_MASK                    (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_READ_MASK                     (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_RANGE                                   (0:0)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_WOFFSET                                 (0x0)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_INIT_ENUM                           (DISABLE)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_DISABLE                   (_MK_ENUM_CONST(0))
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_ENABLE                    (_MK_ENUM_CONST(1))
+
+
+// Register CMAC_B_D_MISC_CFG_0
+#define CMAC_B_D_MISC_CFG_0                             (_MK_ADDR_CONST(0x800c))
+#define CMAC_B_D_MISC_CFG_0_SECURE                                         (0x0)
+#define CMAC_B_D_MISC_CFG_0_DUAL                                           (0x0)
+#define CMAC_B_D_MISC_CFG_0_SCR                                              (0)
+#define CMAC_B_D_MISC_CFG_0_WORD_COUNT                                     (0x1)
+#define CMAC_B_D_MISC_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x1000))
+#define CMAC_B_D_MISC_CFG_0_RESET_MASK                  (_MK_MASK_CONST(0x3001))
+#define CMAC_B_D_MISC_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_READ_MASK                   (_MK_MASK_CONST(0x3001))
+#define CMAC_B_D_MISC_CFG_0_WRITE_MASK                  (_MK_MASK_CONST(0x3001))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_RANGE                                (0:0)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WOFFSET                              (0x0)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                         (DIRECT)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DIRECT                 (_MK_ENUM_CONST(0))
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WINOGRAD               (_MK_ENUM_CONST(1))
+
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT           (_MK_SHIFT_CONST(12))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_RANGE                         (13:12)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                         (0x0)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_DEFAULT         (_MK_MASK_CONST(0x1))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK    (_MK_MASK_CONST(0x3))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                     (INT16)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT8              (_MK_ENUM_CONST(0))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT16             (_MK_ENUM_CONST(1))
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FP16              (_MK_ENUM_CONST(2))
+
+
+// Register CACC_S_STATUS_0
+#define CACC_S_STATUS_0                                 (_MK_ADDR_CONST(0x9000))
+#define CACC_S_STATUS_0_SECURE                                             (0x0)
+#define CACC_S_STATUS_0_DUAL                                               (0x0)
+#define CACC_S_STATUS_0_SCR                                                  (0)
+#define CACC_S_STATUS_0_WORD_COUNT                                         (0x1)
+#define CACC_S_STATUS_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_RESET_MASK                     (_MK_MASK_CONST(0x30003))
+#define CACC_S_STATUS_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_READ_MASK                      (_MK_MASK_CONST(0x30003))
+#define CACC_S_STATUS_0_WRITE_MASK                         (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CACC_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_0_SHIFT))
+#define CACC_S_STATUS_0_STATUS_0_RANGE                                     (1:0)
+#define CACC_S_STATUS_0_STATUS_0_WOFFSET                                   (0x0)
+#define CACC_S_STATUS_0_STATUS_0_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
+#define CACC_S_STATUS_0_STATUS_0_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CACC_S_STATUS_0_STATUS_0_INIT_ENUM                                (IDLE)
+#define CACC_S_STATUS_0_STATUS_0_IDLE                        (_MK_ENUM_CONST(0))
+#define CACC_S_STATUS_0_STATUS_0_RUNNING                     (_MK_ENUM_CONST(1))
+#define CACC_S_STATUS_0_STATUS_0_PENDING                     (_MK_ENUM_CONST(2))
+
+#define CACC_S_STATUS_0_STATUS_1_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CACC_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_1_SHIFT))
+#define CACC_S_STATUS_0_STATUS_1_RANGE                                   (17:16)
+#define CACC_S_STATUS_0_STATUS_1_WOFFSET                                   (0x0)
+#define CACC_S_STATUS_0_STATUS_1_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_1_DEFAULT_MASK              (_MK_MASK_CONST(0x3))
+#define CACC_S_STATUS_0_STATUS_1_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_1_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CACC_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CACC_S_STATUS_0_STATUS_1_INIT_ENUM                                (IDLE)
+#define CACC_S_STATUS_0_STATUS_1_IDLE                        (_MK_ENUM_CONST(0))
+#define CACC_S_STATUS_0_STATUS_1_RUNNING                     (_MK_ENUM_CONST(1))
+#define CACC_S_STATUS_0_STATUS_1_PENDING                     (_MK_ENUM_CONST(2))
+
+
+// Register CACC_S_POINTER_0
+#define CACC_S_POINTER_0                                (_MK_ADDR_CONST(0x9004))
+#define CACC_S_POINTER_0_SECURE                                            (0x0)
+#define CACC_S_POINTER_0_DUAL                                              (0x0)
+#define CACC_S_POINTER_0_SCR                                                 (0)
+#define CACC_S_POINTER_0_WORD_COUNT                                        (0x1)
+#define CACC_S_POINTER_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_RESET_MASK                    (_MK_MASK_CONST(0x10001))
+#define CACC_S_POINTER_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_READ_MASK                     (_MK_MASK_CONST(0x10001))
+#define CACC_S_POINTER_0_WRITE_MASK                        (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_PRODUCER_SHIFT                     (_MK_SHIFT_CONST(0))
+#define CACC_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_S_POINTER_0_PRODUCER_SHIFT))
+#define CACC_S_POINTER_0_PRODUCER_RANGE                                    (0:0)
+#define CACC_S_POINTER_0_PRODUCER_WOFFSET                                  (0x0)
+#define CACC_S_POINTER_0_PRODUCER_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_PRODUCER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_PRODUCER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_PRODUCER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_PRODUCER_INIT_ENUM                            (GROUP_0)
+#define CACC_S_POINTER_0_PRODUCER_GROUP_0                    (_MK_ENUM_CONST(0))
+#define CACC_S_POINTER_0_PRODUCER_GROUP_1                    (_MK_ENUM_CONST(1))
+
+#define CACC_S_POINTER_0_CONSUMER_SHIFT                    (_MK_SHIFT_CONST(16))
+#define CACC_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_S_POINTER_0_CONSUMER_SHIFT))
+#define CACC_S_POINTER_0_CONSUMER_RANGE                                  (16:16)
+#define CACC_S_POINTER_0_CONSUMER_WOFFSET                                  (0x0)
+#define CACC_S_POINTER_0_CONSUMER_DEFAULT                  (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_CONSUMER_DEFAULT_MASK             (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_CONSUMER_SW_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_CONSUMER_PARITY_PROTECTION        (_MK_MASK_CONST(0x0))
+#define CACC_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT       (_MK_MASK_CONST(0x1))
+#define CACC_S_POINTER_0_CONSUMER_INIT_ENUM                            (GROUP_0)
+#define CACC_S_POINTER_0_CONSUMER_GROUP_0                    (_MK_ENUM_CONST(0))
+#define CACC_S_POINTER_0_CONSUMER_GROUP_1                    (_MK_ENUM_CONST(1))
+
+
+// Register CACC_D_OP_ENABLE_0
+#define CACC_D_OP_ENABLE_0                              (_MK_ADDR_CONST(0x9008))
+#define CACC_D_OP_ENABLE_0_SECURE                                          (0x0)
+#define CACC_D_OP_ENABLE_0_DUAL                                            (0x0)
+#define CACC_D_OP_ENABLE_0_SCR                                               (0)
+#define CACC_D_OP_ENABLE_0_WORD_COUNT                                      (0x1)
+#define CACC_D_OP_ENABLE_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_RESET_MASK                      (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_READ_MASK                       (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_WRITE_MASK                      (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_OP_EN_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CACC_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CACC_D_OP_ENABLE_0_OP_EN_RANGE                                     (0:0)
+#define CACC_D_OP_ENABLE_0_OP_EN_WOFFSET                                   (0x0)
+#define CACC_D_OP_ENABLE_0_OP_EN_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CACC_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CACC_D_OP_ENABLE_0_OP_EN_INIT_ENUM                             (DISABLE)
+#define CACC_D_OP_ENABLE_0_OP_EN_DISABLE                     (_MK_ENUM_CONST(0))
+#define CACC_D_OP_ENABLE_0_OP_EN_ENABLE                      (_MK_ENUM_CONST(1))
+
+
+// Register CACC_D_MISC_CFG_0
+#define CACC_D_MISC_CFG_0                               (_MK_ADDR_CONST(0x900c))
+#define CACC_D_MISC_CFG_0_SECURE                                           (0x0)
+#define CACC_D_MISC_CFG_0_DUAL                                             (0x0)
+#define CACC_D_MISC_CFG_0_SCR                                                (0)
+#define CACC_D_MISC_CFG_0_WORD_COUNT                                       (0x1)
+#define CACC_D_MISC_CFG_0_RESET_VAL                     (_MK_MASK_CONST(0x1000))
+#define CACC_D_MISC_CFG_0_RESET_MASK                    (_MK_MASK_CONST(0x3001))
+#define CACC_D_MISC_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_READ_MASK                     (_MK_MASK_CONST(0x3001))
+#define CACC_D_MISC_CFG_0_WRITE_MASK                    (_MK_MASK_CONST(0x3001))
+#define CACC_D_MISC_CFG_0_CONV_MODE_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_D_MISC_CFG_0_CONV_MODE_SHIFT))
+#define CACC_D_MISC_CFG_0_CONV_MODE_RANGE                                  (0:0)
+#define CACC_D_MISC_CFG_0_CONV_MODE_WOFFSET                                (0x0)
+#define CACC_D_MISC_CFG_0_CONV_MODE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define CACC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CACC_D_MISC_CFG_0_CONV_MODE_INIT_ENUM                           (DIRECT)
+#define CACC_D_MISC_CFG_0_CONV_MODE_DIRECT                   (_MK_ENUM_CONST(0))
+#define CACC_D_MISC_CFG_0_CONV_MODE_WINOGRAD                 (_MK_ENUM_CONST(1))
+
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT             (_MK_SHIFT_CONST(12))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_RANGE                           (13:12)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_WOFFSET                           (0x0)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT           (_MK_MASK_CONST(0x1))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_DEFAULT_MASK      (_MK_MASK_CONST(0x3))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_INIT_ENUM                       (INT16)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT8                (_MK_ENUM_CONST(0))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT16               (_MK_ENUM_CONST(1))
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_FP16                (_MK_ENUM_CONST(2))
+
+
+// Register CACC_D_DATAOUT_SIZE_0_0
+#define CACC_D_DATAOUT_SIZE_0_0                         (_MK_ADDR_CONST(0x9010))
+#define CACC_D_DATAOUT_SIZE_0_0_SECURE                                     (0x0)
+#define CACC_D_DATAOUT_SIZE_0_0_DUAL                                       (0x0)
+#define CACC_D_DATAOUT_SIZE_0_0_SCR                                          (0)
+#define CACC_D_DATAOUT_SIZE_0_0_WORD_COUNT                                 (0x1)
+#define CACC_D_DATAOUT_SIZE_0_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_RESET_MASK          (_MK_MASK_CONST(0x1fff1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_READ_MASK           (_MK_MASK_CONST(0x1fff1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_WRITE_MASK          (_MK_MASK_CONST(0x1fff1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT         (_MK_SHIFT_CONST(0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_RANGE                       (12:0)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_WOFFSET                      (0x0)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT       (_MK_SHIFT_CONST(16))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_RANGE                     (28:16)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_WOFFSET                     (0x0)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_DATAOUT_SIZE_1_0
+#define CACC_D_DATAOUT_SIZE_1_0                         (_MK_ADDR_CONST(0x9014))
+#define CACC_D_DATAOUT_SIZE_1_0_SECURE                                     (0x0)
+#define CACC_D_DATAOUT_SIZE_1_0_DUAL                                       (0x0)
+#define CACC_D_DATAOUT_SIZE_1_0_SCR                                          (0)
+#define CACC_D_DATAOUT_SIZE_1_0_WORD_COUNT                                 (0x1)
+#define CACC_D_DATAOUT_SIZE_1_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_RESET_MASK              (_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_READ_MASK               (_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_1_0_WRITE_MASK              (_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT       (_MK_SHIFT_CONST(0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_RANGE                     (12:0)
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_WOFFSET                    (0x0)
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_DATAOUT_ADDR_0
+#define CACC_D_DATAOUT_ADDR_0                           (_MK_ADDR_CONST(0x9018))
+#define CACC_D_DATAOUT_ADDR_0_SECURE                                       (0x0)
+#define CACC_D_DATAOUT_ADDR_0_DUAL                                         (0x0)
+#define CACC_D_DATAOUT_ADDR_0_SCR                                            (0)
+#define CACC_D_DATAOUT_ADDR_0_WORD_COUNT                                   (0x1)
+#define CACC_D_DATAOUT_ADDR_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CACC_D_DATAOUT_ADDR_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define CACC_D_DATAOUT_ADDR_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT            (_MK_SHIFT_CONST(5))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_RANGE                          (31:5)
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_WOFFSET                         (0x0)
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_BATCH_NUMBER_0
+#define CACC_D_BATCH_NUMBER_0                           (_MK_ADDR_CONST(0x901c))
+#define CACC_D_BATCH_NUMBER_0_SECURE                                       (0x0)
+#define CACC_D_BATCH_NUMBER_0_DUAL                                         (0x0)
+#define CACC_D_BATCH_NUMBER_0_SCR                                            (0)
+#define CACC_D_BATCH_NUMBER_0_WORD_COUNT                                   (0x1)
+#define CACC_D_BATCH_NUMBER_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_RESET_MASK                  (_MK_MASK_CONST(0x1f))
+#define CACC_D_BATCH_NUMBER_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_READ_MASK                   (_MK_MASK_CONST(0x1f))
+#define CACC_D_BATCH_NUMBER_0_WRITE_MASK                  (_MK_MASK_CONST(0x1f))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_FIELD \
+	(_MK_FIELD_CONST(0x1f, CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_RANGE                                (4:0)
+#define CACC_D_BATCH_NUMBER_0_BATCHES_WOFFSET                              (0x0)
+#define CACC_D_BATCH_NUMBER_0_BATCHES_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_DEFAULT_MASK        (_MK_MASK_CONST(0x1f))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CACC_D_BATCH_NUMBER_0_BATCHES_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_LINE_STRIDE_0
+#define CACC_D_LINE_STRIDE_0                            (_MK_ADDR_CONST(0x9020))
+#define CACC_D_LINE_STRIDE_0_SECURE                                        (0x0)
+#define CACC_D_LINE_STRIDE_0_DUAL                                          (0x0)
+#define CACC_D_LINE_STRIDE_0_SCR                                             (0)
+#define CACC_D_LINE_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CACC_D_LINE_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_RESET_MASK               (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_LINE_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_READ_MASK                (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_LINE_STRIDE_0_WRITE_MASK               (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_RANGE                            (23:5)
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_WOFFSET                           (0x0)
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_SURF_STRIDE_0
+#define CACC_D_SURF_STRIDE_0                            (_MK_ADDR_CONST(0x9024))
+#define CACC_D_SURF_STRIDE_0_SECURE                                        (0x0)
+#define CACC_D_SURF_STRIDE_0_DUAL                                          (0x0)
+#define CACC_D_SURF_STRIDE_0_SCR                                             (0)
+#define CACC_D_SURF_STRIDE_0_WORD_COUNT                                    (0x1)
+#define CACC_D_SURF_STRIDE_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_RESET_MASK               (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_SURF_STRIDE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_READ_MASK                (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_SURF_STRIDE_0_WRITE_MASK               (_MK_MASK_CONST(0xffffe0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT              (_MK_SHIFT_CONST(5))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_RANGE                            (23:5)
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_WOFFSET                           (0x0)
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_DATAOUT_MAP_0
+#define CACC_D_DATAOUT_MAP_0                            (_MK_ADDR_CONST(0x9028))
+#define CACC_D_DATAOUT_MAP_0_SECURE                                        (0x0)
+#define CACC_D_DATAOUT_MAP_0_DUAL                                          (0x0)
+#define CACC_D_DATAOUT_MAP_0_SCR                                             (0)
+#define CACC_D_DATAOUT_MAP_0_WORD_COUNT                                    (0x1)
+#define CACC_D_DATAOUT_MAP_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
+#define CACC_D_DATAOUT_MAP_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
+#define CACC_D_DATAOUT_MAP_0_WRITE_MASK                (_MK_MASK_CONST(0x10001))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT              (_MK_SHIFT_CONST(0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_RANGE                             (0:0)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_WOFFSET                           (0x0)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_INIT_ENUM                       (FALSE)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FALSE               (_MK_ENUM_CONST(0))
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE                (_MK_ENUM_CONST(1))
+
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT             (_MK_SHIFT_CONST(16))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FIELD \
+	(_MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_RANGE                           (16:16)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_WOFFSET                           (0x0)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_INIT_ENUM                       (FALSE)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FALSE               (_MK_ENUM_CONST(0))
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE                (_MK_ENUM_CONST(1))
+
+
+// Register CACC_D_CLIP_CFG_0
+#define CACC_D_CLIP_CFG_0                               (_MK_ADDR_CONST(0x902c))
+#define CACC_D_CLIP_CFG_0_SECURE                                           (0x0)
+#define CACC_D_CLIP_CFG_0_DUAL                                             (0x0)
+#define CACC_D_CLIP_CFG_0_SCR                                                (0)
+#define CACC_D_CLIP_CFG_0_WORD_COUNT                                       (0x1)
+#define CACC_D_CLIP_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x1f))
+#define CACC_D_CLIP_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x1f))
+#define CACC_D_CLIP_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x1f))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT               (_MK_SHIFT_CONST(0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x1f, CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_RANGE                              (4:0)
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_WOFFSET                            (0x0)
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_DEFAULT_MASK      (_MK_MASK_CONST(0x1f))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_OUT_SATURATION_0
+#define CACC_D_OUT_SATURATION_0                         (_MK_ADDR_CONST(0x9030))
+#define CACC_D_OUT_SATURATION_0_SECURE                                     (0x0)
+#define CACC_D_OUT_SATURATION_0_DUAL                                       (0x0)
+#define CACC_D_OUT_SATURATION_0_SCR                                          (0)
+#define CACC_D_OUT_SATURATION_0_WORD_COUNT                                 (0x1)
+#define CACC_D_OUT_SATURATION_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_OUT_SATURATION_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_OUT_SATURATION_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT             (_MK_SHIFT_CONST(0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_RANGE                           (31:0)
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_WOFFSET                          (0x0)
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CACC_D_CYA_0
+#define CACC_D_CYA_0                                    (_MK_ADDR_CONST(0x9034))
+#define CACC_D_CYA_0_SECURE                                                (0x0)
+#define CACC_D_CYA_0_DUAL                                                  (0x0)
+#define CACC_D_CYA_0_SCR                                                     (0)
+#define CACC_D_CYA_0_WORD_COUNT                                            (0x1)
+#define CACC_D_CYA_0_RESET_VAL                             (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_RESET_MASK                     (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_CYA_0_SW_DEFAULT_VAL                        (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_SW_DEFAULT_MASK                       (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_READ_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_CYA_0_WRITE_MASK                     (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_CYA_0_CYA_SHIFT                              (_MK_SHIFT_CONST(0))
+#define CACC_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, CACC_D_CYA_0_CYA_SHIFT))
+#define CACC_D_CYA_0_CYA_RANGE                                            (31:0)
+#define CACC_D_CYA_0_CYA_WOFFSET                                           (0x0)
+#define CACC_D_CYA_0_CYA_DEFAULT                           (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_CYA_DEFAULT_MASK               (_MK_MASK_CONST(0xffffffff))
+#define CACC_D_CYA_0_CYA_SW_DEFAULT                        (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_CYA_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_CYA_PARITY_PROTECTION                 (_MK_MASK_CONST(0x0))
+#define CACC_D_CYA_0_CYA_PLATFORM_DEPENDENT                (_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_S_STATUS_0
+#define SDP_RDMA_S_STATUS_0                             (_MK_ADDR_CONST(0xa000))
+#define SDP_RDMA_S_STATUS_0_SECURE                                         (0x0)
+#define SDP_RDMA_S_STATUS_0_DUAL                                           (0x0)
+#define SDP_RDMA_S_STATUS_0_SCR                                              (0)
+#define SDP_RDMA_S_STATUS_0_WORD_COUNT                                     (0x1)
+#define SDP_RDMA_S_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_RESET_MASK                 (_MK_MASK_CONST(0x30003))
+#define SDP_RDMA_S_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_READ_MASK                  (_MK_MASK_CONST(0x30003))
+#define SDP_RDMA_S_STATUS_0_WRITE_MASK                     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                  (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_RANGE                                 (1:0)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_WOFFSET                               (0x0)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT               (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_INIT_ENUM                            (IDLE)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_IDLE                    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                 (_MK_ENUM_CONST(1))
+#define SDP_RDMA_S_STATUS_0_STATUS_0_PENDING                 (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                 (_MK_SHIFT_CONST(16))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_RANGE                               (17:16)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_WOFFSET                               (0x0)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT               (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_INIT_ENUM                            (IDLE)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_IDLE                    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                 (_MK_ENUM_CONST(1))
+#define SDP_RDMA_S_STATUS_0_STATUS_1_PENDING                 (_MK_ENUM_CONST(2))
+
+
+// Register SDP_RDMA_S_POINTER_0
+#define SDP_RDMA_S_POINTER_0                            (_MK_ADDR_CONST(0xa004))
+#define SDP_RDMA_S_POINTER_0_SECURE                                        (0x0)
+#define SDP_RDMA_S_POINTER_0_DUAL                                          (0x0)
+#define SDP_RDMA_S_POINTER_0_SCR                                             (0)
+#define SDP_RDMA_S_POINTER_0_WORD_COUNT                                    (0x1)
+#define SDP_RDMA_S_POINTER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
+#define SDP_RDMA_S_POINTER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
+#define SDP_RDMA_S_POINTER_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_RANGE                                (0:0)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_WOFFSET                              (0x0)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_INIT_ENUM                        (GROUP_0)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                (_MK_ENUM_CONST(0))
+#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                (_MK_SHIFT_CONST(16))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_RANGE                              (16:16)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_WOFFSET                              (0x0)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_INIT_ENUM                        (GROUP_0)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                (_MK_ENUM_CONST(0))
+#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_OP_ENABLE_0
+#define SDP_RDMA_D_OP_ENABLE_0                          (_MK_ADDR_CONST(0xa008))
+#define SDP_RDMA_D_OP_ENABLE_0_SECURE                                      (0x0)
+#define SDP_RDMA_D_OP_ENABLE_0_DUAL                                        (0x0)
+#define SDP_RDMA_D_OP_ENABLE_0_SCR                                           (0)
+#define SDP_RDMA_D_OP_ENABLE_0_WORD_COUNT                                  (0x1)
+#define SDP_RDMA_D_OP_ENABLE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                  (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_RANGE                                 (0:0)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                               (0x0)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT               (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                         (DISABLE)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                 (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                  (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_DATA_CUBE_WIDTH_0
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0                    (_MK_ADDR_CONST(0xa00c))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SECURE                                (0x0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SCR                                     (0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_RANGE                          (12:0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_WOFFSET                         (0x0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_DATA_CUBE_HEIGHT_0
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0                   (_MK_ADDR_CONST(0xa010))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SECURE                               (0x0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SCR                                    (0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_RANGE                        (12:0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_WOFFSET                       (0x0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_DATA_CUBE_CHANNEL_0
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0                  (_MK_ADDR_CONST(0xa014))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SECURE                              (0x0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_DUAL                                (0x0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SCR                                   (0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_MASK       (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_READ_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_WRITE_MASK       (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_RANGE                      (12:0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_WOFFSET                     (0x0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0                  (_MK_ADDR_CONST(0xa018))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SECURE                              (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_DUAL                                (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SCR                                   (0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE            (31:5)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET           (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                 (_MK_ADDR_CONST(0xa01c))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SECURE                             (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_DUAL                               (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SCR                                  (0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                         (0x1)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE          (31:0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET         (0x0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_LINE_STRIDE_0
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0                    (_MK_ADDR_CONST(0xa020))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SECURE                                (0x0)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SCR                                     (0)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                (31:5)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET               (0x0)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_SURFACE_STRIDE_0
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0                 (_MK_ADDR_CONST(0xa024))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SECURE                             (0x0)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_DUAL                               (0x0)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SCR                                  (0)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                         (0x1)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE          (31:5)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET         (0x0)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BRDMA_CFG_0
+#define SDP_RDMA_D_BRDMA_CFG_0                          (_MK_ADDR_CONST(0xa028))
+#define SDP_RDMA_D_BRDMA_CFG_0_SECURE                                      (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_DUAL                                        (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_SCR                                           (0)
+#define SDP_RDMA_D_BRDMA_CFG_0_WORD_COUNT                                  (0x1)
+#define SDP_RDMA_D_BRDMA_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_BRDMA_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_BRDMA_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_RANGE                         (0:0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_WOFFSET                       (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_NO              (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_YES             (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT         (_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_RANGE                        (2:1)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_MUL            (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_ALU            (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_BOTH           (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT        (_MK_SHIFT_CONST(3))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_RANGE                       (3:3)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_ONE_BYTE      (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_TWO_BYTE      (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT        (_MK_SHIFT_CONST(4))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_RANGE                       (4:4)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_KERNEL    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_ELEMENT \
+	(_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_RANGE                        (5:5)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_BS_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0                   (_MK_ADDR_CONST(0xa02c))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SECURE                               (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SCR                                    (0)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_RESET_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_READ_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_WRITE_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_RANGE              (31:5)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_WOFFSET             (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BS_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0                  (_MK_ADDR_CONST(0xa030))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SECURE                              (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_DUAL                                (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SCR                                   (0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_RANGE            (31:0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_WOFFSET           (0x0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BS_LINE_STRIDE_0
+#define SDP_RDMA_D_BS_LINE_STRIDE_0                     (_MK_ADDR_CONST(0xa034))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_SECURE                                 (0x0)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_DUAL                                   (0x0)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_SCR                                      (0)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_WORD_COUNT                             (0x1)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT    (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_RANGE                  (31:5)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_WOFFSET                 (0x0)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BS_SURFACE_STRIDE_0
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0                  (_MK_ADDR_CONST(0xa038))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SECURE                              (0x0)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_DUAL                                (0x0)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SCR                                   (0)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_RANGE            (31:5)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_WOFFSET           (0x0)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BS_BATCH_STRIDE_0
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0                    (_MK_ADDR_CONST(0xa03c))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SECURE                                (0x0)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SCR                                     (0)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_RANGE                (31:5)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_WOFFSET               (0x0)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_NRDMA_CFG_0
+#define SDP_RDMA_D_NRDMA_CFG_0                          (_MK_ADDR_CONST(0xa040))
+#define SDP_RDMA_D_NRDMA_CFG_0_SECURE                                      (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_DUAL                                        (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_SCR                                           (0)
+#define SDP_RDMA_D_NRDMA_CFG_0_WORD_COUNT                                  (0x1)
+#define SDP_RDMA_D_NRDMA_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_NRDMA_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_NRDMA_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_RANGE                         (0:0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_WOFFSET                       (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_NO              (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_YES             (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT         (_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_RANGE                        (2:1)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_MUL            (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_ALU            (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_BOTH           (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT        (_MK_SHIFT_CONST(3))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_RANGE                       (3:3)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_ONE_BYTE      (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_TWO_BYTE      (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT        (_MK_SHIFT_CONST(4))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_RANGE                       (4:4)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_KERNEL    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_ELEMENT \
+	(_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_RANGE                        (5:5)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_BN_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0                   (_MK_ADDR_CONST(0xa044))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SECURE                               (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SCR                                    (0)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_RESET_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_READ_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_WRITE_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_RANGE              (31:5)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_WOFFSET             (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BN_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0                  (_MK_ADDR_CONST(0xa048))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SECURE                              (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_DUAL                                (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SCR                                   (0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_RANGE            (31:0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_WOFFSET           (0x0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BN_LINE_STRIDE_0
+#define SDP_RDMA_D_BN_LINE_STRIDE_0                     (_MK_ADDR_CONST(0xa04c))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_SECURE                                 (0x0)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_DUAL                                   (0x0)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_SCR                                      (0)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_WORD_COUNT                             (0x1)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT    (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_RANGE                  (31:5)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_WOFFSET                 (0x0)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BN_SURFACE_STRIDE_0
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0                  (_MK_ADDR_CONST(0xa050))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SECURE                              (0x0)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_DUAL                                (0x0)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SCR                                   (0)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_RANGE            (31:5)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_WOFFSET           (0x0)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_BN_BATCH_STRIDE_0
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0                    (_MK_ADDR_CONST(0xa054))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SECURE                                (0x0)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SCR                                     (0)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_RANGE                (31:5)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_WOFFSET               (0x0)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_ERDMA_CFG_0
+#define SDP_RDMA_D_ERDMA_CFG_0                          (_MK_ADDR_CONST(0xa058))
+#define SDP_RDMA_D_ERDMA_CFG_0_SECURE                                      (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_DUAL                                        (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_SCR                                           (0)
+#define SDP_RDMA_D_ERDMA_CFG_0_WORD_COUNT                                  (0x1)
+#define SDP_RDMA_D_ERDMA_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_ERDMA_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_ERDMA_CFG_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_RANGE                         (0:0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_WOFFSET                       (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_NO              (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_YES             (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT         (_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_RANGE                        (2:1)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_MUL            (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_ALU            (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_BOTH           (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT        (_MK_SHIFT_CONST(3))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_RANGE                       (3:3)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_ONE_BYTE      (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_TWO_BYTE      (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT        (_MK_SHIFT_CONST(4))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_RANGE                       (4:4)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_WOFFSET                     (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_KERNEL    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_ELEMENT \
+	(_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_RANGE                        (5:5)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_EW_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0                   (_MK_ADDR_CONST(0xa05c))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SECURE                               (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SCR                                    (0)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_RESET_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_READ_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_WRITE_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_RANGE              (31:5)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_WOFFSET             (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_EW_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0                  (_MK_ADDR_CONST(0xa060))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SECURE                              (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_DUAL                                (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SCR                                   (0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_READ_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_RANGE            (31:0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_WOFFSET           (0x0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_EW_LINE_STRIDE_0
+#define SDP_RDMA_D_EW_LINE_STRIDE_0                     (_MK_ADDR_CONST(0xa064))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_SECURE                                 (0x0)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_DUAL                                   (0x0)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_SCR                                      (0)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_WORD_COUNT                             (0x1)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT    (_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_RANGE                  (31:5)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_WOFFSET                 (0x0)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_EW_SURFACE_STRIDE_0
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0                  (_MK_ADDR_CONST(0xa068))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SECURE                              (0x0)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_DUAL                                (0x0)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SCR                                   (0)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_WORD_COUNT                          (0x1)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_RANGE            (31:5)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_WOFFSET           (0x0)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_EW_BATCH_STRIDE_0
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0                    (_MK_ADDR_CONST(0xa06c))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SECURE                                (0x0)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_DUAL                                  (0x0)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SCR                                     (0)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_WORD_COUNT                            (0x1)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_RANGE                (31:5)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_WOFFSET               (0x0)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_FEATURE_MODE_CFG_0
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0                   (_MK_ADDR_CONST(0xa070))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SECURE                               (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_DUAL                                 (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SCR                                    (0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WORD_COUNT                           (0x1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_RESET_VAL           (_MK_MASK_CONST(0x14))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT     (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_RANGE                    (0:0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_WOFFSET                  (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF        (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON         (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT        (_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_RANGE                       (1:1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_WOFFSET                     (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF           (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_ON            (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT    (_MK_SHIFT_CONST(2))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_RANGE                   (3:2)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_WOFFSET                 (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT8      (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT16     (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FP16      (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT \
+	(_MK_SHIFT_CONST(4))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_RANGE                 (5:4)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_WOFFSET               (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_DEFAULT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT8    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT16 \
+	(_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FP16    (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT \
+	(_MK_SHIFT_CONST(6))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_RANGE                  (7:6)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_WOFFSET                (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT8     (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT16    (_MK_ENUM_CONST(1))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FP16     (_MK_ENUM_CONST(2))
+
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT    (_MK_SHIFT_CONST(8))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_RANGE                  (12:8)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_WOFFSET                 (0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_SRC_DMA_CFG_0
+#define SDP_RDMA_D_SRC_DMA_CFG_0                        (_MK_ADDR_CONST(0xa074))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SECURE                                    (0x0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_DUAL                                      (0x0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SCR                                         (0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_WORD_COUNT                                (0x1)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_RANGE                        (0:0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_WOFFSET                      (0x0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0               (_MK_ADDR_CONST(0xa078))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SECURE                           (0x0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_DUAL                             (0x0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SCR                                (0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_WORD_COUNT                       (0x1)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_WRITE_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_RANGE      (31:0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_WOFFSET     (0x0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_STATUS_INF_INPUT_NUM_0
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0               (_MK_ADDR_CONST(0xa07c))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SECURE                           (0x0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_DUAL                             (0x0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SCR                                (0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_WORD_COUNT                       (0x1)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_WRITE_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_RANGE      (31:0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_WOFFSET     (0x0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_PERF_ENABLE_0
+#define SDP_RDMA_D_PERF_ENABLE_0                        (_MK_ADDR_CONST(0xa080))
+#define SDP_RDMA_D_PERF_ENABLE_0_SECURE                                    (0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_DUAL                                      (0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_SCR                                         (0)
+#define SDP_RDMA_D_PERF_ENABLE_0_WORD_COUNT                                (0x1)
+#define SDP_RDMA_D_PERF_ENABLE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_RESET_MASK                (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_READ_MASK                 (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_PERF_ENABLE_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_RANGE                         (0:0)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_WOFFSET                       (0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_INIT_ENUM                      (NO)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_NO              (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_YES             (_MK_ENUM_CONST(1))
+
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT \
+	(_MK_SHIFT_CONST(1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_RANGE               (1:1)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_INIT_ENUM            (NO)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO    (_MK_ENUM_CONST(0))
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES \
+	(_MK_ENUM_CONST(1))
+
+
+// Register SDP_RDMA_D_PERF_MRDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa084))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SECURE                          (0x0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_DUAL                            (0x0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SCR                               (0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_WORD_COUNT                      (0x1)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_RANGE              (31:0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_PERF_BRDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa088))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SECURE                          (0x0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_DUAL                            (0x0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SCR                               (0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_WORD_COUNT                      (0x1)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_RANGE              (31:0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_PERF_NRDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa08c))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SECURE                          (0x0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_DUAL                            (0x0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SCR                               (0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_WORD_COUNT                      (0x1)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_RANGE              (31:0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_RDMA_D_PERF_ERDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0              (_MK_ADDR_CONST(0xa090))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SECURE                          (0x0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_DUAL                            (0x0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SCR                               (0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_WORD_COUNT                      (0x1)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_WRITE_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_RANGE              (31:0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_WOFFSET             (0x0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_STATUS_0
+#define SDP_S_STATUS_0                                  (_MK_ADDR_CONST(0xb000))
+#define SDP_S_STATUS_0_SECURE                                              (0x0)
+#define SDP_S_STATUS_0_DUAL                                                (0x0)
+#define SDP_S_STATUS_0_SCR                                                   (0)
+#define SDP_S_STATUS_0_WORD_COUNT                                          (0x1)
+#define SDP_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
+#define SDP_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
+#define SDP_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
+#define SDP_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_0_SHIFT))
+#define SDP_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
+#define SDP_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
+#define SDP_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define SDP_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define SDP_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
+#define SDP_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
+#define SDP_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
+#define SDP_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
+
+#define SDP_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
+#define SDP_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_1_SHIFT))
+#define SDP_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
+#define SDP_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
+#define SDP_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define SDP_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define SDP_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define SDP_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
+#define SDP_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
+#define SDP_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
+#define SDP_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
+
+
+// Register SDP_S_POINTER_0
+#define SDP_S_POINTER_0                                 (_MK_ADDR_CONST(0xb004))
+#define SDP_S_POINTER_0_SECURE                                             (0x0)
+#define SDP_S_POINTER_0_DUAL                                               (0x0)
+#define SDP_S_POINTER_0_SCR                                                  (0)
+#define SDP_S_POINTER_0_WORD_COUNT                                         (0x1)
+#define SDP_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
+#define SDP_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
+#define SDP_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
+#define SDP_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_POINTER_0_PRODUCER_SHIFT))
+#define SDP_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
+#define SDP_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
+#define SDP_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
+#define SDP_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define SDP_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+#define SDP_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
+#define SDP_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_POINTER_0_CONSUMER_SHIFT))
+#define SDP_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
+#define SDP_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
+#define SDP_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define SDP_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define SDP_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
+#define SDP_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define SDP_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+
+// Register SDP_S_LUT_ACCESS_CFG_0
+#define SDP_S_LUT_ACCESS_CFG_0                          (_MK_ADDR_CONST(0xb008))
+#define SDP_S_LUT_ACCESS_CFG_0_SECURE                                      (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_DUAL                                        (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_SCR                                           (0)
+#define SDP_S_LUT_ACCESS_CFG_0_WORD_COUNT                                  (0x1)
+#define SDP_S_LUT_ACCESS_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_RESET_MASK              (_MK_MASK_CONST(0x303ff))
+#define SDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_READ_MASK               (_MK_MASK_CONST(0x303ff))
+#define SDP_S_LUT_ACCESS_CFG_0_WRITE_MASK              (_MK_MASK_CONST(0x303ff))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT               (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD \
+	(_MK_FIELD_CONST(0x3ff, SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_RANGE                              (9:0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_WOFFSET                            (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT_MASK     (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT          (_MK_SHIFT_CONST(16))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_RANGE                        (16:16)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_WOFFSET                        (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_INIT_ENUM                       (LE)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE               (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO               (_MK_ENUM_CONST(1))
+
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT       (_MK_SHIFT_CONST(17))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_RANGE                     (17:17)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WOFFSET                     (0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_INIT_ENUM                  (READ)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ          (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE         (_MK_ENUM_CONST(1))
+
+
+// Register SDP_S_LUT_ACCESS_DATA_0
+#define SDP_S_LUT_ACCESS_DATA_0                         (_MK_ADDR_CONST(0xb00c))
+#define SDP_S_LUT_ACCESS_DATA_0_SECURE                                     (0x0)
+#define SDP_S_LUT_ACCESS_DATA_0_DUAL                                       (0x0)
+#define SDP_S_LUT_ACCESS_DATA_0_SCR                                          (0)
+#define SDP_S_LUT_ACCESS_DATA_0_WORD_COUNT                                 (0x1)
+#define SDP_S_LUT_ACCESS_DATA_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_RESET_MASK              (_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_READ_MASK               (_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_ACCESS_DATA_0_WRITE_MASK              (_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD \
+	(_MK_FIELD_CONST(0xffff, SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_RANGE                            (15:0)
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_WOFFSET                           (0x0)
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_CFG_0
+#define SDP_S_LUT_CFG_0                                 (_MK_ADDR_CONST(0xb010))
+#define SDP_S_LUT_CFG_0_SECURE                                             (0x0)
+#define SDP_S_LUT_CFG_0_DUAL                                               (0x0)
+#define SDP_S_LUT_CFG_0_SCR                                                  (0)
+#define SDP_S_LUT_CFG_0_WORD_COUNT                                         (0x1)
+#define SDP_S_LUT_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_RESET_MASK                        (_MK_MASK_CONST(0x71))
+#define SDP_S_LUT_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_READ_MASK                         (_MK_MASK_CONST(0x71))
+#define SDP_S_LUT_CFG_0_WRITE_MASK                        (_MK_MASK_CONST(0x71))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT               (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_RANGE                              (0:0)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_WOFFSET                            (0x0)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_INIT_ENUM                     (EXPONENT)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT             (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR               (_MK_ENUM_CONST(1))
+
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(4))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_RANGE                           (4:4)
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_WOFFSET                         (0x0)
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
+
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(5))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_RANGE                           (5:5)
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_WOFFSET                         (0x0)
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
+
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT           (_MK_SHIFT_CONST(6))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_RANGE                          (6:6)
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_WOFFSET                        (0x0)
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE               (_MK_ENUM_CONST(0))
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO               (_MK_ENUM_CONST(1))
+
+
+// Register SDP_S_LUT_INFO_0
+#define SDP_S_LUT_INFO_0                                (_MK_ADDR_CONST(0xb014))
+#define SDP_S_LUT_INFO_0_SECURE                                            (0x0)
+#define SDP_S_LUT_INFO_0_DUAL                                              (0x0)
+#define SDP_S_LUT_INFO_0_SCR                                                 (0)
+#define SDP_S_LUT_INFO_0_WORD_COUNT                                        (0x1)
+#define SDP_S_LUT_INFO_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_RESET_MASK                   (_MK_MASK_CONST(0xffffff))
+#define SDP_S_LUT_INFO_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_READ_MASK                    (_MK_MASK_CONST(0xffffff))
+#define SDP_S_LUT_INFO_0_WRITE_MASK                   (_MK_MASK_CONST(0xffffff))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_RANGE                         (7:0)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_WOFFSET                       (0x0)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT          (_MK_SHIFT_CONST(8))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD \
+	(_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_RANGE                        (15:8)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_WOFFSET                       (0x0)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT         (_MK_SHIFT_CONST(16))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD \
+	(_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_RANGE                       (23:16)
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_WOFFSET                       (0x0)
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LE_START_0
+#define SDP_S_LUT_LE_START_0                            (_MK_ADDR_CONST(0xb018))
+#define SDP_S_LUT_LE_START_0_SECURE                                        (0x0)
+#define SDP_S_LUT_LE_START_0_DUAL                                          (0x0)
+#define SDP_S_LUT_LE_START_0_SCR                                             (0)
+#define SDP_S_LUT_LE_START_0_WORD_COUNT                                    (0x1)
+#define SDP_S_LUT_LE_START_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_RESET_MASK             (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_START_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_READ_MASK              (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_START_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT             (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_RANGE                           (31:0)
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_WOFFSET                          (0x0)
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LE_END_0
+#define SDP_S_LUT_LE_END_0                              (_MK_ADDR_CONST(0xb01c))
+#define SDP_S_LUT_LE_END_0_SECURE                                          (0x0)
+#define SDP_S_LUT_LE_END_0_DUAL                                            (0x0)
+#define SDP_S_LUT_LE_END_0_SCR                                               (0)
+#define SDP_S_LUT_LE_END_0_WORD_COUNT                                      (0x1)
+#define SDP_S_LUT_LE_END_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_RESET_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_END_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_READ_MASK                (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_END_0_WRITE_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_RANGE                               (31:0)
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_WOFFSET                              (0x0)
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LO_START_0
+#define SDP_S_LUT_LO_START_0                            (_MK_ADDR_CONST(0xb020))
+#define SDP_S_LUT_LO_START_0_SECURE                                        (0x0)
+#define SDP_S_LUT_LO_START_0_DUAL                                          (0x0)
+#define SDP_S_LUT_LO_START_0_SCR                                             (0)
+#define SDP_S_LUT_LO_START_0_WORD_COUNT                                    (0x1)
+#define SDP_S_LUT_LO_START_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_RESET_MASK             (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_START_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_READ_MASK              (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_START_0_WRITE_MASK             (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT             (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_RANGE                           (31:0)
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_WOFFSET                          (0x0)
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LO_END_0
+#define SDP_S_LUT_LO_END_0                              (_MK_ADDR_CONST(0xb024))
+#define SDP_S_LUT_LO_END_0_SECURE                                          (0x0)
+#define SDP_S_LUT_LO_END_0_DUAL                                            (0x0)
+#define SDP_S_LUT_LO_END_0_SCR                                               (0)
+#define SDP_S_LUT_LO_END_0_WORD_COUNT                                      (0x1)
+#define SDP_S_LUT_LO_END_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_RESET_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_END_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_READ_MASK                (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_END_0_WRITE_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_RANGE                               (31:0)
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_WOFFSET                              (0x0)
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LE_SLOPE_SCALE_0
+#define SDP_S_LUT_LE_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xb028))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_SECURE                                  (0x0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_DUAL                                    (0x0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_SCR                                       (0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_RANGE         (15:0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_RANGE        (31:16)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LE_SLOPE_SHIFT_0
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xb02c))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SECURE                                  (0x0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_DUAL                                    (0x0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SCR                                       (0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LO_SLOPE_SCALE_0
+#define SDP_S_LUT_LO_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xb030))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_SECURE                                  (0x0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_DUAL                                    (0x0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_SCR                                       (0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_RANGE         (15:0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_RANGE        (31:16)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_S_LUT_LO_SLOPE_SHIFT_0
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xb034))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SECURE                                  (0x0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_DUAL                                    (0x0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SCR                                       (0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_OP_ENABLE_0
+#define SDP_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0xb038))
+#define SDP_D_OP_ENABLE_0_SECURE                                           (0x0)
+#define SDP_D_OP_ENABLE_0_DUAL                                             (0x0)
+#define SDP_D_OP_ENABLE_0_SCR                                                (0)
+#define SDP_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
+#define SDP_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define SDP_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define SDP_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
+#define SDP_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
+#define SDP_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define SDP_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define SDP_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
+#define SDP_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define SDP_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DATA_CUBE_WIDTH_0
+#define SDP_D_DATA_CUBE_WIDTH_0                         (_MK_ADDR_CONST(0xb03c))
+#define SDP_D_DATA_CUBE_WIDTH_0_SECURE                                     (0x0)
+#define SDP_D_DATA_CUBE_WIDTH_0_DUAL                                       (0x0)
+#define SDP_D_DATA_CUBE_WIDTH_0_SCR                                          (0)
+#define SDP_D_DATA_CUBE_WIDTH_0_WORD_COUNT                                 (0x1)
+#define SDP_D_DATA_CUBE_WIDTH_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_RESET_MASK              (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_READ_MASK               (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_WIDTH_0_WRITE_MASK              (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_RANGE                               (12:0)
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_WOFFSET                              (0x0)
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT_MASK      (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DATA_CUBE_HEIGHT_0
+#define SDP_D_DATA_CUBE_HEIGHT_0                        (_MK_ADDR_CONST(0xb040))
+#define SDP_D_DATA_CUBE_HEIGHT_0_SECURE                                    (0x0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_DUAL                                      (0x0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_SCR                                         (0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_WORD_COUNT                                (0x1)
+#define SDP_D_DATA_CUBE_HEIGHT_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_RESET_MASK             (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_READ_MASK              (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_HEIGHT_0_WRITE_MASK             (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT               (_MK_SHIFT_CONST(0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_RANGE                             (12:0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_WOFFSET                            (0x0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT_MASK    (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DATA_CUBE_CHANNEL_0
+#define SDP_D_DATA_CUBE_CHANNEL_0                       (_MK_ADDR_CONST(0xb044))
+#define SDP_D_DATA_CUBE_CHANNEL_0_SECURE                                   (0x0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_DUAL                                     (0x0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_SCR                                        (0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_WORD_COUNT                               (0x1)
+#define SDP_D_DATA_CUBE_CHANNEL_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_RESET_MASK            (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_READ_MASK             (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_CHANNEL_0_WRITE_MASK            (_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT             (_MK_SHIFT_CONST(0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_RANGE                           (12:0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_WOFFSET                          (0x0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_BASE_ADDR_LOW_0
+#define SDP_D_DST_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xb048))
+#define SDP_D_DST_BASE_ADDR_LOW_0_SECURE                                   (0x0)
+#define SDP_D_DST_BASE_ADDR_LOW_0_DUAL                                     (0x0)
+#define SDP_D_DST_BASE_ADDR_LOW_0_SCR                                        (0)
+#define SDP_D_DST_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
+#define SDP_D_DST_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_RANGE                 (31:5)
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_WOFFSET                (0x0)
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_BASE_ADDR_HIGH_0
+#define SDP_D_DST_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xb04c))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_SCR                                       (0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_RANGE               (31:0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_WOFFSET              (0x0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_LINE_STRIDE_0
+#define SDP_D_DST_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xb050))
+#define SDP_D_DST_LINE_STRIDE_0_SECURE                                     (0x0)
+#define SDP_D_DST_LINE_STRIDE_0_DUAL                                       (0x0)
+#define SDP_D_DST_LINE_STRIDE_0_SCR                                          (0)
+#define SDP_D_DST_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
+#define SDP_D_DST_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_RANGE                     (31:5)
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_WOFFSET                    (0x0)
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_SURFACE_STRIDE_0
+#define SDP_D_DST_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xb054))
+#define SDP_D_DST_SURFACE_STRIDE_0_SECURE                                  (0x0)
+#define SDP_D_DST_SURFACE_STRIDE_0_DUAL                                    (0x0)
+#define SDP_D_DST_SURFACE_STRIDE_0_SCR                                       (0)
+#define SDP_D_DST_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
+#define SDP_D_DST_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_RANGE               (31:5)
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_WOFFSET              (0x0)
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BS_CFG_0
+#define SDP_D_DP_BS_CFG_0                               (_MK_ADDR_CONST(0xb058))
+#define SDP_D_DP_BS_CFG_0_SECURE                                           (0x0)
+#define SDP_D_DP_BS_CFG_0_DUAL                                             (0x0)
+#define SDP_D_DP_BS_CFG_0_SCR                                                (0)
+#define SDP_D_DP_BS_CFG_0_WORD_COUNT                                       (0x1)
+#define SDP_D_DP_BS_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BS_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BS_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_RANGE                                  (0:0)
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_WOFFSET                                (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_NO                       (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_YES                      (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT               (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_RANGE                              (1:1)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT                 (_MK_SHIFT_CONST(2))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_RANGE                                (3:2)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_WOFFSET                              (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MAX                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MIN                    (_MK_ENUM_CONST(1))
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SUM                    (_MK_ENUM_CONST(2))
+
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT               (_MK_SHIFT_CONST(4))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_RANGE                              (4:4)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT                (_MK_SHIFT_CONST(5))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_RANGE                               (5:5)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_WOFFSET                             (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_NO                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_YES                   (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT              (_MK_SHIFT_CONST(6))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_RANGE                             (6:6)
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_WOFFSET                           (0x0)
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_NO                  (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_YES                 (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_BS_ALU_CFG_0
+#define SDP_D_DP_BS_ALU_CFG_0                           (_MK_ADDR_CONST(0xb05c))
+#define SDP_D_DP_BS_ALU_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_BS_ALU_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_BS_ALU_CFG_0_SCR                                            (0)
+#define SDP_D_DP_BS_ALU_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_BS_ALU_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BS_ALU_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BS_ALU_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_RANGE                             (0:0)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_RANGE                    (13:8)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_WOFFSET                   (0x0)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BS_ALU_SRC_VALUE_0
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb060))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_RANGE                  (15:0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BS_MUL_CFG_0
+#define SDP_D_DP_BS_MUL_CFG_0                           (_MK_ADDR_CONST(0xb064))
+#define SDP_D_DP_BS_MUL_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_BS_MUL_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_BS_MUL_CFG_0_SCR                                            (0)
+#define SDP_D_DP_BS_MUL_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_BS_MUL_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_RESET_MASK                (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BS_MUL_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_READ_MASK                 (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BS_MUL_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_RANGE                             (0:0)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_RANGE                    (15:8)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_WOFFSET                   (0x0)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BS_MUL_SRC_VALUE_0
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb068))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_RANGE                  (15:0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BN_CFG_0
+#define SDP_D_DP_BN_CFG_0                               (_MK_ADDR_CONST(0xb06c))
+#define SDP_D_DP_BN_CFG_0_SECURE                                           (0x0)
+#define SDP_D_DP_BN_CFG_0_DUAL                                             (0x0)
+#define SDP_D_DP_BN_CFG_0_SCR                                                (0)
+#define SDP_D_DP_BN_CFG_0_WORD_COUNT                                       (0x1)
+#define SDP_D_DP_BN_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BN_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BN_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_RANGE                                  (0:0)
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_WOFFSET                                (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_NO                       (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_YES                      (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT               (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_RANGE                              (1:1)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT                 (_MK_SHIFT_CONST(2))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_RANGE                                (3:2)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_WOFFSET                              (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MAX                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MIN                    (_MK_ENUM_CONST(1))
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SUM                    (_MK_ENUM_CONST(2))
+
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT               (_MK_SHIFT_CONST(4))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_RANGE                              (4:4)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT                (_MK_SHIFT_CONST(5))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_RANGE                               (5:5)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_WOFFSET                             (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_NO                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_YES                   (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT              (_MK_SHIFT_CONST(6))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_RANGE                             (6:6)
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_WOFFSET                           (0x0)
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_NO                  (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_YES                 (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_BN_ALU_CFG_0
+#define SDP_D_DP_BN_ALU_CFG_0                           (_MK_ADDR_CONST(0xb070))
+#define SDP_D_DP_BN_ALU_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_BN_ALU_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_BN_ALU_CFG_0_SCR                                            (0)
+#define SDP_D_DP_BN_ALU_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_BN_ALU_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BN_ALU_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BN_ALU_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x3f01))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_RANGE                             (0:0)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_RANGE                    (13:8)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_WOFFSET                   (0x0)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BN_ALU_SRC_VALUE_0
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb074))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_RANGE                  (15:0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BN_MUL_CFG_0
+#define SDP_D_DP_BN_MUL_CFG_0                           (_MK_ADDR_CONST(0xb078))
+#define SDP_D_DP_BN_MUL_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_BN_MUL_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_BN_MUL_CFG_0_SCR                                            (0)
+#define SDP_D_DP_BN_MUL_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_BN_MUL_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_RESET_MASK                (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BN_MUL_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_READ_MASK                 (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BN_MUL_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0xff01))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_RANGE                             (0:0)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT      (_MK_SHIFT_CONST(8))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_RANGE                    (15:8)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_WOFFSET                   (0x0)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_BN_MUL_SRC_VALUE_0
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb07c))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_READ_MASK           (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_RANGE                  (15:0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_CFG_0
+#define SDP_D_DP_EW_CFG_0                               (_MK_ADDR_CONST(0xb080))
+#define SDP_D_DP_EW_CFG_0_SECURE                                           (0x0)
+#define SDP_D_DP_EW_CFG_0_DUAL                                             (0x0)
+#define SDP_D_DP_EW_CFG_0_SCR                                                (0)
+#define SDP_D_DP_EW_CFG_0_WORD_COUNT                                       (0x1)
+#define SDP_D_DP_EW_CFG_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_EW_CFG_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_EW_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x7f))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_RANGE                                  (0:0)
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_WOFFSET                                (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_NO                       (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_YES                      (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT               (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_RANGE                              (1:1)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT                 (_MK_SHIFT_CONST(2))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_RANGE                                (3:2)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_WOFFSET                              (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MAX                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MIN                    (_MK_ENUM_CONST(1))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SUM                    (_MK_ENUM_CONST(2))
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_EQL                    (_MK_ENUM_CONST(3))
+
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT               (_MK_SHIFT_CONST(4))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_RANGE                              (4:4)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT                (_MK_SHIFT_CONST(5))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_RANGE                               (5:5)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_WOFFSET                             (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_NO                    (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_YES                   (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT               (_MK_SHIFT_CONST(6))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_RANGE                              (6:6)
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_WOFFSET                            (0x0)
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_YES                  (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_EW_ALU_CFG_0
+#define SDP_D_DP_EW_ALU_CFG_0                           (_MK_ADDR_CONST(0xb084))
+#define SDP_D_DP_EW_ALU_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_SCR                                            (0)
+#define SDP_D_DP_EW_ALU_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_EW_ALU_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_RESET_MASK                   (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_ALU_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_READ_MASK                    (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_ALU_CFG_0_WRITE_MASK                   (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_RANGE                             (0:0)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT       (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_RANGE                      (1:1)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_WOFFSET                    (0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_NO           (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_YES          (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_EW_ALU_SRC_VALUE_0
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb088))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_RANGE                  (31:0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0              (_MK_ADDR_CONST(0xb08c))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SECURE                          (0x0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_DUAL                            (0x0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SCR                               (0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_WORD_COUNT                      (0x1)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_RANGE        (31:0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_WOFFSET       (0x0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0               (_MK_ADDR_CONST(0xb090))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SECURE                           (0x0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_DUAL                             (0x0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SCR                                (0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_WORD_COUNT                       (0x1)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_RESET_MASK    (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_READ_MASK     (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_WRITE_MASK    (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_RANGE          (15:0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_WOFFSET         (0x0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0            (_MK_ADDR_CONST(0xb094))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SECURE                        (0x0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_DUAL                          (0x0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SCR                             (0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_WORD_COUNT                    (0x1)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_RESET_VAL     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_RESET_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_READ_MASK    (_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_RANGE     (5:0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_WOFFSET \
+	(0x0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_MUL_CFG_0
+#define SDP_D_DP_EW_MUL_CFG_0                           (_MK_ADDR_CONST(0xb098))
+#define SDP_D_DP_EW_MUL_CFG_0_SECURE                                       (0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_DUAL                                         (0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_SCR                                            (0)
+#define SDP_D_DP_EW_MUL_CFG_0_WORD_COUNT                                   (0x1)
+#define SDP_D_DP_EW_MUL_CFG_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_RESET_MASK                   (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_MUL_CFG_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_READ_MASK                    (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_MUL_CFG_0_WRITE_MASK                   (_MK_MASK_CONST(0x3))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_RANGE                             (0:0)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_WOFFSET                           (0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_REG                 (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_MEM                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT       (_MK_SHIFT_CONST(1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_RANGE                      (1:1)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_WOFFSET                    (0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_NO           (_MK_ENUM_CONST(0))
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_YES          (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DP_EW_MUL_SRC_VALUE_0
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0                     (_MK_ADDR_CONST(0xb09c))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SECURE                                 (0x0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_DUAL                                   (0x0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SCR                                      (0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_WORD_COUNT                             (0x1)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_RANGE                  (31:0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_WOFFSET                 (0x0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0              (_MK_ADDR_CONST(0xb0a0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SECURE                          (0x0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_DUAL                            (0x0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SCR                               (0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_WORD_COUNT                      (0x1)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_RESET_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_RANGE        (31:0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_WOFFSET       (0x0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0               (_MK_ADDR_CONST(0xb0a4))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SECURE                           (0x0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_DUAL                             (0x0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SCR                                (0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_WORD_COUNT                       (0x1)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_RESET_MASK    (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_READ_MASK     (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_WRITE_MASK    (_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_RANGE          (15:0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_WOFFSET         (0x0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0            (_MK_ADDR_CONST(0xb0a8))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SECURE                        (0x0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_DUAL                          (0x0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SCR                             (0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_WORD_COUNT                    (0x1)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_RESET_VAL     (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_RESET_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_READ_MASK    (_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_RANGE     (5:0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_WOFFSET \
+	(0x0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DP_EW_TRUNCATE_VALUE_0
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0                    (_MK_ADDR_CONST(0xb0ac))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SECURE                                (0x0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_DUAL                                  (0x0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SCR                                     (0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_WORD_COUNT                            (0x1)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_RESET_MASK          (_MK_MASK_CONST(0x3ff))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_READ_MASK           (_MK_MASK_CONST(0x3ff))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_WRITE_MASK          (_MK_MASK_CONST(0x3ff))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT      (_MK_SHIFT_CONST(0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_RANGE                     (9:0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_WOFFSET                   (0x0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_FEATURE_MODE_CFG_0
+#define SDP_D_FEATURE_MODE_CFG_0                        (_MK_ADDR_CONST(0xb0b0))
+#define SDP_D_FEATURE_MODE_CFG_0_SECURE                                    (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_DUAL                                      (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_SCR                                         (0)
+#define SDP_D_FEATURE_MODE_CFG_0_WORD_COUNT                                (0x1)
+#define SDP_D_FEATURE_MODE_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_RESET_MASK             (_MK_MASK_CONST(0x1f0f))
+#define SDP_D_FEATURE_MODE_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_READ_MASK              (_MK_MASK_CONST(0x1f0f))
+#define SDP_D_FEATURE_MODE_CFG_0_WRITE_MASK             (_MK_MASK_CONST(0x1f0f))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT          (_MK_SHIFT_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_RANGE                         (0:0)
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_WOFFSET                       (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF             (_MK_ENUM_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON              (_MK_ENUM_CONST(1))
+
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT           (_MK_SHIFT_CONST(1))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_RANGE                          (1:1)
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_WOFFSET                        (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_MEM              (_MK_ENUM_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PDP              (_MK_ENUM_CONST(1))
+
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT             (_MK_SHIFT_CONST(2))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_RANGE                            (2:2)
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_WOFFSET                          (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_DEFAULT_MASK     (_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF                (_MK_ENUM_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_ON                 (_MK_ENUM_CONST(1))
+
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT          (_MK_SHIFT_CONST(3))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_RANGE                         (3:3)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_WOFFSET                       (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_INIT_ENUM                 (DISABLE)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DISABLE         (_MK_ENUM_CONST(0))
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_ENABLE          (_MK_ENUM_CONST(1))
+
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT         (_MK_SHIFT_CONST(8))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD \
+	(_MK_FIELD_CONST(0x1f, SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_RANGE                       (12:8)
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_WOFFSET                      (0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DST_DMA_CFG_0
+#define SDP_D_DST_DMA_CFG_0                             (_MK_ADDR_CONST(0xb0b4))
+#define SDP_D_DST_DMA_CFG_0_SECURE                                         (0x0)
+#define SDP_D_DST_DMA_CFG_0_DUAL                                           (0x0)
+#define SDP_D_DST_DMA_CFG_0_SCR                                              (0)
+#define SDP_D_DST_DMA_CFG_0_WORD_COUNT                                     (0x1)
+#define SDP_D_DST_DMA_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_READ_MASK                      (_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_RANGE                             (0:0)
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_WOFFSET                           (0x0)
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV                  (_MK_ENUM_CONST(0))
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC                  (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_DST_BATCH_STRIDE_0
+#define SDP_D_DST_BATCH_STRIDE_0                        (_MK_ADDR_CONST(0xb0b8))
+#define SDP_D_DST_BATCH_STRIDE_0_SECURE                                    (0x0)
+#define SDP_D_DST_BATCH_STRIDE_0_DUAL                                      (0x0)
+#define SDP_D_DST_BATCH_STRIDE_0_SCR                                         (0)
+#define SDP_D_DST_BATCH_STRIDE_0_WORD_COUNT                                (0x1)
+#define SDP_D_DST_BATCH_STRIDE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BATCH_STRIDE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BATCH_STRIDE_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT     (_MK_SHIFT_CONST(5))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_RANGE                   (31:5)
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_WOFFSET                  (0x0)
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_DATA_FORMAT_0
+#define SDP_D_DATA_FORMAT_0                             (_MK_ADDR_CONST(0xb0bc))
+#define SDP_D_DATA_FORMAT_0_SECURE                                         (0x0)
+#define SDP_D_DATA_FORMAT_0_DUAL                                           (0x0)
+#define SDP_D_DATA_FORMAT_0_SCR                                              (0)
+#define SDP_D_DATA_FORMAT_0_WORD_COUNT                                     (0x1)
+#define SDP_D_DATA_FORMAT_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_RESET_MASK                     (_MK_MASK_CONST(0xf))
+#define SDP_D_DATA_FORMAT_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_READ_MASK                      (_MK_MASK_CONST(0xf))
+#define SDP_D_DATA_FORMAT_0_WRITE_MASK                     (_MK_MASK_CONST(0xf))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_RANGE                           (1:0)
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_WOFFSET                         (0x0)
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_DEFAULT_MASK    (_MK_MASK_CONST(0x3))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT8              (_MK_ENUM_CONST(0))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT16             (_MK_ENUM_CONST(1))
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FP16              (_MK_ENUM_CONST(2))
+
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT             (_MK_SHIFT_CONST(2))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_RANGE                            (3:2)
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_WOFFSET                          (0x0)
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_DEFAULT          (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_DEFAULT_MASK     (_MK_MASK_CONST(0x3))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT8               (_MK_ENUM_CONST(0))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT16              (_MK_ENUM_CONST(1))
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FP16               (_MK_ENUM_CONST(2))
+
+
+// Register SDP_D_CVT_OFFSET_0
+#define SDP_D_CVT_OFFSET_0                              (_MK_ADDR_CONST(0xb0c0))
+#define SDP_D_CVT_OFFSET_0_SECURE                                          (0x0)
+#define SDP_D_CVT_OFFSET_0_DUAL                                            (0x0)
+#define SDP_D_CVT_OFFSET_0_SCR                                               (0)
+#define SDP_D_CVT_OFFSET_0_WORD_COUNT                                      (0x1)
+#define SDP_D_CVT_OFFSET_0_RESET_VAL                       (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_RESET_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_CVT_OFFSET_0_SW_DEFAULT_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_SW_DEFAULT_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_READ_MASK                (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_CVT_OFFSET_0_WRITE_MASK               (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_RANGE                               (31:0)
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_WOFFSET                              (0x0)
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_CVT_SCALE_0
+#define SDP_D_CVT_SCALE_0                               (_MK_ADDR_CONST(0xb0c4))
+#define SDP_D_CVT_SCALE_0_SECURE                                           (0x0)
+#define SDP_D_CVT_SCALE_0_DUAL                                             (0x0)
+#define SDP_D_CVT_SCALE_0_SCR                                                (0)
+#define SDP_D_CVT_SCALE_0_WORD_COUNT                                       (0x1)
+#define SDP_D_CVT_SCALE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_RESET_MASK                    (_MK_MASK_CONST(0xffff))
+#define SDP_D_CVT_SCALE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_READ_MASK                     (_MK_MASK_CONST(0xffff))
+#define SDP_D_CVT_SCALE_0_WRITE_MASK                    (_MK_MASK_CONST(0xffff))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_RANGE                                 (15:0)
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_WOFFSET                                (0x0)
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_DEFAULT_MASK        (_MK_MASK_CONST(0xffff))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_CVT_SHIFT_0
+#define SDP_D_CVT_SHIFT_0                               (_MK_ADDR_CONST(0xb0c8))
+#define SDP_D_CVT_SHIFT_0_SECURE                                           (0x0)
+#define SDP_D_CVT_SHIFT_0_DUAL                                             (0x0)
+#define SDP_D_CVT_SHIFT_0_SCR                                                (0)
+#define SDP_D_CVT_SHIFT_0_WORD_COUNT                                       (0x1)
+#define SDP_D_CVT_SHIFT_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_RESET_MASK                      (_MK_MASK_CONST(0x3f))
+#define SDP_D_CVT_SHIFT_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_READ_MASK                       (_MK_MASK_CONST(0x3f))
+#define SDP_D_CVT_SHIFT_0_WRITE_MASK                      (_MK_MASK_CONST(0x3f))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT                   (_MK_SHIFT_CONST(0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x3f, SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_RANGE                                  (5:0)
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_WOFFSET                                (0x0)
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_DEFAULT                (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_DEFAULT_MASK          (_MK_MASK_CONST(0x3f))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_STATUS_0
+#define SDP_D_STATUS_0                                  (_MK_ADDR_CONST(0xb0cc))
+#define SDP_D_STATUS_0_SECURE                                              (0x0)
+#define SDP_D_STATUS_0_DUAL                                                (0x0)
+#define SDP_D_STATUS_0_SCR                                                   (0)
+#define SDP_D_STATUS_0_WORD_COUNT                                          (0x1)
+#define SDP_D_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_RESET_MASK                          (_MK_MASK_CONST(0x1))
+#define SDP_D_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_READ_MASK                           (_MK_MASK_CONST(0x1))
+#define SDP_D_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT                 (_MK_SHIFT_CONST(0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_RANGE                                (0:0)
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_WOFFSET                              (0x0)
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_DEFAULT              (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_STATUS_NAN_INPUT_NUM_0
+#define SDP_D_STATUS_NAN_INPUT_NUM_0                    (_MK_ADDR_CONST(0xb0d0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_SECURE                                (0x0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_DUAL                                  (0x0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_SCR                                     (0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_WORD_COUNT                            (0x1)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_RANGE           (31:0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_WOFFSET          (0x0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_STATUS_INF_INPUT_NUM_0
+#define SDP_D_STATUS_INF_INPUT_NUM_0                    (_MK_ADDR_CONST(0xb0d4))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_SECURE                                (0x0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_DUAL                                  (0x0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_SCR                                     (0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_WORD_COUNT                            (0x1)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_RANGE           (31:0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_WOFFSET          (0x0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_STATUS_NAN_OUTPUT_NUM_0
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0                   (_MK_ADDR_CONST(0xb0d8))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SECURE                               (0x0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_DUAL                                 (0x0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SCR                                    (0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_WORD_COUNT                           (0x1)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_RANGE         (31:0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_WOFFSET        (0x0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_ENABLE_0
+#define SDP_D_PERF_ENABLE_0                             (_MK_ADDR_CONST(0xb0dc))
+#define SDP_D_PERF_ENABLE_0_SECURE                                         (0x0)
+#define SDP_D_PERF_ENABLE_0_DUAL                                           (0x0)
+#define SDP_D_PERF_ENABLE_0_SCR                                              (0)
+#define SDP_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
+#define SDP_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0xf))
+#define SDP_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0xf))
+#define SDP_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0xf))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT               (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_RANGE                              (0:0)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_WOFFSET                            (0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_INIT_ENUM                           (NO)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT               (_MK_SHIFT_CONST(1))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_RANGE                              (1:1)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_WOFFSET                            (0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_INIT_ENUM                           (NO)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT               (_MK_SHIFT_CONST(2))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_RANGE                              (2:2)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_WOFFSET                            (0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_INIT_ENUM                           (NO)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_NO                   (_MK_ENUM_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_YES                  (_MK_ENUM_CONST(1))
+
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT     (_MK_SHIFT_CONST(3))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_RANGE                    (3:3)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_WOFFSET                  (0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_INIT_ENUM                 (NO)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO         (_MK_ENUM_CONST(0))
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES        (_MK_ENUM_CONST(1))
+
+
+// Register SDP_D_PERF_WDMA_WRITE_STALL_0
+#define SDP_D_PERF_WDMA_WRITE_STALL_0                   (_MK_ADDR_CONST(0xb0e0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_SECURE                               (0x0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_DUAL                                 (0x0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_SCR                                    (0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WORD_COUNT                           (0x1)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_RESET_MASK    (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_READ_MASK     (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WRITE_MASK           (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT      (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_RANGE                    (31:0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_WOFFSET                   (0x0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_UFLOW_0
+#define SDP_D_PERF_LUT_UFLOW_0                          (_MK_ADDR_CONST(0xb0e4))
+#define SDP_D_PERF_LUT_UFLOW_0_SECURE                                      (0x0)
+#define SDP_D_PERF_LUT_UFLOW_0_DUAL                                        (0x0)
+#define SDP_D_PERF_LUT_UFLOW_0_SCR                                           (0)
+#define SDP_D_PERF_LUT_UFLOW_0_WORD_COUNT                                  (0x1)
+#define SDP_D_PERF_LUT_UFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_UFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_RANGE                            (31:0)
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_WOFFSET                           (0x0)
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_OFLOW_0
+#define SDP_D_PERF_LUT_OFLOW_0                          (_MK_ADDR_CONST(0xb0e8))
+#define SDP_D_PERF_LUT_OFLOW_0_SECURE                                      (0x0)
+#define SDP_D_PERF_LUT_OFLOW_0_DUAL                                        (0x0)
+#define SDP_D_PERF_LUT_OFLOW_0_SCR                                           (0)
+#define SDP_D_PERF_LUT_OFLOW_0_WORD_COUNT                                  (0x1)
+#define SDP_D_PERF_LUT_OFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_OFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT              (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_RANGE                            (31:0)
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_WOFFSET                           (0x0)
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_OUT_SATURATION_0
+#define SDP_D_PERF_OUT_SATURATION_0                     (_MK_ADDR_CONST(0xb0ec))
+#define SDP_D_PERF_OUT_SATURATION_0_SECURE                                 (0x0)
+#define SDP_D_PERF_OUT_SATURATION_0_DUAL                                   (0x0)
+#define SDP_D_PERF_OUT_SATURATION_0_SCR                                      (0)
+#define SDP_D_PERF_OUT_SATURATION_0_WORD_COUNT                             (0x1)
+#define SDP_D_PERF_OUT_SATURATION_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_RESET_MASK      (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_OUT_SATURATION_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_READ_MASK       (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_OUT_SATURATION_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT    (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_RANGE                  (31:0)
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_WOFFSET                 (0x0)
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_HYBRID_0
+#define SDP_D_PERF_LUT_HYBRID_0                         (_MK_ADDR_CONST(0xb0f0))
+#define SDP_D_PERF_LUT_HYBRID_0_SECURE                                     (0x0)
+#define SDP_D_PERF_LUT_HYBRID_0_DUAL                                       (0x0)
+#define SDP_D_PERF_LUT_HYBRID_0_SCR                                          (0)
+#define SDP_D_PERF_LUT_HYBRID_0_WORD_COUNT                                 (0x1)
+#define SDP_D_PERF_LUT_HYBRID_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_HYBRID_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_RANGE                          (31:0)
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_WOFFSET                         (0x0)
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_LE_HIT_0
+#define SDP_D_PERF_LUT_LE_HIT_0                         (_MK_ADDR_CONST(0xb0f4))
+#define SDP_D_PERF_LUT_LE_HIT_0_SECURE                                     (0x0)
+#define SDP_D_PERF_LUT_LE_HIT_0_DUAL                                       (0x0)
+#define SDP_D_PERF_LUT_LE_HIT_0_SCR                                          (0)
+#define SDP_D_PERF_LUT_LE_HIT_0_WORD_COUNT                                 (0x1)
+#define SDP_D_PERF_LUT_LE_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LE_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_RANGE                          (31:0)
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_WOFFSET                         (0x0)
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register SDP_D_PERF_LUT_LO_HIT_0
+#define SDP_D_PERF_LUT_LO_HIT_0                         (_MK_ADDR_CONST(0xb0f8))
+#define SDP_D_PERF_LUT_LO_HIT_0_SECURE                                     (0x0)
+#define SDP_D_PERF_LUT_LO_HIT_0_DUAL                                       (0x0)
+#define SDP_D_PERF_LUT_LO_HIT_0_SCR                                          (0)
+#define SDP_D_PERF_LUT_LO_HIT_0_WORD_COUNT                                 (0x1)
+#define SDP_D_PERF_LUT_LO_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LO_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT            (_MK_SHIFT_CONST(0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_RANGE                          (31:0)
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_WOFFSET                         (0x0)
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_DEFAULT         (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_S_STATUS_0
+#define PDP_RDMA_S_STATUS_0                             (_MK_ADDR_CONST(0xc000))
+#define PDP_RDMA_S_STATUS_0_SECURE                                         (0x0)
+#define PDP_RDMA_S_STATUS_0_DUAL                                           (0x0)
+#define PDP_RDMA_S_STATUS_0_SCR                                              (0)
+#define PDP_RDMA_S_STATUS_0_WORD_COUNT                                     (0x1)
+#define PDP_RDMA_S_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_RESET_MASK                 (_MK_MASK_CONST(0x30003))
+#define PDP_RDMA_S_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_READ_MASK                  (_MK_MASK_CONST(0x30003))
+#define PDP_RDMA_S_STATUS_0_WRITE_MASK                     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                  (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_RANGE                                 (1:0)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_WOFFSET                               (0x0)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_INIT_ENUM                            (IDLE)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_IDLE                    (_MK_ENUM_CONST(0))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                 (_MK_ENUM_CONST(1))
+#define PDP_RDMA_S_STATUS_0_STATUS_0_PENDING                 (_MK_ENUM_CONST(2))
+
+#define PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                 (_MK_SHIFT_CONST(16))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_RANGE                               (17:16)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_WOFFSET                               (0x0)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_INIT_ENUM                            (IDLE)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_IDLE                    (_MK_ENUM_CONST(0))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                 (_MK_ENUM_CONST(1))
+#define PDP_RDMA_S_STATUS_0_STATUS_1_PENDING                 (_MK_ENUM_CONST(2))
+
+
+// Register PDP_RDMA_S_POINTER_0
+#define PDP_RDMA_S_POINTER_0                            (_MK_ADDR_CONST(0xc004))
+#define PDP_RDMA_S_POINTER_0_SECURE                                        (0x0)
+#define PDP_RDMA_S_POINTER_0_DUAL                                          (0x0)
+#define PDP_RDMA_S_POINTER_0_SCR                                             (0)
+#define PDP_RDMA_S_POINTER_0_WORD_COUNT                                    (0x1)
+#define PDP_RDMA_S_POINTER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
+#define PDP_RDMA_S_POINTER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
+#define PDP_RDMA_S_POINTER_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_RANGE                                (0:0)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_WOFFSET                              (0x0)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_INIT_ENUM                        (GROUP_0)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                (_MK_ENUM_CONST(0))
+#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                (_MK_ENUM_CONST(1))
+
+#define PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                (_MK_SHIFT_CONST(16))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_RANGE                              (16:16)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_WOFFSET                              (0x0)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_INIT_ENUM                        (GROUP_0)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                (_MK_ENUM_CONST(0))
+#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_OP_ENABLE_0
+#define PDP_RDMA_D_OP_ENABLE_0                          (_MK_ADDR_CONST(0xc008))
+#define PDP_RDMA_D_OP_ENABLE_0_SECURE                                      (0x0)
+#define PDP_RDMA_D_OP_ENABLE_0_DUAL                                        (0x0)
+#define PDP_RDMA_D_OP_ENABLE_0_SCR                                           (0)
+#define PDP_RDMA_D_OP_ENABLE_0_WORD_COUNT                                  (0x1)
+#define PDP_RDMA_D_OP_ENABLE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                  (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_RANGE                                 (0:0)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                               (0x0)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                         (DISABLE)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                 (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                  (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0                 (_MK_ADDR_CONST(0xc00c))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SECURE                             (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_DUAL                               (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SCR                                  (0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_RESET_MASK      (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_READ_MASK       (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_WRITE_MASK      (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_RANGE               (12:0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_WOFFSET              (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0                (_MK_ADDR_CONST(0xc010))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SECURE                            (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_DUAL                              (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SCR                                 (0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_WORD_COUNT                        (0x1)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_RESET_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_RESET_MASK     (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_VAL    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_READ_MASK      (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_WRITE_MASK     (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_RANGE             (12:0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_WOFFSET            (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0               (_MK_ADDR_CONST(0xc014))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SECURE                           (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_DUAL                             (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SCR                                (0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_WORD_COUNT                       (0x1)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_RESET_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_RESET_MASK    (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_READ_MASK     (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_WRITE_MASK    (_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_RANGE           (12:0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_WOFFSET          (0x0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_FLYING_MODE_0
+#define PDP_RDMA_D_FLYING_MODE_0                        (_MK_ADDR_CONST(0xc018))
+#define PDP_RDMA_D_FLYING_MODE_0_SECURE                                    (0x0)
+#define PDP_RDMA_D_FLYING_MODE_0_DUAL                                      (0x0)
+#define PDP_RDMA_D_FLYING_MODE_0_SCR                                         (0)
+#define PDP_RDMA_D_FLYING_MODE_0_WORD_COUNT                                (0x1)
+#define PDP_RDMA_D_FLYING_MODE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT          (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_RANGE                         (0:0)
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_WOFFSET                       (0x0)
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_DEFAULT       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_ON_FLYING       (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_OFF_FLYING      (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_SRC_BASE_ADDR_LOW_0
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0                  (_MK_ADDR_CONST(0xc01c))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SECURE                              (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_DUAL                                (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SCR                                   (0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                          (0x1)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE            (31:5)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET           (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                 (_MK_ADDR_CONST(0xc020))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SECURE                             (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_DUAL                               (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SCR                                  (0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE          (31:0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET         (0x0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_SRC_LINE_STRIDE_0
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0                    (_MK_ADDR_CONST(0xc024))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SECURE                                (0x0)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_DUAL                                  (0x0)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SCR                                     (0)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_WORD_COUNT                            (0x1)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                (31:5)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET               (0x0)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_SRC_SURFACE_STRIDE_0
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0                 (_MK_ADDR_CONST(0xc028))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SECURE                             (0x0)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_DUAL                               (0x0)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SCR                                  (0)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE          (31:5)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET         (0x0)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_SRC_RAM_CFG_0
+#define PDP_RDMA_D_SRC_RAM_CFG_0                        (_MK_ADDR_CONST(0xc02c))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SECURE                                    (0x0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_DUAL                                      (0x0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SCR                                         (0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_WORD_COUNT                                (0x1)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_RANGE                        (0:0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_WOFFSET                      (0x0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_DATA_FORMAT_0
+#define PDP_RDMA_D_DATA_FORMAT_0                        (_MK_ADDR_CONST(0xc030))
+#define PDP_RDMA_D_DATA_FORMAT_0_SECURE                                    (0x0)
+#define PDP_RDMA_D_DATA_FORMAT_0_DUAL                                      (0x0)
+#define PDP_RDMA_D_DATA_FORMAT_0_SCR                                         (0)
+#define PDP_RDMA_D_DATA_FORMAT_0_WORD_COUNT                                (0x1)
+#define PDP_RDMA_D_DATA_FORMAT_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_RESET_MASK                (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_READ_MASK                 (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_D_DATA_FORMAT_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT           (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_RANGE                          (1:0)
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_WOFFSET                        (0x0)
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8             (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16            (_MK_ENUM_CONST(1))
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16             (_MK_ENUM_CONST(2))
+
+
+// Register PDP_RDMA_D_OPERATION_MODE_CFG_0
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0                 (_MK_ADDR_CONST(0xc034))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SECURE                             (0x0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_DUAL                               (0x0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SCR                                  (0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_RESET_MASK        (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_READ_MASK         (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT     (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xff, \
+	PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_RANGE                    (7:0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_WOFFSET                  (0x0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_POOLING_KERNEL_CFG_0
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0                 (_MK_ADDR_CONST(0xc038))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SECURE                             (0x0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_DUAL                               (0x0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SCR                                  (0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_WORD_COUNT                         (0x1)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_RESET_MASK        (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_READ_MASK         (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0xff))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_RANGE                 (3:0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_WOFFSET               (0x0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 \
+	(_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 \
+	(_MK_ENUM_CONST(1))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 \
+	(_MK_ENUM_CONST(2))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 \
+	(_MK_ENUM_CONST(3))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 \
+	(_MK_ENUM_CONST(4))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 \
+	(_MK_ENUM_CONST(5))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 \
+	(_MK_ENUM_CONST(6))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 \
+	(_MK_ENUM_CONST(7))
+
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(4))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_RANGE          (7:4)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_WOFFSET        (0x0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_POOLING_PADDING_CFG_0
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0                (_MK_ADDR_CONST(0xc03c))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SECURE                            (0x0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_DUAL                              (0x0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SCR                                 (0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_WORD_COUNT                        (0x1)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_RESET_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_RESET_MASK        (_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SW_DEFAULT_VAL    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_READ_MASK         (_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_WRITE_MASK        (_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT    (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_RANGE                   (3:0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_WOFFSET                 (0x0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_PARTIAL_WIDTH_IN_0
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0                   (_MK_ADDR_CONST(0xc040))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SECURE                               (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_DUAL                                 (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SCR                                    (0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_WORD_COUNT                           (0x1)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_RESET_MASK    (_MK_MASK_CONST(0x3fffffff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_READ_MASK     (_MK_MASK_CONST(0x3fffffff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_WRITE_MASK    (_MK_MASK_CONST(0x3fffffff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_RANGE         (9:0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_WOFFSET       (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT \
+	(_MK_SHIFT_CONST(10))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_RANGE        (19:10)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_WOFFSET        (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_RANGE         (29:20)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_WOFFSET         (0x0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_PERF_ENABLE_0
+#define PDP_RDMA_D_PERF_ENABLE_0                        (_MK_ADDR_CONST(0xc044))
+#define PDP_RDMA_D_PERF_ENABLE_0_SECURE                                    (0x0)
+#define PDP_RDMA_D_PERF_ENABLE_0_DUAL                                      (0x0)
+#define PDP_RDMA_D_PERF_ENABLE_0_SCR                                         (0)
+#define PDP_RDMA_D_PERF_ENABLE_0_WORD_COUNT                                (0x1)
+#define PDP_RDMA_D_PERF_ENABLE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT               (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_RANGE                              (0:0)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_WOFFSET                            (0x0)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                      (DISABLE)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE              (_MK_ENUM_CONST(0))
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE               (_MK_ENUM_CONST(1))
+
+
+// Register PDP_RDMA_D_PERF_READ_STALL_0
+#define PDP_RDMA_D_PERF_READ_STALL_0                    (_MK_ADDR_CONST(0xc048))
+#define PDP_RDMA_D_PERF_READ_STALL_0_SECURE                                (0x0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_DUAL                                  (0x0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_SCR                                     (0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_WORD_COUNT                            (0x1)
+#define PDP_RDMA_D_PERF_READ_STALL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_PERF_READ_STALL_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_RANGE                (31:0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_WOFFSET               (0x0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_RDMA_D_CYA_0
+#define PDP_RDMA_D_CYA_0                                (_MK_ADDR_CONST(0xc04c))
+#define PDP_RDMA_D_CYA_0_SECURE                                            (0x0)
+#define PDP_RDMA_D_CYA_0_DUAL                                              (0x0)
+#define PDP_RDMA_D_CYA_0_SCR                                                 (0)
+#define PDP_RDMA_D_CYA_0_WORD_COUNT                                        (0x1)
+#define PDP_RDMA_D_CYA_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_RESET_MASK                 (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_CYA_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_READ_MASK                  (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_CYA_0_WRITE_MASK                 (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_CYA_0_CYA_SHIFT                          (_MK_SHIFT_CONST(0))
+#define PDP_RDMA_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_CYA_0_CYA_SHIFT))
+#define PDP_RDMA_D_CYA_0_CYA_RANGE                                        (31:0)
+#define PDP_RDMA_D_CYA_0_CYA_WOFFSET                                       (0x0)
+#define PDP_RDMA_D_CYA_0_CYA_DEFAULT                       (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_CYA_DEFAULT_MASK           (_MK_MASK_CONST(0xffffffff))
+#define PDP_RDMA_D_CYA_0_CYA_SW_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_CYA_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_CYA_PARITY_PROTECTION             (_MK_MASK_CONST(0x0))
+#define PDP_RDMA_D_CYA_0_CYA_PLATFORM_DEPENDENT            (_MK_MASK_CONST(0x1))
+
+
+// Register PDP_S_STATUS_0
+#define PDP_S_STATUS_0                                  (_MK_ADDR_CONST(0xd000))
+#define PDP_S_STATUS_0_SECURE                                              (0x0)
+#define PDP_S_STATUS_0_DUAL                                                (0x0)
+#define PDP_S_STATUS_0_SCR                                                   (0)
+#define PDP_S_STATUS_0_WORD_COUNT                                          (0x1)
+#define PDP_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
+#define PDP_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
+#define PDP_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
+#define PDP_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_0_SHIFT))
+#define PDP_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
+#define PDP_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
+#define PDP_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define PDP_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define PDP_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
+#define PDP_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
+#define PDP_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
+#define PDP_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
+
+#define PDP_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
+#define PDP_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_1_SHIFT))
+#define PDP_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
+#define PDP_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
+#define PDP_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define PDP_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define PDP_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define PDP_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
+#define PDP_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
+#define PDP_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
+#define PDP_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
+
+
+// Register PDP_S_POINTER_0
+#define PDP_S_POINTER_0                                 (_MK_ADDR_CONST(0xd004))
+#define PDP_S_POINTER_0_SECURE                                             (0x0)
+#define PDP_S_POINTER_0_DUAL                                               (0x0)
+#define PDP_S_POINTER_0_SCR                                                  (0)
+#define PDP_S_POINTER_0_WORD_COUNT                                         (0x1)
+#define PDP_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
+#define PDP_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
+#define PDP_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
+#define PDP_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_S_POINTER_0_PRODUCER_SHIFT))
+#define PDP_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
+#define PDP_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
+#define PDP_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
+#define PDP_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define PDP_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+#define PDP_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
+#define PDP_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_S_POINTER_0_CONSUMER_SHIFT))
+#define PDP_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
+#define PDP_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
+#define PDP_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define PDP_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define PDP_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
+#define PDP_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define PDP_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_OP_ENABLE_0
+#define PDP_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0xd008))
+#define PDP_D_OP_ENABLE_0_SECURE                                           (0x0)
+#define PDP_D_OP_ENABLE_0_DUAL                                             (0x0)
+#define PDP_D_OP_ENABLE_0_SCR                                                (0)
+#define PDP_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
+#define PDP_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define PDP_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define PDP_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
+#define PDP_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
+#define PDP_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define PDP_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define PDP_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
+#define PDP_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define PDP_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_DATA_CUBE_IN_WIDTH_0
+#define PDP_D_DATA_CUBE_IN_WIDTH_0                      (_MK_ADDR_CONST(0xd00c))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_SECURE                                  (0x0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_DUAL                                    (0x0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_SCR                                       (0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_WORD_COUNT                              (0x1)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_RESET_MASK           (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_READ_MASK            (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_WRITE_MASK           (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT      (_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_RANGE                    (12:0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_WOFFSET                   (0x0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_IN_HEIGHT_0
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0                     (_MK_ADDR_CONST(0xd010))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SECURE                                 (0x0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_DUAL                                   (0x0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SCR                                      (0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_WORD_COUNT                             (0x1)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_RESET_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_READ_MASK           (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_WRITE_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT    (_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_RANGE                  (12:0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_WOFFSET                 (0x0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_IN_CHANNEL_0
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0                    (_MK_ADDR_CONST(0xd014))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SECURE                                (0x0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_DUAL                                  (0x0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SCR                                     (0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_WORD_COUNT                            (0x1)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_RANGE                (12:0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_WOFFSET               (0x0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_OUT_WIDTH_0
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0                     (_MK_ADDR_CONST(0xd018))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SECURE                                 (0x0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_DUAL                                   (0x0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SCR                                      (0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_WORD_COUNT                             (0x1)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_RESET_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_READ_MASK           (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_WRITE_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT    (_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_RANGE                  (12:0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_WOFFSET                 (0x0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_OUT_HEIGHT_0
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0                    (_MK_ADDR_CONST(0xd01c))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SECURE                                (0x0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_DUAL                                  (0x0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SCR                                     (0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_WORD_COUNT                            (0x1)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_RANGE                (12:0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_WOFFSET               (0x0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DATA_CUBE_OUT_CHANNEL_0
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0                   (_MK_ADDR_CONST(0xd020))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SECURE                               (0x0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_DUAL                                 (0x0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SCR                                    (0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_WORD_COUNT                           (0x1)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_RANGE              (12:0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_WOFFSET             (0x0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_OPERATION_MODE_CFG_0
+#define PDP_D_OPERATION_MODE_CFG_0                      (_MK_ADDR_CONST(0xd024))
+#define PDP_D_OPERATION_MODE_CFG_0_SECURE                                  (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_DUAL                                    (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_SCR                                       (0)
+#define PDP_D_OPERATION_MODE_CFG_0_WORD_COUNT                              (0x1)
+#define PDP_D_OPERATION_MODE_CFG_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_RESET_MASK           (_MK_MASK_CONST(0xff13))
+#define PDP_D_OPERATION_MODE_CFG_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_READ_MASK            (_MK_MASK_CONST(0xff13))
+#define PDP_D_OPERATION_MODE_CFG_0_WRITE_MASK           (_MK_MASK_CONST(0xff13))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT     (_MK_SHIFT_CONST(0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_RANGE                    (1:0)
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_WOFFSET                  (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE \
+	(_MK_ENUM_CONST(0))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX \
+	(_MK_ENUM_CONST(1))
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN \
+	(_MK_ENUM_CONST(2))
+
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT        (_MK_SHIFT_CONST(4))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_RANGE                       (4:4)
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_WOFFSET                     (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING     (_MK_ENUM_CONST(0))
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING    (_MK_ENUM_CONST(1))
+
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT          (_MK_SHIFT_CONST(8))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xff, PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_RANGE                        (15:8)
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_WOFFSET                       (0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT       (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_NAN_FLUSH_TO_ZERO_0
+#define PDP_D_NAN_FLUSH_TO_ZERO_0                       (_MK_ADDR_CONST(0xd028))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_SECURE                                   (0x0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_DUAL                                     (0x0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_SCR                                        (0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_WORD_COUNT                               (0x1)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_RESET_MASK               (_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_READ_MASK                (_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_WRITE_MASK               (_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT         (_MK_SHIFT_CONST(0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_RANGE                        (0:0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_WOFFSET                      (0x0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT      (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_INIT_ENUM                (DISABLE)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE        (_MK_ENUM_CONST(0))
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE         (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_PARTIAL_WIDTH_IN_0
+#define PDP_D_PARTIAL_WIDTH_IN_0                        (_MK_ADDR_CONST(0xd02c))
+#define PDP_D_PARTIAL_WIDTH_IN_0_SECURE                                    (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_DUAL                                      (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_SCR                                         (0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_WORD_COUNT                                (0x1)
+#define PDP_D_PARTIAL_WIDTH_IN_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_RESET_MASK         (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_READ_MASK          (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_WRITE_MASK         (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_RANGE              (9:0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_WOFFSET            (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT \
+	(_MK_SHIFT_CONST(10))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_RANGE             (19:10)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_WOFFSET             (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_RANGE              (29:20)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_WOFFSET              (0x0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_PARTIAL_WIDTH_OUT_0
+#define PDP_D_PARTIAL_WIDTH_OUT_0                       (_MK_ADDR_CONST(0xd030))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_SECURE                                   (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_DUAL                                     (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_SCR                                        (0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_WORD_COUNT                               (0x1)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_RESET_MASK        (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_READ_MASK         (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_WRITE_MASK        (_MK_MASK_CONST(0x3fffffff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_RANGE            (9:0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_WOFFSET          (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT \
+	(_MK_SHIFT_CONST(10))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_RANGE           (19:10)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_WOFFSET           (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_FIELD \
+	(_MK_FIELD_CONST(0x3ff, \
+	PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_RANGE            (29:20)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_WOFFSET            (0x0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3ff))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_KERNEL_CFG_0
+#define PDP_D_POOLING_KERNEL_CFG_0                      (_MK_ADDR_CONST(0xd034))
+#define PDP_D_POOLING_KERNEL_CFG_0_SECURE                                  (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_DUAL                                    (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_SCR                                       (0)
+#define PDP_D_POOLING_KERNEL_CFG_0_WORD_COUNT                              (0x1)
+#define PDP_D_POOLING_KERNEL_CFG_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_RESET_MASK         (_MK_MASK_CONST(0xff0f0f))
+#define PDP_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_READ_MASK          (_MK_MASK_CONST(0xff0f0f))
+#define PDP_D_POOLING_KERNEL_CFG_0_WRITE_MASK         (_MK_MASK_CONST(0xff0f0f))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT       (_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_RANGE                      (3:0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_WOFFSET                    (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 \
+	(_MK_ENUM_CONST(0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 \
+	(_MK_ENUM_CONST(1))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 \
+	(_MK_ENUM_CONST(2))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 \
+	(_MK_ENUM_CONST(3))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 \
+	(_MK_ENUM_CONST(4))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 \
+	(_MK_ENUM_CONST(5))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 \
+	(_MK_ENUM_CONST(6))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 \
+	(_MK_ENUM_CONST(7))
+
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT      (_MK_SHIFT_CONST(8))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_RANGE                    (11:8)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_WOFFSET                   (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_1 \
+	(_MK_ENUM_CONST(0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_2 \
+	(_MK_ENUM_CONST(1))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_3 \
+	(_MK_ENUM_CONST(2))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_4 \
+	(_MK_ENUM_CONST(3))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_5 \
+	(_MK_ENUM_CONST(4))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_6 \
+	(_MK_ENUM_CONST(5))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_7 \
+	(_MK_ENUM_CONST(6))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_8 \
+	(_MK_ENUM_CONST(7))
+
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_RANGE             (19:16)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_WOFFSET             (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT \
+	(_MK_SHIFT_CONST(20))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0xf, \
+	PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_RANGE            (23:20)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_WOFFSET            (0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xf))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_RECIP_KERNEL_WIDTH_0
+#define PDP_D_RECIP_KERNEL_WIDTH_0                      (_MK_ADDR_CONST(0xd038))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_SECURE                                  (0x0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_DUAL                                    (0x0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_SCR                                       (0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_WORD_COUNT                              (0x1)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RESET_MASK          (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_READ_MASK           (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_WRITE_MASK          (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1ffff, \
+	PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_RANGE               (16:0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_WOFFSET              (0x0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_RECIP_KERNEL_HEIGHT_0
+#define PDP_D_RECIP_KERNEL_HEIGHT_0                     (_MK_ADDR_CONST(0xd03c))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_SECURE                                 (0x0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_DUAL                                   (0x0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_SCR                                      (0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_WORD_COUNT                             (0x1)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RESET_MASK         (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_READ_MASK          (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_WRITE_MASK         (_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1ffff, \
+	PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_RANGE             (16:0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_WOFFSET            (0x0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1ffff))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_CFG_0
+#define PDP_D_POOLING_PADDING_CFG_0                     (_MK_ADDR_CONST(0xd040))
+#define PDP_D_POOLING_PADDING_CFG_0_SECURE                                 (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_DUAL                                   (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_SCR                                      (0)
+#define PDP_D_POOLING_PADDING_CFG_0_WORD_COUNT                             (0x1)
+#define PDP_D_POOLING_PADDING_CFG_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_RESET_MASK          (_MK_MASK_CONST(0x7777))
+#define PDP_D_POOLING_PADDING_CFG_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_READ_MASK           (_MK_MASK_CONST(0x7777))
+#define PDP_D_POOLING_PADDING_CFG_0_WRITE_MASK          (_MK_MASK_CONST(0x7777))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT          (_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_FIELD \
+	(_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_RANGE                         (2:0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_WOFFSET                       (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT           (_MK_SHIFT_CONST(4))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_FIELD \
+	(_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_RANGE                          (6:4)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_WOFFSET                        (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT         (_MK_SHIFT_CONST(8))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_FIELD \
+	(_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_RANGE                       (10:8)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_WOFFSET                      (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_DEFAULT      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT       (_MK_SHIFT_CONST(12))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_FIELD \
+	(_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_RANGE                     (14:12)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_WOFFSET                     (0x0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_1_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0             (_MK_ADDR_CONST(0xd044))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_2_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0             (_MK_ADDR_CONST(0xd048))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_3_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0             (_MK_ADDR_CONST(0xd04c))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_4_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0             (_MK_ADDR_CONST(0xd050))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_5_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0             (_MK_ADDR_CONST(0xd054))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_6_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0             (_MK_ADDR_CONST(0xd058))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_7_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0             (_MK_ADDR_CONST(0xd05c))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SECURE                         (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_DUAL                           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SCR                              (0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_WORD_COUNT                     (0x1)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_RESET_VAL      (_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_RESET_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SW_DEFAULT_VAL \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_READ_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_WRITE_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_FIELD \
+	(_MK_FIELD_CONST(0x7ffff, \
+	PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_RANGE            (18:0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_WOFFSET           (0x0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffff))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_SRC_BASE_ADDR_LOW_0
+#define PDP_D_SRC_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xd060))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SECURE                                   (0x0)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_DUAL                                     (0x0)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SCR                                        (0)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE                 (31:5)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET                (0x0)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_SRC_BASE_ADDR_HIGH_0
+#define PDP_D_SRC_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xd064))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SCR                                       (0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE               (31:0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET              (0x0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_SRC_LINE_STRIDE_0
+#define PDP_D_SRC_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xd068))
+#define PDP_D_SRC_LINE_STRIDE_0_SECURE                                     (0x0)
+#define PDP_D_SRC_LINE_STRIDE_0_DUAL                                       (0x0)
+#define PDP_D_SRC_LINE_STRIDE_0_SCR                                          (0)
+#define PDP_D_SRC_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
+#define PDP_D_SRC_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                     (31:5)
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET                    (0x0)
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_SRC_SURFACE_STRIDE_0
+#define PDP_D_SRC_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xd06c))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SECURE                                  (0x0)
+#define PDP_D_SRC_SURFACE_STRIDE_0_DUAL                                    (0x0)
+#define PDP_D_SRC_SURFACE_STRIDE_0_SCR                                       (0)
+#define PDP_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
+#define PDP_D_SRC_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE               (31:5)
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET              (0x0)
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_BASE_ADDR_LOW_0
+#define PDP_D_DST_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xd070))
+#define PDP_D_DST_BASE_ADDR_LOW_0_SECURE                                   (0x0)
+#define PDP_D_DST_BASE_ADDR_LOW_0_DUAL                                     (0x0)
+#define PDP_D_DST_BASE_ADDR_LOW_0_SCR                                        (0)
+#define PDP_D_DST_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
+#define PDP_D_DST_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_RANGE                 (31:5)
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_WOFFSET                (0x0)
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_BASE_ADDR_HIGH_0
+#define PDP_D_DST_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xd074))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_SCR                                       (0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_RANGE               (31:0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_WOFFSET              (0x0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_LINE_STRIDE_0
+#define PDP_D_DST_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xd078))
+#define PDP_D_DST_LINE_STRIDE_0_SECURE                                     (0x0)
+#define PDP_D_DST_LINE_STRIDE_0_DUAL                                       (0x0)
+#define PDP_D_DST_LINE_STRIDE_0_SCR                                          (0)
+#define PDP_D_DST_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
+#define PDP_D_DST_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_RANGE                     (31:5)
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_WOFFSET                    (0x0)
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_SURFACE_STRIDE_0
+#define PDP_D_DST_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xd07c))
+#define PDP_D_DST_SURFACE_STRIDE_0_SECURE                                  (0x0)
+#define PDP_D_DST_SURFACE_STRIDE_0_DUAL                                    (0x0)
+#define PDP_D_DST_SURFACE_STRIDE_0_SCR                                       (0)
+#define PDP_D_DST_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
+#define PDP_D_DST_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_RANGE               (31:5)
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_WOFFSET              (0x0)
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_DST_RAM_CFG_0
+#define PDP_D_DST_RAM_CFG_0                             (_MK_ADDR_CONST(0xd080))
+#define PDP_D_DST_RAM_CFG_0_SECURE                                         (0x0)
+#define PDP_D_DST_RAM_CFG_0_DUAL                                           (0x0)
+#define PDP_D_DST_RAM_CFG_0_SCR                                              (0)
+#define PDP_D_DST_RAM_CFG_0_WORD_COUNT                                     (0x1)
+#define PDP_D_DST_RAM_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_READ_MASK                      (_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT              (_MK_SHIFT_CONST(0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_RANGE                             (0:0)
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_WOFFSET                           (0x0)
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_CV                  (_MK_ENUM_CONST(0))
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_MC                  (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_DATA_FORMAT_0
+#define PDP_D_DATA_FORMAT_0                             (_MK_ADDR_CONST(0xd084))
+#define PDP_D_DATA_FORMAT_0_SECURE                                         (0x0)
+#define PDP_D_DATA_FORMAT_0_DUAL                                           (0x0)
+#define PDP_D_DATA_FORMAT_0_SCR                                              (0)
+#define PDP_D_DATA_FORMAT_0_WORD_COUNT                                     (0x1)
+#define PDP_D_DATA_FORMAT_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_RESET_MASK                     (_MK_MASK_CONST(0x3))
+#define PDP_D_DATA_FORMAT_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_READ_MASK                      (_MK_MASK_CONST(0x3))
+#define PDP_D_DATA_FORMAT_0_WRITE_MASK                     (_MK_MASK_CONST(0x3))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT                (_MK_SHIFT_CONST(0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FIELD \
+	(_MK_FIELD_CONST(0x3, PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_RANGE                               (1:0)
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_WOFFSET                             (0x0)
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT             (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT_MASK        (_MK_MASK_CONST(0x3))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT8                  (_MK_ENUM_CONST(0))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT16                 (_MK_ENUM_CONST(1))
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FP16                  (_MK_ENUM_CONST(2))
+
+
+// Register PDP_D_INF_INPUT_NUM_0
+#define PDP_D_INF_INPUT_NUM_0                           (_MK_ADDR_CONST(0xd088))
+#define PDP_D_INF_INPUT_NUM_0_SECURE                                       (0x0)
+#define PDP_D_INF_INPUT_NUM_0_DUAL                                         (0x0)
+#define PDP_D_INF_INPUT_NUM_0_SCR                                            (0)
+#define PDP_D_INF_INPUT_NUM_0_WORD_COUNT                                   (0x1)
+#define PDP_D_INF_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_INF_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_INF_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_RANGE                         (31:0)
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_WOFFSET                        (0x0)
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_NAN_INPUT_NUM_0
+#define PDP_D_NAN_INPUT_NUM_0                           (_MK_ADDR_CONST(0xd08c))
+#define PDP_D_NAN_INPUT_NUM_0_SECURE                                       (0x0)
+#define PDP_D_NAN_INPUT_NUM_0_DUAL                                         (0x0)
+#define PDP_D_NAN_INPUT_NUM_0_SCR                                            (0)
+#define PDP_D_NAN_INPUT_NUM_0_WORD_COUNT                                   (0x1)
+#define PDP_D_NAN_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_RANGE                         (31:0)
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_WOFFSET                        (0x0)
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_NAN_OUTPUT_NUM_0
+#define PDP_D_NAN_OUTPUT_NUM_0                          (_MK_ADDR_CONST(0xd090))
+#define PDP_D_NAN_OUTPUT_NUM_0_SECURE                                      (0x0)
+#define PDP_D_NAN_OUTPUT_NUM_0_DUAL                                        (0x0)
+#define PDP_D_NAN_OUTPUT_NUM_0_SCR                                           (0)
+#define PDP_D_NAN_OUTPUT_NUM_0_WORD_COUNT                                  (0x1)
+#define PDP_D_NAN_OUTPUT_NUM_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_OUTPUT_NUM_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT         (_MK_SHIFT_CONST(0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_RANGE                       (31:0)
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_WOFFSET                      (0x0)
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT      (_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_PERF_ENABLE_0
+#define PDP_D_PERF_ENABLE_0                             (_MK_ADDR_CONST(0xd094))
+#define PDP_D_PERF_ENABLE_0_SECURE                                         (0x0)
+#define PDP_D_PERF_ENABLE_0_DUAL                                           (0x0)
+#define PDP_D_PERF_ENABLE_0_SCR                                              (0)
+#define PDP_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
+#define PDP_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT                    (_MK_SHIFT_CONST(0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_RANGE                                   (0:0)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_WOFFSET                                 (0x0)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                           (DISABLE)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_DISABLE                   (_MK_ENUM_CONST(0))
+#define PDP_D_PERF_ENABLE_0_DMA_EN_ENABLE                    (_MK_ENUM_CONST(1))
+
+
+// Register PDP_D_PERF_WRITE_STALL_0
+#define PDP_D_PERF_WRITE_STALL_0                        (_MK_ADDR_CONST(0xd098))
+#define PDP_D_PERF_WRITE_STALL_0_SECURE                                    (0x0)
+#define PDP_D_PERF_WRITE_STALL_0_DUAL                                      (0x0)
+#define PDP_D_PERF_WRITE_STALL_0_SCR                                         (0)
+#define PDP_D_PERF_WRITE_STALL_0_WORD_COUNT                                (0x1)
+#define PDP_D_PERF_WRITE_STALL_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_PERF_WRITE_STALL_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT     (_MK_SHIFT_CONST(0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_RANGE                   (31:0)
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_WOFFSET                  (0x0)
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register PDP_D_CYA_0
+#define PDP_D_CYA_0                                     (_MK_ADDR_CONST(0xd09c))
+#define PDP_D_CYA_0_SECURE                                                 (0x0)
+#define PDP_D_CYA_0_DUAL                                                   (0x0)
+#define PDP_D_CYA_0_SCR                                                      (0)
+#define PDP_D_CYA_0_WORD_COUNT                                             (0x1)
+#define PDP_D_CYA_0_RESET_VAL                              (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_RESET_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_CYA_0_SW_DEFAULT_VAL                         (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_SW_DEFAULT_MASK                        (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_READ_MASK                       (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_CYA_0_WRITE_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_CYA_0_CYA_SHIFT                               (_MK_SHIFT_CONST(0))
+#define PDP_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, PDP_D_CYA_0_CYA_SHIFT))
+#define PDP_D_CYA_0_CYA_RANGE                                             (31:0)
+#define PDP_D_CYA_0_CYA_WOFFSET                                            (0x0)
+#define PDP_D_CYA_0_CYA_DEFAULT                            (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_CYA_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff))
+#define PDP_D_CYA_0_CYA_SW_DEFAULT                         (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_CYA_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_CYA_PARITY_PROTECTION                  (_MK_MASK_CONST(0x0))
+#define PDP_D_CYA_0_CYA_PLATFORM_DEPENDENT                 (_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_S_STATUS_0
+#define CDP_RDMA_S_STATUS_0                             (_MK_ADDR_CONST(0xe000))
+#define CDP_RDMA_S_STATUS_0_SECURE                                         (0x0)
+#define CDP_RDMA_S_STATUS_0_DUAL                                           (0x0)
+#define CDP_RDMA_S_STATUS_0_SCR                                              (0)
+#define CDP_RDMA_S_STATUS_0_WORD_COUNT                                     (0x1)
+#define CDP_RDMA_S_STATUS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_RESET_MASK                 (_MK_MASK_CONST(0x30003))
+#define CDP_RDMA_S_STATUS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_READ_MASK                  (_MK_MASK_CONST(0x30003))
+#define CDP_RDMA_S_STATUS_0_WRITE_MASK                     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_RANGE                                 (1:0)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_WOFFSET                               (0x0)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_INIT_ENUM                            (IDLE)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_IDLE                    (_MK_ENUM_CONST(0))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_RUNNING                 (_MK_ENUM_CONST(1))
+#define CDP_RDMA_S_STATUS_0_STATUS_0_PENDING                 (_MK_ENUM_CONST(2))
+
+#define CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT                 (_MK_SHIFT_CONST(16))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_RANGE                               (17:16)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_WOFFSET                               (0x0)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_DEFAULT_MASK          (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_INIT_ENUM                            (IDLE)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_IDLE                    (_MK_ENUM_CONST(0))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_RUNNING                 (_MK_ENUM_CONST(1))
+#define CDP_RDMA_S_STATUS_0_STATUS_1_PENDING                 (_MK_ENUM_CONST(2))
+
+
+// Register CDP_RDMA_S_POINTER_0
+#define CDP_RDMA_S_POINTER_0                            (_MK_ADDR_CONST(0xe004))
+#define CDP_RDMA_S_POINTER_0_SECURE                                        (0x0)
+#define CDP_RDMA_S_POINTER_0_DUAL                                          (0x0)
+#define CDP_RDMA_S_POINTER_0_SCR                                             (0)
+#define CDP_RDMA_S_POINTER_0_WORD_COUNT                                    (0x1)
+#define CDP_RDMA_S_POINTER_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_RESET_MASK                (_MK_MASK_CONST(0x10001))
+#define CDP_RDMA_S_POINTER_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_READ_MASK                 (_MK_MASK_CONST(0x10001))
+#define CDP_RDMA_S_POINTER_0_WRITE_MASK                    (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT                 (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_RANGE                                (0:0)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_WOFFSET                              (0x0)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_INIT_ENUM                        (GROUP_0)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0                (_MK_ENUM_CONST(0))
+#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1                (_MK_ENUM_CONST(1))
+
+#define CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT                (_MK_SHIFT_CONST(16))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_RANGE                              (16:16)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_WOFFSET                              (0x0)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_DEFAULT_MASK         (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_INIT_ENUM                        (GROUP_0)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0                (_MK_ENUM_CONST(0))
+#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1                (_MK_ENUM_CONST(1))
+
+
+// Register CDP_RDMA_D_OP_ENABLE_0
+#define CDP_RDMA_D_OP_ENABLE_0                          (_MK_ADDR_CONST(0xe008))
+#define CDP_RDMA_D_OP_ENABLE_0_SECURE                                      (0x0)
+#define CDP_RDMA_D_OP_ENABLE_0_DUAL                                        (0x0)
+#define CDP_RDMA_D_OP_ENABLE_0_SCR                                           (0)
+#define CDP_RDMA_D_OP_ENABLE_0_WORD_COUNT                                  (0x1)
+#define CDP_RDMA_D_OP_ENABLE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT                  (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_RANGE                                 (0:0)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_WOFFSET                               (0x0)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT               (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK          (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT    (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_INIT_ENUM                         (DISABLE)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE                 (_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE                  (_MK_ENUM_CONST(1))
+
+
+// Register CDP_RDMA_D_DATA_CUBE_WIDTH_0
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0                    (_MK_ADDR_CONST(0xe00c))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SECURE                                (0x0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_DUAL                                  (0x0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SCR                                     (0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WORD_COUNT                            (0x1)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_RESET_MASK         (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_READ_MASK          (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WRITE_MASK         (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT            (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_RANGE                          (12:0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_WOFFSET                         (0x0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_DATA_CUBE_HEIGHT_0
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0                   (_MK_ADDR_CONST(0xe010))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SECURE                               (0x0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_DUAL                                 (0x0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SCR                                    (0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_WORD_COUNT                           (0x1)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_RESET_MASK        (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_VAL       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_READ_MASK         (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_WRITE_MASK        (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_RANGE                        (12:0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_WOFFSET                       (0x0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_DATA_CUBE_CHANNEL_0
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0                  (_MK_ADDR_CONST(0xe014))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SECURE                              (0x0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_DUAL                                (0x0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SCR                                   (0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_WORD_COUNT                          (0x1)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_RESET_MASK       (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_READ_MASK        (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_WRITE_MASK       (_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_RANGE                      (12:0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_WOFFSET                     (0x0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_BASE_ADDR_LOW_0
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0                  (_MK_ADDR_CONST(0xe018))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SECURE                              (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_DUAL                                (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SCR                                   (0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WORD_COUNT                          (0x1)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_VAL           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_VAL      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_READ_MASK    (_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_RANGE            (31:5)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_WOFFSET           (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0                 (_MK_ADDR_CONST(0xe01c))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SECURE                             (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_DUAL                               (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SCR                                  (0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WORD_COUNT                         (0x1)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_RANGE          (31:0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_WOFFSET         (0x0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_LINE_STRIDE_0
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0                    (_MK_ADDR_CONST(0xe020))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SECURE                                (0x0)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_DUAL                                  (0x0)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SCR                                     (0)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_WORD_COUNT                            (0x1)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_RESET_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_READ_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_WRITE_MASK     (_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_RANGE                (31:5)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_WOFFSET               (0x0)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_SURFACE_STRIDE_0
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0                 (_MK_ADDR_CONST(0xe024))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SECURE                             (0x0)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_DUAL                               (0x0)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SCR                                  (0)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_WORD_COUNT                         (0x1)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_RESET_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_READ_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_WRITE_MASK \
+	(_MK_MASK_CONST(0xffffffe0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_RANGE          (31:5)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_WOFFSET         (0x0)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_SRC_DMA_CFG_0
+#define CDP_RDMA_D_SRC_DMA_CFG_0                        (_MK_ADDR_CONST(0xe028))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SECURE                                    (0x0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_DUAL                                      (0x0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SCR                                         (0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_WORD_COUNT                                (0x1)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_RANGE                        (0:0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_WOFFSET                      (0x0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV             (_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC             (_MK_ENUM_CONST(1))
+
+
+// Register CDP_RDMA_D_SRC_COMPRESSION_EN_0
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0                 (_MK_ADDR_CONST(0xe02c))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SECURE                             (0x0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_DUAL                               (0x0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SCR                                  (0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_WORD_COUNT                         (0x1)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_RESET_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_RESET_MASK         (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SW_DEFAULT_VAL     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_READ_MASK          (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_WRITE_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_RANGE           (0:0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_WOFFSET         (0x0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DISABLE \
+	(_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_ENABLE \
+	(_MK_ENUM_CONST(1))
+
+
+// Register CDP_RDMA_D_OPERATION_MODE_0
+#define CDP_RDMA_D_OPERATION_MODE_0                     (_MK_ADDR_CONST(0xe030))
+#define CDP_RDMA_D_OPERATION_MODE_0_SECURE                                 (0x0)
+#define CDP_RDMA_D_OPERATION_MODE_0_DUAL                                   (0x0)
+#define CDP_RDMA_D_OPERATION_MODE_0_SCR                                      (0)
+#define CDP_RDMA_D_OPERATION_MODE_0_WORD_COUNT                             (0x1)
+#define CDP_RDMA_D_OPERATION_MODE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_RESET_MASK             (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_OPERATION_MODE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_READ_MASK              (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_OPERATION_MODE_0_WRITE_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT    (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_FIELD \
+	(_MK_FIELD_CONST(0x3, \
+	CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_RANGE                   (1:0)
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WOFFSET                 (0x0)
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_READPHILE \
+	(_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WRITEPHILE \
+	(_MK_ENUM_CONST(1))
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_ORDINARY \
+	(_MK_ENUM_CONST(2))
+
+
+// Register CDP_RDMA_D_DATA_FORMAT_0
+#define CDP_RDMA_D_DATA_FORMAT_0                        (_MK_ADDR_CONST(0xe034))
+#define CDP_RDMA_D_DATA_FORMAT_0_SECURE                                    (0x0)
+#define CDP_RDMA_D_DATA_FORMAT_0_DUAL                                      (0x0)
+#define CDP_RDMA_D_DATA_FORMAT_0_SCR                                         (0)
+#define CDP_RDMA_D_DATA_FORMAT_0_WORD_COUNT                                (0x1)
+#define CDP_RDMA_D_DATA_FORMAT_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_RESET_MASK                (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_READ_MASK                 (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_DATA_FORMAT_0_WRITE_MASK                (_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT           (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_RANGE                          (1:0)
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_WOFFSET                        (0x0)
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8             (_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16            (_MK_ENUM_CONST(1))
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16             (_MK_ENUM_CONST(2))
+
+
+// Register CDP_RDMA_D_PERF_ENABLE_0
+#define CDP_RDMA_D_PERF_ENABLE_0                        (_MK_ADDR_CONST(0xe038))
+#define CDP_RDMA_D_PERF_ENABLE_0_SECURE                                    (0x0)
+#define CDP_RDMA_D_PERF_ENABLE_0_DUAL                                      (0x0)
+#define CDP_RDMA_D_PERF_ENABLE_0_SCR                                         (0)
+#define CDP_RDMA_D_PERF_ENABLE_0_WORD_COUNT                                (0x1)
+#define CDP_RDMA_D_PERF_ENABLE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_RESET_MASK                (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_READ_MASK                 (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_WRITE_MASK                (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT               (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_RANGE                              (0:0)
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_WOFFSET                            (0x0)
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                      (DISABLE)
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE              (_MK_ENUM_CONST(0))
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE               (_MK_ENUM_CONST(1))
+
+
+// Register CDP_RDMA_D_PERF_READ_STALL_0
+#define CDP_RDMA_D_PERF_READ_STALL_0                    (_MK_ADDR_CONST(0xe03c))
+#define CDP_RDMA_D_PERF_READ_STALL_0_SECURE                                (0x0)
+#define CDP_RDMA_D_PERF_READ_STALL_0_DUAL                                  (0x0)
+#define CDP_RDMA_D_PERF_READ_STALL_0_SCR                                     (0)
+#define CDP_RDMA_D_PERF_READ_STALL_0_WORD_COUNT                            (0x1)
+#define CDP_RDMA_D_PERF_READ_STALL_0_RESET_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_READ_STALL_0_RESET_MASK     (_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_VAL        (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_READ_STALL_0_SW_DEFAULT_MASK       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_READ_STALL_0_READ_MASK      (_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_PERF_READ_STALL_0_WRITE_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT))
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_RANGE                (31:0)
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_WOFFSET               (0x0)
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_RDMA_D_CYA_0
+#define CDP_RDMA_D_CYA_0                                (_MK_ADDR_CONST(0xe040))
+#define CDP_RDMA_D_CYA_0_SECURE                                            (0x0)
+#define CDP_RDMA_D_CYA_0_DUAL                                              (0x0)
+#define CDP_RDMA_D_CYA_0_SCR                                                 (0)
+#define CDP_RDMA_D_CYA_0_WORD_COUNT                                        (0x1)
+#define CDP_RDMA_D_CYA_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_CYA_0_RESET_MASK                 (_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_CYA_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_CYA_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_CYA_0_READ_MASK                  (_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_CYA_0_WRITE_MASK                 (_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_CYA_0_CYA_SHIFT                          (_MK_SHIFT_CONST(0))
+#define CDP_RDMA_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_CYA_0_CYA_SHIFT))
+#define CDP_RDMA_D_CYA_0_CYA_RANGE                                        (31:0)
+#define CDP_RDMA_D_CYA_0_CYA_WOFFSET                                       (0x0)
+#define CDP_RDMA_D_CYA_0_CYA_DEFAULT                       (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_CYA_0_CYA_DEFAULT_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_RDMA_D_CYA_0_CYA_SW_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_CYA_0_CYA_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_CYA_0_CYA_PARITY_PROTECTION             (_MK_MASK_CONST(0x0))
+#define CDP_RDMA_D_CYA_0_CYA_PLATFORM_DEPENDENT            (_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_STATUS_0
+#define CDP_S_STATUS_0                                  (_MK_ADDR_CONST(0xf000))
+#define CDP_S_STATUS_0_SECURE                                              (0x0)
+#define CDP_S_STATUS_0_DUAL                                                (0x0)
+#define CDP_S_STATUS_0_SCR                                                   (0)
+#define CDP_S_STATUS_0_WORD_COUNT                                          (0x1)
+#define CDP_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
+#define CDP_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
+#define CDP_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CDP_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_0_SHIFT))
+#define CDP_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
+#define CDP_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
+#define CDP_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define CDP_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CDP_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
+#define CDP_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
+#define CDP_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
+#define CDP_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
+
+#define CDP_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
+#define CDP_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_1_SHIFT))
+#define CDP_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
+#define CDP_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
+#define CDP_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define CDP_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CDP_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CDP_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
+#define CDP_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
+#define CDP_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
+#define CDP_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
+
+
+// Register CDP_S_POINTER_0
+#define CDP_S_POINTER_0                                 (_MK_ADDR_CONST(0xf004))
+#define CDP_S_POINTER_0_SECURE                                             (0x0)
+#define CDP_S_POINTER_0_DUAL                                               (0x0)
+#define CDP_S_POINTER_0_SCR                                                  (0)
+#define CDP_S_POINTER_0_WORD_COUNT                                         (0x1)
+#define CDP_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
+#define CDP_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
+#define CDP_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
+#define CDP_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
+#define CDP_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_S_POINTER_0_PRODUCER_SHIFT))
+#define CDP_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
+#define CDP_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
+#define CDP_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CDP_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CDP_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
+#define CDP_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define CDP_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+#define CDP_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
+#define CDP_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_S_POINTER_0_CONSUMER_SHIFT))
+#define CDP_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
+#define CDP_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
+#define CDP_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define CDP_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define CDP_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define CDP_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
+#define CDP_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define CDP_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+
+// Register CDP_S_LUT_ACCESS_CFG_0
+#define CDP_S_LUT_ACCESS_CFG_0                          (_MK_ADDR_CONST(0xf008))
+#define CDP_S_LUT_ACCESS_CFG_0_SECURE                                      (0x0)
+#define CDP_S_LUT_ACCESS_CFG_0_DUAL                                        (0x0)
+#define CDP_S_LUT_ACCESS_CFG_0_SCR                                           (0)
+#define CDP_S_LUT_ACCESS_CFG_0_WORD_COUNT                                  (0x1)
+#define CDP_S_LUT_ACCESS_CFG_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_RESET_MASK              (_MK_MASK_CONST(0x303ff))
+#define CDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_READ_MASK               (_MK_MASK_CONST(0x303ff))
+#define CDP_S_LUT_ACCESS_CFG_0_WRITE_MASK              (_MK_MASK_CONST(0x303ff))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT               (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD \
+	(_MK_FIELD_CONST(0x3ff, CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_RANGE                              (9:0)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_WOFFSET                            (0x0)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_DEFAULT_MASK     (_MK_MASK_CONST(0x3ff))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT          (_MK_SHIFT_CONST(16))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_RANGE                        (16:16)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_WOFFSET                        (0x0)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE               (_MK_ENUM_CONST(0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO               (_MK_ENUM_CONST(1))
+
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT       (_MK_SHIFT_CONST(17))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_RANGE                     (17:17)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WOFFSET                     (0x0)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ          (_MK_ENUM_CONST(0))
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE         (_MK_ENUM_CONST(1))
+
+
+// Register CDP_S_LUT_ACCESS_DATA_0
+#define CDP_S_LUT_ACCESS_DATA_0                         (_MK_ADDR_CONST(0xf00c))
+#define CDP_S_LUT_ACCESS_DATA_0_SECURE                                     (0x0)
+#define CDP_S_LUT_ACCESS_DATA_0_DUAL                                       (0x0)
+#define CDP_S_LUT_ACCESS_DATA_0_SCR                                          (0)
+#define CDP_S_LUT_ACCESS_DATA_0_WORD_COUNT                                 (0x1)
+#define CDP_S_LUT_ACCESS_DATA_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_DATA_0_RESET_MASK              (_MK_MASK_CONST(0xffff))
+#define CDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_DATA_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_DATA_0_READ_MASK               (_MK_MASK_CONST(0xffff))
+#define CDP_S_LUT_ACCESS_DATA_0_WRITE_MASK              (_MK_MASK_CONST(0xffff))
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT              (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT))
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_RANGE                            (15:0)
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_WOFFSET                           (0x0)
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_CFG_0
+#define CDP_S_LUT_CFG_0                                 (_MK_ADDR_CONST(0xf010))
+#define CDP_S_LUT_CFG_0_SECURE                                             (0x0)
+#define CDP_S_LUT_CFG_0_DUAL                                               (0x0)
+#define CDP_S_LUT_CFG_0_SCR                                                  (0)
+#define CDP_S_LUT_CFG_0_WORD_COUNT                                         (0x1)
+#define CDP_S_LUT_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_RESET_MASK                        (_MK_MASK_CONST(0x71))
+#define CDP_S_LUT_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_READ_MASK                         (_MK_MASK_CONST(0x71))
+#define CDP_S_LUT_CFG_0_WRITE_MASK                        (_MK_MASK_CONST(0x71))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT               (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_RANGE                              (0:0)
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_WOFFSET                            (0x0)
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT            (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_DEFAULT_MASK       (_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT             (_MK_ENUM_CONST(0))
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR               (_MK_ENUM_CONST(1))
+
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(4))
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT))
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_RANGE                           (4:4)
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_WOFFSET                         (0x0)
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
+
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT            (_MK_SHIFT_CONST(5))
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT))
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_RANGE                           (5:5)
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_WOFFSET                         (0x0)
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_DEFAULT_MASK    (_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE                (_MK_ENUM_CONST(0))
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO                (_MK_ENUM_CONST(1))
+
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT           (_MK_SHIFT_CONST(6))
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT))
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_RANGE                          (6:6)
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_WOFFSET                        (0x0)
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE               (_MK_ENUM_CONST(0))
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO               (_MK_ENUM_CONST(1))
+
+
+// Register CDP_S_LUT_INFO_0
+#define CDP_S_LUT_INFO_0                                (_MK_ADDR_CONST(0xf014))
+#define CDP_S_LUT_INFO_0_SECURE                                            (0x0)
+#define CDP_S_LUT_INFO_0_DUAL                                              (0x0)
+#define CDP_S_LUT_INFO_0_SCR                                                 (0)
+#define CDP_S_LUT_INFO_0_WORD_COUNT                                        (0x1)
+#define CDP_S_LUT_INFO_0_RESET_VAL                         (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_RESET_MASK                   (_MK_MASK_CONST(0xffffff))
+#define CDP_S_LUT_INFO_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_READ_MASK                    (_MK_MASK_CONST(0xffffff))
+#define CDP_S_LUT_INFO_0_WRITE_MASK                   (_MK_MASK_CONST(0xffffff))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT          (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_RANGE                         (7:0)
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_WOFFSET                       (0x0)
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT          (_MK_SHIFT_CONST(8))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD \
+	(_MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_RANGE                        (15:8)
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_WOFFSET                       (0x0)
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT         (_MK_SHIFT_CONST(16))
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD \
+	(_MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT))
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_RANGE                       (23:16)
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_WOFFSET                       (0x0)
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xff))
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LE_START_LOW_0
+#define CDP_S_LUT_LE_START_LOW_0                        (_MK_ADDR_CONST(0xf018))
+#define CDP_S_LUT_LE_START_LOW_0_SECURE                                    (0x0)
+#define CDP_S_LUT_LE_START_LOW_0_DUAL                                      (0x0)
+#define CDP_S_LUT_LE_START_LOW_0_SCR                                         (0)
+#define CDP_S_LUT_LE_START_LOW_0_WORD_COUNT                                (0x1)
+#define CDP_S_LUT_LE_START_LOW_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_LOW_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_START_LOW_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_LOW_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_LOW_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_START_LOW_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT     (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT))
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_RANGE                   (31:0)
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_WOFFSET                  (0x0)
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LE_START_HIGH_0
+#define CDP_S_LUT_LE_START_HIGH_0                       (_MK_ADDR_CONST(0xf01c))
+#define CDP_S_LUT_LE_START_HIGH_0_SECURE                                   (0x0)
+#define CDP_S_LUT_LE_START_HIGH_0_DUAL                                     (0x0)
+#define CDP_S_LUT_LE_START_HIGH_0_SCR                                        (0)
+#define CDP_S_LUT_LE_START_HIGH_0_WORD_COUNT                               (0x1)
+#define CDP_S_LUT_LE_START_HIGH_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_HIGH_0_RESET_MASK              (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LE_START_HIGH_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_HIGH_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_HIGH_0_READ_MASK               (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LE_START_HIGH_0_WRITE_MASK              (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT))
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_RANGE                  (5:0)
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_WOFFSET                (0x0)
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LE_END_LOW_0
+#define CDP_S_LUT_LE_END_LOW_0                          (_MK_ADDR_CONST(0xf020))
+#define CDP_S_LUT_LE_END_LOW_0_SECURE                                      (0x0)
+#define CDP_S_LUT_LE_END_LOW_0_DUAL                                        (0x0)
+#define CDP_S_LUT_LE_END_LOW_0_SCR                                           (0)
+#define CDP_S_LUT_LE_END_LOW_0_WORD_COUNT                                  (0x1)
+#define CDP_S_LUT_LE_END_LOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_LOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_END_LOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_LOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_LOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_END_LOW_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT))
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_RANGE                       (31:0)
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_WOFFSET                      (0x0)
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LE_END_HIGH_0
+#define CDP_S_LUT_LE_END_HIGH_0                         (_MK_ADDR_CONST(0xf024))
+#define CDP_S_LUT_LE_END_HIGH_0_SECURE                                     (0x0)
+#define CDP_S_LUT_LE_END_HIGH_0_DUAL                                       (0x0)
+#define CDP_S_LUT_LE_END_HIGH_0_SCR                                          (0)
+#define CDP_S_LUT_LE_END_HIGH_0_WORD_COUNT                                 (0x1)
+#define CDP_S_LUT_LE_END_HIGH_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_HIGH_0_RESET_MASK                (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LE_END_HIGH_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_HIGH_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_HIGH_0_READ_MASK                 (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LE_END_HIGH_0_WRITE_MASK                (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT       (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT))
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_RANGE                      (5:0)
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_WOFFSET                    (0x0)
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LO_START_LOW_0
+#define CDP_S_LUT_LO_START_LOW_0                        (_MK_ADDR_CONST(0xf028))
+#define CDP_S_LUT_LO_START_LOW_0_SECURE                                    (0x0)
+#define CDP_S_LUT_LO_START_LOW_0_DUAL                                      (0x0)
+#define CDP_S_LUT_LO_START_LOW_0_SCR                                         (0)
+#define CDP_S_LUT_LO_START_LOW_0_WORD_COUNT                                (0x1)
+#define CDP_S_LUT_LO_START_LOW_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_LOW_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_START_LOW_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_LOW_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_LOW_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_START_LOW_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT     (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT))
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_RANGE                   (31:0)
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_WOFFSET                  (0x0)
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LO_START_HIGH_0
+#define CDP_S_LUT_LO_START_HIGH_0                       (_MK_ADDR_CONST(0xf02c))
+#define CDP_S_LUT_LO_START_HIGH_0_SECURE                                   (0x0)
+#define CDP_S_LUT_LO_START_HIGH_0_DUAL                                     (0x0)
+#define CDP_S_LUT_LO_START_HIGH_0_SCR                                        (0)
+#define CDP_S_LUT_LO_START_HIGH_0_WORD_COUNT                               (0x1)
+#define CDP_S_LUT_LO_START_HIGH_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_HIGH_0_RESET_MASK              (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LO_START_HIGH_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_HIGH_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_HIGH_0_READ_MASK               (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LO_START_HIGH_0_WRITE_MASK              (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT))
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_RANGE                  (5:0)
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_WOFFSET                (0x0)
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LO_END_LOW_0
+#define CDP_S_LUT_LO_END_LOW_0                          (_MK_ADDR_CONST(0xf030))
+#define CDP_S_LUT_LO_END_LOW_0_SECURE                                      (0x0)
+#define CDP_S_LUT_LO_END_LOW_0_DUAL                                        (0x0)
+#define CDP_S_LUT_LO_END_LOW_0_SCR                                           (0)
+#define CDP_S_LUT_LO_END_LOW_0_WORD_COUNT                                  (0x1)
+#define CDP_S_LUT_LO_END_LOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_LOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_END_LOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_LOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_LOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_END_LOW_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT))
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_RANGE                       (31:0)
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_WOFFSET                      (0x0)
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LO_END_HIGH_0
+#define CDP_S_LUT_LO_END_HIGH_0                         (_MK_ADDR_CONST(0xf034))
+#define CDP_S_LUT_LO_END_HIGH_0_SECURE                                     (0x0)
+#define CDP_S_LUT_LO_END_HIGH_0_DUAL                                       (0x0)
+#define CDP_S_LUT_LO_END_HIGH_0_SCR                                          (0)
+#define CDP_S_LUT_LO_END_HIGH_0_WORD_COUNT                                 (0x1)
+#define CDP_S_LUT_LO_END_HIGH_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_HIGH_0_RESET_MASK                (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LO_END_HIGH_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_HIGH_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_HIGH_0_READ_MASK                 (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LO_END_HIGH_0_WRITE_MASK                (_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT       (_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_FIELD \
+	(_MK_FIELD_CONST(0x3f, \
+	CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT))
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_RANGE                      (5:0)
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_WOFFSET                    (0x0)
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LE_SLOPE_SCALE_0
+#define CDP_S_LUT_LE_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xf038))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_SECURE                                  (0x0)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_DUAL                                    (0x0)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_SCR                                       (0)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_RANGE         (15:0)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_RANGE        (31:16)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LE_SLOPE_SHIFT_0
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xf03c))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_SECURE                                  (0x0)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_DUAL                                    (0x0)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_SCR                                       (0)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LO_SLOPE_SCALE_0
+#define CDP_S_LUT_LO_SLOPE_SCALE_0                      (_MK_ADDR_CONST(0xf040))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_SECURE                                  (0x0)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_DUAL                                    (0x0)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_SCR                                       (0)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_WORD_COUNT                              (0x1)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_RANGE         (15:0)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_WOFFSET        (0x0)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT \
+	(_MK_SHIFT_CONST(16))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, \
+	CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_RANGE        (31:16)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_WOFFSET        (0x0)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_S_LUT_LO_SLOPE_SHIFT_0
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0                      (_MK_ADDR_CONST(0xf044))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_SECURE                                  (0x0)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_DUAL                                    (0x0)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_SCR                                       (0)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_WORD_COUNT                              (0x1)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_RESET_MASK            (_MK_MASK_CONST(0x3ff))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_READ_MASK             (_MK_MASK_CONST(0x3ff))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_WRITE_MASK            (_MK_MASK_CONST(0x3ff))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_RANGE          (4:0)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_WOFFSET        (0x0)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD \
+	(_MK_FIELD_CONST(0x1f, \
+	CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_RANGE          (9:5)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_WOFFSET        (0x0)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_OP_ENABLE_0
+#define CDP_D_OP_ENABLE_0                               (_MK_ADDR_CONST(0xf048))
+#define CDP_D_OP_ENABLE_0_SECURE                                           (0x0)
+#define CDP_D_OP_ENABLE_0_DUAL                                             (0x0)
+#define CDP_D_OP_ENABLE_0_SCR                                                (0)
+#define CDP_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
+#define CDP_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define CDP_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define CDP_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define CDP_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define CDP_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define CDP_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define CDP_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define CDP_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
+#define CDP_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
+#define CDP_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define CDP_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define CDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CDP_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define CDP_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define CDP_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
+#define CDP_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define CDP_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+
+// Register CDP_D_FUNC_BYPASS_0
+#define CDP_D_FUNC_BYPASS_0                             (_MK_ADDR_CONST(0xf04c))
+#define CDP_D_FUNC_BYPASS_0_SECURE                                         (0x0)
+#define CDP_D_FUNC_BYPASS_0_DUAL                                           (0x0)
+#define CDP_D_FUNC_BYPASS_0_SCR                                              (0)
+#define CDP_D_FUNC_BYPASS_0_WORD_COUNT                                     (0x1)
+#define CDP_D_FUNC_BYPASS_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_RESET_MASK                     (_MK_MASK_CONST(0x3))
+#define CDP_D_FUNC_BYPASS_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_READ_MASK                      (_MK_MASK_CONST(0x3))
+#define CDP_D_FUNC_BYPASS_0_WRITE_MASK                     (_MK_MASK_CONST(0x3))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT              (_MK_SHIFT_CONST(0))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_RANGE                             (0:0)
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_WOFFSET                           (0x0)
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_INIT_ENUM                     (DISABLE)
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DISABLE             (_MK_ENUM_CONST(0))
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_ENABLE              (_MK_ENUM_CONST(1))
+
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT                (_MK_SHIFT_CONST(1))
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT))
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_RANGE                               (1:1)
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_WOFFSET                             (0x0)
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DEFAULT_MASK        (_MK_MASK_CONST(0x1))
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SW_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SW_DEFAULT_MASK     (_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_INIT_ENUM                       (DISABLE)
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DISABLE               (_MK_ENUM_CONST(0))
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_ENABLE                (_MK_ENUM_CONST(1))
+
+
+// Register CDP_D_DST_BASE_ADDR_LOW_0
+#define CDP_D_DST_BASE_ADDR_LOW_0                       (_MK_ADDR_CONST(0xf050))
+#define CDP_D_DST_BASE_ADDR_LOW_0_SECURE                                   (0x0)
+#define CDP_D_DST_BASE_ADDR_LOW_0_DUAL                                     (0x0)
+#define CDP_D_DST_BASE_ADDR_LOW_0_SCR                                        (0)
+#define CDP_D_DST_BASE_ADDR_LOW_0_WORD_COUNT                               (0x1)
+#define CDP_D_DST_BASE_ADDR_LOW_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT))
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_RANGE                 (31:5)
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_WOFFSET                (0x0)
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_DST_BASE_ADDR_HIGH_0
+#define CDP_D_DST_BASE_ADDR_HIGH_0                      (_MK_ADDR_CONST(0xf054))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_SECURE                                  (0x0)
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DUAL                                    (0x0)
+#define CDP_D_DST_BASE_ADDR_HIGH_0_SCR                                       (0)
+#define CDP_D_DST_BASE_ADDR_HIGH_0_WORD_COUNT                              (0x1)
+#define CDP_D_DST_BASE_ADDR_HIGH_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_RESET_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_READ_MASK        (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_RANGE               (31:0)
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_WOFFSET              (0x0)
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_DST_LINE_STRIDE_0
+#define CDP_D_DST_LINE_STRIDE_0                         (_MK_ADDR_CONST(0xf058))
+#define CDP_D_DST_LINE_STRIDE_0_SECURE                                     (0x0)
+#define CDP_D_DST_LINE_STRIDE_0_DUAL                                       (0x0)
+#define CDP_D_DST_LINE_STRIDE_0_SCR                                          (0)
+#define CDP_D_DST_LINE_STRIDE_0_WORD_COUNT                                 (0x1)
+#define CDP_D_DST_LINE_STRIDE_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_LINE_STRIDE_0_RESET_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_LINE_STRIDE_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_LINE_STRIDE_0_READ_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define CDP_D_DST_LINE_STRIDE_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT       (_MK_SHIFT_CONST(5))
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT))
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_RANGE                     (31:5)
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_WOFFSET                    (0x0)
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_DST_SURFACE_STRIDE_0
+#define CDP_D_DST_SURFACE_STRIDE_0                      (_MK_ADDR_CONST(0xf05c))
+#define CDP_D_DST_SURFACE_STRIDE_0_SECURE                                  (0x0)
+#define CDP_D_DST_SURFACE_STRIDE_0_DUAL                                    (0x0)
+#define CDP_D_DST_SURFACE_STRIDE_0_SCR                                       (0)
+#define CDP_D_DST_SURFACE_STRIDE_0_WORD_COUNT                              (0x1)
+#define CDP_D_DST_SURFACE_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_SURFACE_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define CDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_SURFACE_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_SURFACE_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define CDP_D_DST_SURFACE_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT))
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_RANGE               (31:5)
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_WOFFSET              (0x0)
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_DST_DMA_CFG_0
+#define CDP_D_DST_DMA_CFG_0                             (_MK_ADDR_CONST(0xf060))
+#define CDP_D_DST_DMA_CFG_0_SECURE                                         (0x0)
+#define CDP_D_DST_DMA_CFG_0_DUAL                                           (0x0)
+#define CDP_D_DST_DMA_CFG_0_SCR                                              (0)
+#define CDP_D_DST_DMA_CFG_0_WORD_COUNT                                     (0x1)
+#define CDP_D_DST_DMA_CFG_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_DMA_CFG_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
+#define CDP_D_DST_DMA_CFG_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_DMA_CFG_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_DMA_CFG_0_READ_MASK                      (_MK_MASK_CONST(0x1))
+#define CDP_D_DST_DMA_CFG_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT              (_MK_SHIFT_CONST(0))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_RANGE                             (0:0)
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_WOFFSET                           (0x0)
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT           (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_DEFAULT_MASK      (_MK_MASK_CONST(0x1))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV                  (_MK_ENUM_CONST(0))
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC                  (_MK_ENUM_CONST(1))
+
+
+// Register CDP_D_DST_COMPRESSION_EN_0
+#define CDP_D_DST_COMPRESSION_EN_0                      (_MK_ADDR_CONST(0xf064))
+#define CDP_D_DST_COMPRESSION_EN_0_SECURE                                  (0x0)
+#define CDP_D_DST_COMPRESSION_EN_0_DUAL                                    (0x0)
+#define CDP_D_DST_COMPRESSION_EN_0_SCR                                       (0)
+#define CDP_D_DST_COMPRESSION_EN_0_WORD_COUNT                              (0x1)
+#define CDP_D_DST_COMPRESSION_EN_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_COMPRESSION_EN_0_RESET_MASK              (_MK_MASK_CONST(0x1))
+#define CDP_D_DST_COMPRESSION_EN_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_COMPRESSION_EN_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_COMPRESSION_EN_0_READ_MASK               (_MK_MASK_CONST(0x1))
+#define CDP_D_DST_COMPRESSION_EN_0_WRITE_MASK              (_MK_MASK_CONST(0x0))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT \
+	(_MK_SHIFT_CONST(0))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, \
+	CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_RANGE                (0:0)
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_WOFFSET              (0x0)
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DISABLE \
+	(_MK_ENUM_CONST(0))
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_ENABLE \
+	(_MK_ENUM_CONST(1))
+
+
+// Register CDP_D_DATA_FORMAT_0
+#define CDP_D_DATA_FORMAT_0                             (_MK_ADDR_CONST(0xf068))
+#define CDP_D_DATA_FORMAT_0_SECURE                                         (0x0)
+#define CDP_D_DATA_FORMAT_0_DUAL                                           (0x0)
+#define CDP_D_DATA_FORMAT_0_SCR                                              (0)
+#define CDP_D_DATA_FORMAT_0_WORD_COUNT                                     (0x1)
+#define CDP_D_DATA_FORMAT_0_RESET_VAL                      (_MK_MASK_CONST(0x1))
+#define CDP_D_DATA_FORMAT_0_RESET_MASK                     (_MK_MASK_CONST(0x3))
+#define CDP_D_DATA_FORMAT_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_D_DATA_FORMAT_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CDP_D_DATA_FORMAT_0_READ_MASK                      (_MK_MASK_CONST(0x3))
+#define CDP_D_DATA_FORMAT_0_WRITE_MASK                     (_MK_MASK_CONST(0x3))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT           (_MK_SHIFT_CONST(0))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_RANGE                          (1:0)
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_WOFFSET                        (0x0)
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_DEFAULT        (_MK_MASK_CONST(0x1))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT8             (_MK_ENUM_CONST(0))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT16            (_MK_ENUM_CONST(1))
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FP16             (_MK_ENUM_CONST(2))
+
+
+// Register CDP_D_NAN_FLUSH_TO_ZERO_0
+#define CDP_D_NAN_FLUSH_TO_ZERO_0                       (_MK_ADDR_CONST(0xf06c))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_SECURE                                   (0x0)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_DUAL                                     (0x0)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_SCR                                        (0)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_WORD_COUNT                               (0x1)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_RESET_MASK               (_MK_MASK_CONST(0x1))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_READ_MASK                (_MK_MASK_CONST(0x1))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_WRITE_MASK               (_MK_MASK_CONST(0x1))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_RANGE                        (0:0)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_WOFFSET                      (0x0)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_INIT_ENUM                (DISABLE)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE        (_MK_ENUM_CONST(0))
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE         (_MK_ENUM_CONST(1))
+
+
+// Register CDP_D_LRN_CFG_0
+#define CDP_D_LRN_CFG_0                                 (_MK_ADDR_CONST(0xf070))
+#define CDP_D_LRN_CFG_0_SECURE                                             (0x0)
+#define CDP_D_LRN_CFG_0_DUAL                                               (0x0)
+#define CDP_D_LRN_CFG_0_SCR                                                  (0)
+#define CDP_D_LRN_CFG_0_WORD_COUNT                                         (0x1)
+#define CDP_D_LRN_CFG_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define CDP_D_LRN_CFG_0_RESET_MASK                         (_MK_MASK_CONST(0x3))
+#define CDP_D_LRN_CFG_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define CDP_D_LRN_CFG_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CDP_D_LRN_CFG_0_READ_MASK                          (_MK_MASK_CONST(0x3))
+#define CDP_D_LRN_CFG_0_WRITE_MASK                         (_MK_MASK_CONST(0x3))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT                   (_MK_SHIFT_CONST(0))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_FIELD \
+	(_MK_FIELD_CONST(0x3, CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_RANGE                                  (1:0)
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_WOFFSET                                (0x0)
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_DEFAULT                (_MK_MASK_CONST(0x0))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_DEFAULT_MASK           (_MK_MASK_CONST(0x3))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN3                     (_MK_ENUM_CONST(0))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN5                     (_MK_ENUM_CONST(1))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN7                     (_MK_ENUM_CONST(2))
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9                     (_MK_ENUM_CONST(3))
+
+
+// Register CDP_D_DATIN_OFFSET_0
+#define CDP_D_DATIN_OFFSET_0                            (_MK_ADDR_CONST(0xf074))
+#define CDP_D_DATIN_OFFSET_0_SECURE                                        (0x0)
+#define CDP_D_DATIN_OFFSET_0_DUAL                                          (0x0)
+#define CDP_D_DATIN_OFFSET_0_SCR                                             (0)
+#define CDP_D_DATIN_OFFSET_0_WORD_COUNT                                    (0x1)
+#define CDP_D_DATIN_OFFSET_0_RESET_VAL                     (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_OFFSET_0_RESET_MASK                 (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATIN_OFFSET_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_OFFSET_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_OFFSET_0_READ_MASK                  (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATIN_OFFSET_0_WRITE_MASK                 (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT             (_MK_SHIFT_CONST(0))
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT))
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_RANGE                           (15:0)
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_WOFFSET                          (0x0)
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_DEFAULT          (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_DATIN_SCALE_0
+#define CDP_D_DATIN_SCALE_0                             (_MK_ADDR_CONST(0xf078))
+#define CDP_D_DATIN_SCALE_0_SECURE                                         (0x0)
+#define CDP_D_DATIN_SCALE_0_DUAL                                           (0x0)
+#define CDP_D_DATIN_SCALE_0_SCR                                              (0)
+#define CDP_D_DATIN_SCALE_0_WORD_COUNT                                     (0x1)
+#define CDP_D_DATIN_SCALE_0_RESET_VAL                      (_MK_MASK_CONST(0x1))
+#define CDP_D_DATIN_SCALE_0_RESET_MASK                  (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATIN_SCALE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SCALE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SCALE_0_READ_MASK                   (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATIN_SCALE_0_WRITE_MASK                  (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT               (_MK_SHIFT_CONST(0))
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT))
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_RANGE                             (15:0)
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_WOFFSET                            (0x0)
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_DEFAULT            (_MK_MASK_CONST(0x1))
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_DEFAULT_MASK    (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SW_DEFAULT         (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SW_DEFAULT_MASK    (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_DATIN_SHIFTER_0
+#define CDP_D_DATIN_SHIFTER_0                           (_MK_ADDR_CONST(0xf07c))
+#define CDP_D_DATIN_SHIFTER_0_SECURE                                       (0x0)
+#define CDP_D_DATIN_SHIFTER_0_DUAL                                         (0x0)
+#define CDP_D_DATIN_SHIFTER_0_SCR                                            (0)
+#define CDP_D_DATIN_SHIFTER_0_WORD_COUNT                                   (0x1)
+#define CDP_D_DATIN_SHIFTER_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SHIFTER_0_RESET_MASK                  (_MK_MASK_CONST(0x1f))
+#define CDP_D_DATIN_SHIFTER_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SHIFTER_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SHIFTER_0_READ_MASK                   (_MK_MASK_CONST(0x1f))
+#define CDP_D_DATIN_SHIFTER_0_WRITE_MASK                  (_MK_MASK_CONST(0x1f))
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT           (_MK_SHIFT_CONST(0))
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_FIELD \
+	(_MK_FIELD_CONST(0x1f, CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT))
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_RANGE                          (4:0)
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_WOFFSET                        (0x0)
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_DATOUT_OFFSET_0
+#define CDP_D_DATOUT_OFFSET_0                           (_MK_ADDR_CONST(0xf080))
+#define CDP_D_DATOUT_OFFSET_0_SECURE                                       (0x0)
+#define CDP_D_DATOUT_OFFSET_0_DUAL                                         (0x0)
+#define CDP_D_DATOUT_OFFSET_0_SCR                                            (0)
+#define CDP_D_DATOUT_OFFSET_0_WORD_COUNT                                   (0x1)
+#define CDP_D_DATOUT_OFFSET_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_OFFSET_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_DATOUT_OFFSET_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_OFFSET_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_OFFSET_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_DATOUT_OFFSET_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT           (_MK_SHIFT_CONST(0))
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT))
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_RANGE                         (31:0)
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_WOFFSET                        (0x0)
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_DATOUT_SCALE_0
+#define CDP_D_DATOUT_SCALE_0                            (_MK_ADDR_CONST(0xf084))
+#define CDP_D_DATOUT_SCALE_0_SECURE                                        (0x0)
+#define CDP_D_DATOUT_SCALE_0_DUAL                                          (0x0)
+#define CDP_D_DATOUT_SCALE_0_SCR                                             (0)
+#define CDP_D_DATOUT_SCALE_0_WORD_COUNT                                    (0x1)
+#define CDP_D_DATOUT_SCALE_0_RESET_VAL                     (_MK_MASK_CONST(0x1))
+#define CDP_D_DATOUT_SCALE_0_RESET_MASK                 (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATOUT_SCALE_0_SW_DEFAULT_VAL                (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SCALE_0_SW_DEFAULT_MASK               (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SCALE_0_READ_MASK                  (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATOUT_SCALE_0_WRITE_MASK                 (_MK_MASK_CONST(0xffff))
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT             (_MK_SHIFT_CONST(0))
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_FIELD \
+	(_MK_FIELD_CONST(0xffff, CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT))
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_RANGE                           (15:0)
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_WOFFSET                          (0x0)
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_DEFAULT          (_MK_MASK_CONST(0x1))
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffff))
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SW_DEFAULT       (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_DATOUT_SHIFTER_0
+#define CDP_D_DATOUT_SHIFTER_0                          (_MK_ADDR_CONST(0xf088))
+#define CDP_D_DATOUT_SHIFTER_0_SECURE                                      (0x0)
+#define CDP_D_DATOUT_SHIFTER_0_DUAL                                        (0x0)
+#define CDP_D_DATOUT_SHIFTER_0_SCR                                           (0)
+#define CDP_D_DATOUT_SHIFTER_0_WORD_COUNT                                  (0x1)
+#define CDP_D_DATOUT_SHIFTER_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SHIFTER_0_RESET_MASK                 (_MK_MASK_CONST(0x3f))
+#define CDP_D_DATOUT_SHIFTER_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SHIFTER_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SHIFTER_0_READ_MASK                  (_MK_MASK_CONST(0x3f))
+#define CDP_D_DATOUT_SHIFTER_0_WRITE_MASK                 (_MK_MASK_CONST(0x3f))
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_FIELD \
+	(_MK_FIELD_CONST(0x3f, CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT))
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_RANGE                        (5:0)
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_WOFFSET                      (0x0)
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x3f))
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_NAN_INPUT_NUM_0
+#define CDP_D_NAN_INPUT_NUM_0                           (_MK_ADDR_CONST(0xf08c))
+#define CDP_D_NAN_INPUT_NUM_0_SECURE                                       (0x0)
+#define CDP_D_NAN_INPUT_NUM_0_DUAL                                         (0x0)
+#define CDP_D_NAN_INPUT_NUM_0_SCR                                            (0)
+#define CDP_D_NAN_INPUT_NUM_0_WORD_COUNT                                   (0x1)
+#define CDP_D_NAN_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_NAN_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT))
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_RANGE                         (31:0)
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_WOFFSET                        (0x0)
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_INF_INPUT_NUM_0
+#define CDP_D_INF_INPUT_NUM_0                           (_MK_ADDR_CONST(0xf090))
+#define CDP_D_INF_INPUT_NUM_0_SECURE                                       (0x0)
+#define CDP_D_INF_INPUT_NUM_0_DUAL                                         (0x0)
+#define CDP_D_INF_INPUT_NUM_0_SCR                                            (0)
+#define CDP_D_INF_INPUT_NUM_0_WORD_COUNT                                   (0x1)
+#define CDP_D_INF_INPUT_NUM_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define CDP_D_INF_INPUT_NUM_0_RESET_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_INF_INPUT_NUM_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define CDP_D_INF_INPUT_NUM_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define CDP_D_INF_INPUT_NUM_0_READ_MASK             (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_INF_INPUT_NUM_0_WRITE_MASK                   (_MK_MASK_CONST(0x0))
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT           (_MK_SHIFT_CONST(0))
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT))
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_RANGE                         (31:0)
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_WOFFSET                        (0x0)
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT        (_MK_MASK_CONST(0x0))
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_NAN_OUTPUT_NUM_0
+#define CDP_D_NAN_OUTPUT_NUM_0                          (_MK_ADDR_CONST(0xf094))
+#define CDP_D_NAN_OUTPUT_NUM_0_SECURE                                      (0x0)
+#define CDP_D_NAN_OUTPUT_NUM_0_DUAL                                        (0x0)
+#define CDP_D_NAN_OUTPUT_NUM_0_SCR                                           (0)
+#define CDP_D_NAN_OUTPUT_NUM_0_WORD_COUNT                                  (0x1)
+#define CDP_D_NAN_OUTPUT_NUM_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_OUTPUT_NUM_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_OUTPUT_NUM_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_OUTPUT_NUM_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_NAN_OUTPUT_NUM_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT))
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_RANGE                       (31:0)
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_WOFFSET                      (0x0)
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_OUT_SATURATION_0
+#define CDP_D_OUT_SATURATION_0                          (_MK_ADDR_CONST(0xf098))
+#define CDP_D_OUT_SATURATION_0_SECURE                                      (0x0)
+#define CDP_D_OUT_SATURATION_0_DUAL                                        (0x0)
+#define CDP_D_OUT_SATURATION_0_SCR                                           (0)
+#define CDP_D_OUT_SATURATION_0_WORD_COUNT                                  (0x1)
+#define CDP_D_OUT_SATURATION_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_D_OUT_SATURATION_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_OUT_SATURATION_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_D_OUT_SATURATION_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_D_OUT_SATURATION_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_OUT_SATURATION_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT))
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_RANGE                       (31:0)
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_WOFFSET                      (0x0)
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_PERF_ENABLE_0
+#define CDP_D_PERF_ENABLE_0                             (_MK_ADDR_CONST(0xf09c))
+#define CDP_D_PERF_ENABLE_0_SECURE                                         (0x0)
+#define CDP_D_PERF_ENABLE_0_DUAL                                           (0x0)
+#define CDP_D_PERF_ENABLE_0_SCR                                              (0)
+#define CDP_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
+#define CDP_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0x3))
+#define CDP_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0x3))
+#define CDP_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0x3))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT                    (_MK_SHIFT_CONST(0))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_RANGE                                   (0:0)
+#define CDP_D_PERF_ENABLE_0_DMA_EN_WOFFSET                                 (0x0)
+#define CDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_INIT_ENUM                           (DISABLE)
+#define CDP_D_PERF_ENABLE_0_DMA_EN_DISABLE                   (_MK_ENUM_CONST(0))
+#define CDP_D_PERF_ENABLE_0_DMA_EN_ENABLE                    (_MK_ENUM_CONST(1))
+
+#define CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT                    (_MK_SHIFT_CONST(1))
+#define CDP_D_PERF_ENABLE_0_LUT_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT))
+#define CDP_D_PERF_ENABLE_0_LUT_EN_RANGE                                   (1:1)
+#define CDP_D_PERF_ENABLE_0_LUT_EN_WOFFSET                                 (0x0)
+#define CDP_D_PERF_ENABLE_0_LUT_EN_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_LUT_EN_DEFAULT_MASK            (_MK_MASK_CONST(0x1))
+#define CDP_D_PERF_ENABLE_0_LUT_EN_SW_DEFAULT              (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_LUT_EN_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_LUT_EN_PARITY_PROTECTION       (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_ENABLE_0_LUT_EN_PLATFORM_DEPENDENT      (_MK_MASK_CONST(0x1))
+#define CDP_D_PERF_ENABLE_0_LUT_EN_INIT_ENUM                           (DISABLE)
+#define CDP_D_PERF_ENABLE_0_LUT_EN_DISABLE                   (_MK_ENUM_CONST(0))
+#define CDP_D_PERF_ENABLE_0_LUT_EN_ENABLE                    (_MK_ENUM_CONST(1))
+
+
+// Register CDP_D_PERF_WRITE_STALL_0
+#define CDP_D_PERF_WRITE_STALL_0                        (_MK_ADDR_CONST(0xf0a0))
+#define CDP_D_PERF_WRITE_STALL_0_SECURE                                    (0x0)
+#define CDP_D_PERF_WRITE_STALL_0_DUAL                                      (0x0)
+#define CDP_D_PERF_WRITE_STALL_0_SCR                                         (0)
+#define CDP_D_PERF_WRITE_STALL_0_WORD_COUNT                                (0x1)
+#define CDP_D_PERF_WRITE_STALL_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_WRITE_STALL_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_WRITE_STALL_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_WRITE_STALL_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_WRITE_STALL_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT     (_MK_SHIFT_CONST(0))
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT))
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_RANGE                   (31:0)
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_WOFFSET                  (0x0)
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_PERF_LUT_UFLOW_0
+#define CDP_D_PERF_LUT_UFLOW_0                          (_MK_ADDR_CONST(0xf0a4))
+#define CDP_D_PERF_LUT_UFLOW_0_SECURE                                      (0x0)
+#define CDP_D_PERF_LUT_UFLOW_0_DUAL                                        (0x0)
+#define CDP_D_PERF_LUT_UFLOW_0_SCR                                           (0)
+#define CDP_D_PERF_LUT_UFLOW_0_WORD_COUNT                                  (0x1)
+#define CDP_D_PERF_LUT_UFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_UFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_UFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_UFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_UFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT))
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_RANGE                       (31:0)
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_WOFFSET                      (0x0)
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_PERF_LUT_OFLOW_0
+#define CDP_D_PERF_LUT_OFLOW_0                          (_MK_ADDR_CONST(0xf0a8))
+#define CDP_D_PERF_LUT_OFLOW_0_SECURE                                      (0x0)
+#define CDP_D_PERF_LUT_OFLOW_0_DUAL                                        (0x0)
+#define CDP_D_PERF_LUT_OFLOW_0_SCR                                           (0)
+#define CDP_D_PERF_LUT_OFLOW_0_WORD_COUNT                                  (0x1)
+#define CDP_D_PERF_LUT_OFLOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_OFLOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_OFLOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_OFLOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_OFLOW_0_WRITE_MASK                  (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT         (_MK_SHIFT_CONST(0))
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT))
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_RANGE                       (31:0)
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_WOFFSET                      (0x0)
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_PERF_LUT_HYBRID_0
+#define CDP_D_PERF_LUT_HYBRID_0                         (_MK_ADDR_CONST(0xf0ac))
+#define CDP_D_PERF_LUT_HYBRID_0_SECURE                                     (0x0)
+#define CDP_D_PERF_LUT_HYBRID_0_DUAL                                       (0x0)
+#define CDP_D_PERF_LUT_HYBRID_0_SCR                                          (0)
+#define CDP_D_PERF_LUT_HYBRID_0_WORD_COUNT                                 (0x1)
+#define CDP_D_PERF_LUT_HYBRID_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_HYBRID_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_HYBRID_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_HYBRID_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_HYBRID_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT       (_MK_SHIFT_CONST(0))
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT))
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_RANGE                     (31:0)
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_WOFFSET                    (0x0)
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_PERF_LUT_LE_HIT_0
+#define CDP_D_PERF_LUT_LE_HIT_0                         (_MK_ADDR_CONST(0xf0b0))
+#define CDP_D_PERF_LUT_LE_HIT_0_SECURE                                     (0x0)
+#define CDP_D_PERF_LUT_LE_HIT_0_DUAL                                       (0x0)
+#define CDP_D_PERF_LUT_LE_HIT_0_SCR                                          (0)
+#define CDP_D_PERF_LUT_LE_HIT_0_WORD_COUNT                                 (0x1)
+#define CDP_D_PERF_LUT_LE_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LE_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LE_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LE_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_LE_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT       (_MK_SHIFT_CONST(0))
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT))
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_RANGE                     (31:0)
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_WOFFSET                    (0x0)
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_PERF_LUT_LO_HIT_0
+#define CDP_D_PERF_LUT_LO_HIT_0                         (_MK_ADDR_CONST(0xf0b4))
+#define CDP_D_PERF_LUT_LO_HIT_0_SECURE                                     (0x0)
+#define CDP_D_PERF_LUT_LO_HIT_0_DUAL                                       (0x0)
+#define CDP_D_PERF_LUT_LO_HIT_0_SCR                                          (0)
+#define CDP_D_PERF_LUT_LO_HIT_0_WORD_COUNT                                 (0x1)
+#define CDP_D_PERF_LUT_LO_HIT_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LO_HIT_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LO_HIT_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LO_HIT_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_LO_HIT_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT       (_MK_SHIFT_CONST(0))
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT))
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_RANGE                     (31:0)
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_WOFFSET                    (0x0)
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_DEFAULT    (_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register CDP_D_CYA_0
+#define CDP_D_CYA_0                                     (_MK_ADDR_CONST(0xf0b8))
+#define CDP_D_CYA_0_SECURE                                                 (0x0)
+#define CDP_D_CYA_0_DUAL                                                   (0x0)
+#define CDP_D_CYA_0_SCR                                                      (0)
+#define CDP_D_CYA_0_WORD_COUNT                                             (0x1)
+#define CDP_D_CYA_0_RESET_VAL                              (_MK_MASK_CONST(0x0))
+#define CDP_D_CYA_0_RESET_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_CYA_0_SW_DEFAULT_VAL                         (_MK_MASK_CONST(0x0))
+#define CDP_D_CYA_0_SW_DEFAULT_MASK                        (_MK_MASK_CONST(0x0))
+#define CDP_D_CYA_0_READ_MASK                       (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_CYA_0_WRITE_MASK                      (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_CYA_0_CYA_SHIFT                               (_MK_SHIFT_CONST(0))
+#define CDP_D_CYA_0_CYA_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, CDP_D_CYA_0_CYA_SHIFT))
+#define CDP_D_CYA_0_CYA_RANGE                                             (31:0)
+#define CDP_D_CYA_0_CYA_WOFFSET                                            (0x0)
+#define CDP_D_CYA_0_CYA_DEFAULT                            (_MK_MASK_CONST(0x0))
+#define CDP_D_CYA_0_CYA_DEFAULT_MASK                (_MK_MASK_CONST(0xffffffff))
+#define CDP_D_CYA_0_CYA_SW_DEFAULT                         (_MK_MASK_CONST(0x0))
+#define CDP_D_CYA_0_CYA_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define CDP_D_CYA_0_CYA_PARITY_PROTECTION                  (_MK_MASK_CONST(0x0))
+#define CDP_D_CYA_0_CYA_PLATFORM_DEPENDENT                 (_MK_MASK_CONST(0x1))
+
+
+// Register RBK_S_STATUS_0
+#define RBK_S_STATUS_0                                 (_MK_ADDR_CONST(0x10000))
+#define RBK_S_STATUS_0_SECURE                                              (0x0)
+#define RBK_S_STATUS_0_DUAL                                                (0x0)
+#define RBK_S_STATUS_0_SCR                                                   (0)
+#define RBK_S_STATUS_0_WORD_COUNT                                          (0x1)
+#define RBK_S_STATUS_0_RESET_VAL                           (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_RESET_MASK                      (_MK_MASK_CONST(0x30003))
+#define RBK_S_STATUS_0_SW_DEFAULT_VAL                      (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_SW_DEFAULT_MASK                     (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_READ_MASK                       (_MK_MASK_CONST(0x30003))
+#define RBK_S_STATUS_0_WRITE_MASK                          (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_STATUS_0_SHIFT                       (_MK_SHIFT_CONST(0))
+#define RBK_S_STATUS_0_STATUS_0_FIELD \
+	(_MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_0_SHIFT))
+#define RBK_S_STATUS_0_STATUS_0_RANGE                                      (1:0)
+#define RBK_S_STATUS_0_STATUS_0_WOFFSET                                    (0x0)
+#define RBK_S_STATUS_0_STATUS_0_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_STATUS_0_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define RBK_S_STATUS_0_STATUS_0_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_STATUS_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_STATUS_0_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_STATUS_0_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define RBK_S_STATUS_0_STATUS_0_INIT_ENUM                                 (IDLE)
+#define RBK_S_STATUS_0_STATUS_0_IDLE                         (_MK_ENUM_CONST(0))
+#define RBK_S_STATUS_0_STATUS_0_RUNNING                      (_MK_ENUM_CONST(1))
+#define RBK_S_STATUS_0_STATUS_0_PENDING                      (_MK_ENUM_CONST(2))
+
+#define RBK_S_STATUS_0_STATUS_1_SHIFT                      (_MK_SHIFT_CONST(16))
+#define RBK_S_STATUS_0_STATUS_1_FIELD \
+	(_MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_1_SHIFT))
+#define RBK_S_STATUS_0_STATUS_1_RANGE                                    (17:16)
+#define RBK_S_STATUS_0_STATUS_1_WOFFSET                                    (0x0)
+#define RBK_S_STATUS_0_STATUS_1_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_STATUS_1_DEFAULT_MASK               (_MK_MASK_CONST(0x3))
+#define RBK_S_STATUS_0_STATUS_1_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_STATUS_1_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_STATUS_1_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define RBK_S_STATUS_0_STATUS_1_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define RBK_S_STATUS_0_STATUS_1_INIT_ENUM                                 (IDLE)
+#define RBK_S_STATUS_0_STATUS_1_IDLE                         (_MK_ENUM_CONST(0))
+#define RBK_S_STATUS_0_STATUS_1_RUNNING                      (_MK_ENUM_CONST(1))
+#define RBK_S_STATUS_0_STATUS_1_PENDING                      (_MK_ENUM_CONST(2))
+
+
+// Register RBK_S_POINTER_0
+#define RBK_S_POINTER_0                                (_MK_ADDR_CONST(0x10004))
+#define RBK_S_POINTER_0_SECURE                                             (0x0)
+#define RBK_S_POINTER_0_DUAL                                               (0x0)
+#define RBK_S_POINTER_0_SCR                                                  (0)
+#define RBK_S_POINTER_0_WORD_COUNT                                         (0x1)
+#define RBK_S_POINTER_0_RESET_VAL                          (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_RESET_MASK                     (_MK_MASK_CONST(0x10001))
+#define RBK_S_POINTER_0_SW_DEFAULT_VAL                     (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_SW_DEFAULT_MASK                    (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_READ_MASK                      (_MK_MASK_CONST(0x10001))
+#define RBK_S_POINTER_0_WRITE_MASK                         (_MK_MASK_CONST(0x1))
+#define RBK_S_POINTER_0_PRODUCER_SHIFT                      (_MK_SHIFT_CONST(0))
+#define RBK_S_POINTER_0_PRODUCER_FIELD \
+	(_MK_FIELD_CONST(0x1, RBK_S_POINTER_0_PRODUCER_SHIFT))
+#define RBK_S_POINTER_0_PRODUCER_RANGE                                     (0:0)
+#define RBK_S_POINTER_0_PRODUCER_WOFFSET                                   (0x0)
+#define RBK_S_POINTER_0_PRODUCER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_PRODUCER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define RBK_S_POINTER_0_PRODUCER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_PRODUCER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_PRODUCER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_PRODUCER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define RBK_S_POINTER_0_PRODUCER_INIT_ENUM                             (GROUP_0)
+#define RBK_S_POINTER_0_PRODUCER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define RBK_S_POINTER_0_PRODUCER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+#define RBK_S_POINTER_0_CONSUMER_SHIFT                     (_MK_SHIFT_CONST(16))
+#define RBK_S_POINTER_0_CONSUMER_FIELD \
+	(_MK_FIELD_CONST(0x1, RBK_S_POINTER_0_CONSUMER_SHIFT))
+#define RBK_S_POINTER_0_CONSUMER_RANGE                                   (16:16)
+#define RBK_S_POINTER_0_CONSUMER_WOFFSET                                   (0x0)
+#define RBK_S_POINTER_0_CONSUMER_DEFAULT                   (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_CONSUMER_DEFAULT_MASK              (_MK_MASK_CONST(0x1))
+#define RBK_S_POINTER_0_CONSUMER_SW_DEFAULT                (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_CONSUMER_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_CONSUMER_PARITY_PROTECTION         (_MK_MASK_CONST(0x0))
+#define RBK_S_POINTER_0_CONSUMER_PLATFORM_DEPENDENT        (_MK_MASK_CONST(0x1))
+#define RBK_S_POINTER_0_CONSUMER_INIT_ENUM                             (GROUP_0)
+#define RBK_S_POINTER_0_CONSUMER_GROUP_0                     (_MK_ENUM_CONST(0))
+#define RBK_S_POINTER_0_CONSUMER_GROUP_1                     (_MK_ENUM_CONST(1))
+
+
+// Register RBK_D_OP_ENABLE_0
+#define RBK_D_OP_ENABLE_0                              (_MK_ADDR_CONST(0x10008))
+#define RBK_D_OP_ENABLE_0_SECURE                                           (0x0)
+#define RBK_D_OP_ENABLE_0_DUAL                                             (0x0)
+#define RBK_D_OP_ENABLE_0_SCR                                                (0)
+#define RBK_D_OP_ENABLE_0_WORD_COUNT                                       (0x1)
+#define RBK_D_OP_ENABLE_0_RESET_VAL                        (_MK_MASK_CONST(0x0))
+#define RBK_D_OP_ENABLE_0_RESET_MASK                       (_MK_MASK_CONST(0x1))
+#define RBK_D_OP_ENABLE_0_SW_DEFAULT_VAL                   (_MK_MASK_CONST(0x0))
+#define RBK_D_OP_ENABLE_0_SW_DEFAULT_MASK                  (_MK_MASK_CONST(0x0))
+#define RBK_D_OP_ENABLE_0_READ_MASK                        (_MK_MASK_CONST(0x1))
+#define RBK_D_OP_ENABLE_0_WRITE_MASK                       (_MK_MASK_CONST(0x1))
+#define RBK_D_OP_ENABLE_0_OP_EN_SHIFT                       (_MK_SHIFT_CONST(0))
+#define RBK_D_OP_ENABLE_0_OP_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, RBK_D_OP_ENABLE_0_OP_EN_SHIFT))
+#define RBK_D_OP_ENABLE_0_OP_EN_RANGE                                      (0:0)
+#define RBK_D_OP_ENABLE_0_OP_EN_WOFFSET                                    (0x0)
+#define RBK_D_OP_ENABLE_0_OP_EN_DEFAULT                    (_MK_MASK_CONST(0x0))
+#define RBK_D_OP_ENABLE_0_OP_EN_DEFAULT_MASK               (_MK_MASK_CONST(0x1))
+#define RBK_D_OP_ENABLE_0_OP_EN_SW_DEFAULT                 (_MK_MASK_CONST(0x0))
+#define RBK_D_OP_ENABLE_0_OP_EN_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define RBK_D_OP_ENABLE_0_OP_EN_PARITY_PROTECTION          (_MK_MASK_CONST(0x0))
+#define RBK_D_OP_ENABLE_0_OP_EN_PLATFORM_DEPENDENT         (_MK_MASK_CONST(0x1))
+#define RBK_D_OP_ENABLE_0_OP_EN_INIT_ENUM                              (DISABLE)
+#define RBK_D_OP_ENABLE_0_OP_EN_DISABLE                      (_MK_ENUM_CONST(0))
+#define RBK_D_OP_ENABLE_0_OP_EN_ENABLE                       (_MK_ENUM_CONST(1))
+
+
+// Register RBK_D_MISC_CFG_0
+#define RBK_D_MISC_CFG_0                               (_MK_ADDR_CONST(0x1000c))
+#define RBK_D_MISC_CFG_0_SECURE                                            (0x0)
+#define RBK_D_MISC_CFG_0_DUAL                                              (0x0)
+#define RBK_D_MISC_CFG_0_SCR                                                 (0)
+#define RBK_D_MISC_CFG_0_WORD_COUNT                                        (0x1)
+#define RBK_D_MISC_CFG_0_RESET_VAL                       (_MK_MASK_CONST(0x100))
+#define RBK_D_MISC_CFG_0_RESET_MASK                      (_MK_MASK_CONST(0x303))
+#define RBK_D_MISC_CFG_0_SW_DEFAULT_VAL                    (_MK_MASK_CONST(0x0))
+#define RBK_D_MISC_CFG_0_SW_DEFAULT_MASK                   (_MK_MASK_CONST(0x0))
+#define RBK_D_MISC_CFG_0_READ_MASK                       (_MK_MASK_CONST(0x303))
+#define RBK_D_MISC_CFG_0_WRITE_MASK                      (_MK_MASK_CONST(0x303))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT                   (_MK_SHIFT_CONST(0))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_FIELD \
+	(_MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_RANGE                                  (1:0)
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_WOFFSET                                (0x0)
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_DEFAULT                (_MK_MASK_CONST(0x0))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_DEFAULT_MASK           (_MK_MASK_CONST(0x3))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_INIT_ENUM                         (CONTRACT)
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_CONTRACT                 (_MK_ENUM_CONST(0))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_SPLIT                    (_MK_ENUM_CONST(1))
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE                    (_MK_ENUM_CONST(2))
+
+#define RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT                 (_MK_SHIFT_CONST(8))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_FIELD \
+	(_MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_RANGE                                (9:8)
+#define RBK_D_MISC_CFG_0_IN_PRECISION_WOFFSET                              (0x0)
+#define RBK_D_MISC_CFG_0_IN_PRECISION_DEFAULT              (_MK_MASK_CONST(0x1))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_DEFAULT_MASK         (_MK_MASK_CONST(0x3))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT           (_MK_MASK_CONST(0x0))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_SW_DEFAULT_MASK      (_MK_MASK_CONST(0x0))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_PARITY_PROTECTION    (_MK_MASK_CONST(0x0))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_INIT_ENUM                          (INT16)
+#define RBK_D_MISC_CFG_0_IN_PRECISION_INT8                   (_MK_ENUM_CONST(0))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_INT16                  (_MK_ENUM_CONST(1))
+#define RBK_D_MISC_CFG_0_IN_PRECISION_FP16                   (_MK_ENUM_CONST(2))
+
+
+// Register RBK_D_DAIN_RAM_TYPE_0
+#define RBK_D_DAIN_RAM_TYPE_0                          (_MK_ADDR_CONST(0x10010))
+#define RBK_D_DAIN_RAM_TYPE_0_SECURE                                       (0x0)
+#define RBK_D_DAIN_RAM_TYPE_0_DUAL                                         (0x0)
+#define RBK_D_DAIN_RAM_TYPE_0_SCR                                            (0)
+#define RBK_D_DAIN_RAM_TYPE_0_WORD_COUNT                                   (0x1)
+#define RBK_D_DAIN_RAM_TYPE_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_RAM_TYPE_0_RESET_MASK                   (_MK_MASK_CONST(0x1))
+#define RBK_D_DAIN_RAM_TYPE_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_RAM_TYPE_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_RAM_TYPE_0_READ_MASK                    (_MK_MASK_CONST(0x1))
+#define RBK_D_DAIN_RAM_TYPE_0_WRITE_MASK                   (_MK_MASK_CONST(0x1))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT         (_MK_SHIFT_CONST(0))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_RANGE                        (0:0)
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_WOFFSET                      (0x0)
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_INIT_ENUM                   (CVIF)
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF           (_MK_ENUM_CONST(0))
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF           (_MK_ENUM_CONST(1))
+
+
+// Register RBK_D_DATAIN_SIZE_0_0
+#define RBK_D_DATAIN_SIZE_0_0                          (_MK_ADDR_CONST(0x10014))
+#define RBK_D_DATAIN_SIZE_0_0_SECURE                                       (0x0)
+#define RBK_D_DATAIN_SIZE_0_0_DUAL                                         (0x0)
+#define RBK_D_DATAIN_SIZE_0_0_SCR                                            (0)
+#define RBK_D_DATAIN_SIZE_0_0_WORD_COUNT                                   (0x1)
+#define RBK_D_DATAIN_SIZE_0_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_RESET_MASK            (_MK_MASK_CONST(0x1fff1fff))
+#define RBK_D_DATAIN_SIZE_0_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_READ_MASK             (_MK_MASK_CONST(0x1fff1fff))
+#define RBK_D_DATAIN_SIZE_0_0_WRITE_MASK            (_MK_MASK_CONST(0x1fff1fff))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT            (_MK_SHIFT_CONST(0))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD \
+	(_MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_RANGE                          (12:0)
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_WOFFSET                         (0x0)
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT         (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT          (_MK_SHIFT_CONST(16))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD \
+	(_MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_RANGE                        (28:16)
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_WOFFSET                        (0x0)
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT        (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DATAIN_SIZE_1_0
+#define RBK_D_DATAIN_SIZE_1_0                          (_MK_ADDR_CONST(0x10018))
+#define RBK_D_DATAIN_SIZE_1_0_SECURE                                       (0x0)
+#define RBK_D_DATAIN_SIZE_1_0_DUAL                                         (0x0)
+#define RBK_D_DATAIN_SIZE_1_0_SCR                                            (0)
+#define RBK_D_DATAIN_SIZE_1_0_WORD_COUNT                                   (0x1)
+#define RBK_D_DATAIN_SIZE_1_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_1_0_RESET_MASK                (_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAIN_SIZE_1_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_1_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_1_0_READ_MASK                 (_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAIN_SIZE_1_0_WRITE_MASK                (_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT          (_MK_SHIFT_CONST(0))
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT))
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_RANGE                        (12:0)
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_WOFFSET                       (0x0)
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT       (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAIN_ADDR_HIGH_0
+#define RBK_D_DAIN_ADDR_HIGH_0                         (_MK_ADDR_CONST(0x1001c))
+#define RBK_D_DAIN_ADDR_HIGH_0_SECURE                                      (0x0)
+#define RBK_D_DAIN_ADDR_HIGH_0_DUAL                                        (0x0)
+#define RBK_D_DAIN_ADDR_HIGH_0_SCR                                           (0)
+#define RBK_D_DAIN_ADDR_HIGH_0_WORD_COUNT                                  (0x1)
+#define RBK_D_DAIN_ADDR_HIGH_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_HIGH_0_RESET_MASK           (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_DAIN_ADDR_HIGH_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_HIGH_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_HIGH_0_READ_MASK            (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_DAIN_ADDR_HIGH_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT         (_MK_SHIFT_CONST(0))
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT))
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_RANGE                       (31:0)
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_WOFFSET                      (0x0)
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_DEFAULT      (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAIN_ADDR_LOW_0
+#define RBK_D_DAIN_ADDR_LOW_0                          (_MK_ADDR_CONST(0x10020))
+#define RBK_D_DAIN_ADDR_LOW_0_SECURE                                       (0x0)
+#define RBK_D_DAIN_ADDR_LOW_0_DUAL                                         (0x0)
+#define RBK_D_DAIN_ADDR_LOW_0_SCR                                            (0)
+#define RBK_D_DAIN_ADDR_LOW_0_WORD_COUNT                                   (0x1)
+#define RBK_D_DAIN_ADDR_LOW_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_LOW_0_RESET_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_ADDR_LOW_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_LOW_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_LOW_0_READ_MASK             (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_ADDR_LOW_0_WRITE_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT           (_MK_SHIFT_CONST(5))
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT))
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_RANGE                         (31:5)
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_WOFFSET                        (0x0)
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_DEFAULT        (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SW_DEFAULT     (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAIN_LINE_STRIDE_0
+#define RBK_D_DAIN_LINE_STRIDE_0                       (_MK_ADDR_CONST(0x10024))
+#define RBK_D_DAIN_LINE_STRIDE_0_SECURE                                    (0x0)
+#define RBK_D_DAIN_LINE_STRIDE_0_DUAL                                      (0x0)
+#define RBK_D_DAIN_LINE_STRIDE_0_SCR                                         (0)
+#define RBK_D_DAIN_LINE_STRIDE_0_WORD_COUNT                                (0x1)
+#define RBK_D_DAIN_LINE_STRIDE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_LINE_STRIDE_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_LINE_STRIDE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_LINE_STRIDE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_LINE_STRIDE_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_LINE_STRIDE_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT     (_MK_SHIFT_CONST(5))
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT))
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_RANGE                   (31:5)
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_WOFFSET                  (0x0)
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAIN_SURF_STRIDE_0
+#define RBK_D_DAIN_SURF_STRIDE_0                       (_MK_ADDR_CONST(0x10028))
+#define RBK_D_DAIN_SURF_STRIDE_0_SECURE                                    (0x0)
+#define RBK_D_DAIN_SURF_STRIDE_0_DUAL                                      (0x0)
+#define RBK_D_DAIN_SURF_STRIDE_0_SCR                                         (0)
+#define RBK_D_DAIN_SURF_STRIDE_0_WORD_COUNT                                (0x1)
+#define RBK_D_DAIN_SURF_STRIDE_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_SURF_STRIDE_0_RESET_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_SURF_STRIDE_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_SURF_STRIDE_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_SURF_STRIDE_0_READ_MASK          (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_SURF_STRIDE_0_WRITE_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT     (_MK_SHIFT_CONST(5))
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT))
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_RANGE                   (31:5)
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_WOFFSET                  (0x0)
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAIN_PLANAR_STRIDE_0
+#define RBK_D_DAIN_PLANAR_STRIDE_0                     (_MK_ADDR_CONST(0x1002c))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_SECURE                                  (0x0)
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DUAL                                    (0x0)
+#define RBK_D_DAIN_PLANAR_STRIDE_0_SCR                                       (0)
+#define RBK_D_DAIN_PLANAR_STRIDE_0_WORD_COUNT                              (0x1)
+#define RBK_D_DAIN_PLANAR_STRIDE_0_RESET_VAL               (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_RESET_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_SW_DEFAULT_VAL          (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_SW_DEFAULT_MASK         (_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_READ_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_WRITE_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_RANGE               (31:5)
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_WOFFSET              (0x0)
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAOUT_RAM_TYPE_0
+#define RBK_D_DAOUT_RAM_TYPE_0                         (_MK_ADDR_CONST(0x10030))
+#define RBK_D_DAOUT_RAM_TYPE_0_SECURE                                      (0x0)
+#define RBK_D_DAOUT_RAM_TYPE_0_DUAL                                        (0x0)
+#define RBK_D_DAOUT_RAM_TYPE_0_SCR                                           (0)
+#define RBK_D_DAOUT_RAM_TYPE_0_WORD_COUNT                                  (0x1)
+#define RBK_D_DAOUT_RAM_TYPE_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_RAM_TYPE_0_RESET_MASK                  (_MK_MASK_CONST(0x1))
+#define RBK_D_DAOUT_RAM_TYPE_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_RAM_TYPE_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_RAM_TYPE_0_READ_MASK                   (_MK_MASK_CONST(0x1))
+#define RBK_D_DAOUT_RAM_TYPE_0_WRITE_MASK                  (_MK_MASK_CONST(0x1))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT       (_MK_SHIFT_CONST(0))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_FIELD \
+	(_MK_FIELD_CONST(0x1, RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_RANGE                      (0:0)
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_WOFFSET                    (0x0)
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_DEFAULT    (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_INIT_ENUM                 (CVIF)
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_CVIF         (_MK_ENUM_CONST(0))
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_MCIF         (_MK_ENUM_CONST(1))
+
+
+// Register RBK_D_DATAOUT_SIZE_1_0
+#define RBK_D_DATAOUT_SIZE_1_0                         (_MK_ADDR_CONST(0x10034))
+#define RBK_D_DATAOUT_SIZE_1_0_SECURE                                      (0x0)
+#define RBK_D_DATAOUT_SIZE_1_0_DUAL                                        (0x0)
+#define RBK_D_DATAOUT_SIZE_1_0_SCR                                           (0)
+#define RBK_D_DATAOUT_SIZE_1_0_WORD_COUNT                                  (0x1)
+#define RBK_D_DATAOUT_SIZE_1_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAOUT_SIZE_1_0_RESET_MASK               (_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAOUT_SIZE_1_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAOUT_SIZE_1_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAOUT_SIZE_1_0_READ_MASK                (_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAOUT_SIZE_1_0_WRITE_MASK               (_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT        (_MK_SHIFT_CONST(0))
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD \
+	(_MK_FIELD_CONST(0x1fff, \
+	RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT))
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_RANGE                      (12:0)
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_WOFFSET                     (0x0)
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT     (_MK_MASK_CONST(0x0))
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1fff))
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAOUT_ADDR_HIGH_0
+#define RBK_D_DAOUT_ADDR_HIGH_0                        (_MK_ADDR_CONST(0x10038))
+#define RBK_D_DAOUT_ADDR_HIGH_0_SECURE                                     (0x0)
+#define RBK_D_DAOUT_ADDR_HIGH_0_DUAL                                       (0x0)
+#define RBK_D_DAOUT_ADDR_HIGH_0_SCR                                          (0)
+#define RBK_D_DAOUT_ADDR_HIGH_0_WORD_COUNT                                 (0x1)
+#define RBK_D_DAOUT_ADDR_HIGH_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_HIGH_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_DAOUT_ADDR_HIGH_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_HIGH_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_HIGH_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_DAOUT_ADDR_HIGH_0_WRITE_MASK          (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT       (_MK_SHIFT_CONST(0))
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT))
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_RANGE                     (31:0)
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_WOFFSET                    (0x0)
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_DEFAULT    (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAOUT_ADDR_LOW_0
+#define RBK_D_DAOUT_ADDR_LOW_0                         (_MK_ADDR_CONST(0x1003c))
+#define RBK_D_DAOUT_ADDR_LOW_0_SECURE                                      (0x0)
+#define RBK_D_DAOUT_ADDR_LOW_0_DUAL                                        (0x0)
+#define RBK_D_DAOUT_ADDR_LOW_0_SCR                                           (0)
+#define RBK_D_DAOUT_ADDR_LOW_0_WORD_COUNT                                  (0x1)
+#define RBK_D_DAOUT_ADDR_LOW_0_RESET_VAL                   (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_LOW_0_RESET_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_ADDR_LOW_0_SW_DEFAULT_VAL              (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_LOW_0_SW_DEFAULT_MASK             (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_LOW_0_READ_MASK            (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_ADDR_LOW_0_WRITE_MASK           (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT         (_MK_SHIFT_CONST(5))
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT))
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_RANGE                       (31:5)
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_WOFFSET                      (0x0)
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_DEFAULT      (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAOUT_LINE_STRIDE_0
+#define RBK_D_DAOUT_LINE_STRIDE_0                      (_MK_ADDR_CONST(0x10040))
+#define RBK_D_DAOUT_LINE_STRIDE_0_SECURE                                   (0x0)
+#define RBK_D_DAOUT_LINE_STRIDE_0_DUAL                                     (0x0)
+#define RBK_D_DAOUT_LINE_STRIDE_0_SCR                                        (0)
+#define RBK_D_DAOUT_LINE_STRIDE_0_WORD_COUNT                               (0x1)
+#define RBK_D_DAOUT_LINE_STRIDE_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT))
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_RANGE                 (31:5)
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_WOFFSET                (0x0)
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_CONTRACT_STRIDE_0_0
+#define RBK_D_CONTRACT_STRIDE_0_0                      (_MK_ADDR_CONST(0x10044))
+#define RBK_D_CONTRACT_STRIDE_0_0_SECURE                                   (0x0)
+#define RBK_D_CONTRACT_STRIDE_0_0_DUAL                                     (0x0)
+#define RBK_D_CONTRACT_STRIDE_0_0_SCR                                        (0)
+#define RBK_D_CONTRACT_STRIDE_0_0_WORD_COUNT                               (0x1)
+#define RBK_D_CONTRACT_STRIDE_0_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_0_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_CONTRACT_STRIDE_0_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_0_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_0_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_CONTRACT_STRIDE_0_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT))
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_RANGE                 (31:5)
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_WOFFSET                (0x0)
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_CONTRACT_STRIDE_1_0
+#define RBK_D_CONTRACT_STRIDE_1_0                      (_MK_ADDR_CONST(0x10048))
+#define RBK_D_CONTRACT_STRIDE_1_0_SECURE                                   (0x0)
+#define RBK_D_CONTRACT_STRIDE_1_0_DUAL                                     (0x0)
+#define RBK_D_CONTRACT_STRIDE_1_0_SCR                                        (0)
+#define RBK_D_CONTRACT_STRIDE_1_0_WORD_COUNT                               (0x1)
+#define RBK_D_CONTRACT_STRIDE_1_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_1_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_CONTRACT_STRIDE_1_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_1_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_1_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_CONTRACT_STRIDE_1_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT))
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_RANGE                 (31:5)
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_WOFFSET                (0x0)
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAOUT_SURF_STRIDE_0
+#define RBK_D_DAOUT_SURF_STRIDE_0                      (_MK_ADDR_CONST(0x1004c))
+#define RBK_D_DAOUT_SURF_STRIDE_0_SECURE                                   (0x0)
+#define RBK_D_DAOUT_SURF_STRIDE_0_DUAL                                     (0x0)
+#define RBK_D_DAOUT_SURF_STRIDE_0_SCR                                        (0)
+#define RBK_D_DAOUT_SURF_STRIDE_0_WORD_COUNT                               (0x1)
+#define RBK_D_DAOUT_SURF_STRIDE_0_RESET_VAL                (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_RESET_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_SW_DEFAULT_VAL           (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_SW_DEFAULT_MASK          (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_READ_MASK         (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_WRITE_MASK        (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT))
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_RANGE                 (31:5)
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_WOFFSET                (0x0)
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DAOUT_PLANAR_STRIDE_0
+#define RBK_D_DAOUT_PLANAR_STRIDE_0                    (_MK_ADDR_CONST(0x10050))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_SECURE                                 (0x0)
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DUAL                                   (0x0)
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_SCR                                      (0)
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_WORD_COUNT                             (0x1)
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_RESET_VAL              (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_RESET_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_SW_DEFAULT_VAL         (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_READ_MASK       (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_WRITE_MASK      (_MK_MASK_CONST(0xffffffe0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT \
+	(_MK_SHIFT_CONST(5))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x7ffffff, \
+	RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_RANGE             (31:5)
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_WOFFSET            (0x0)
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x7ffffff))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_DECONV_STRIDE_0
+#define RBK_D_DECONV_STRIDE_0                          (_MK_ADDR_CONST(0x10054))
+#define RBK_D_DECONV_STRIDE_0_SECURE                                       (0x0)
+#define RBK_D_DECONV_STRIDE_0_DUAL                                         (0x0)
+#define RBK_D_DECONV_STRIDE_0_SCR                                            (0)
+#define RBK_D_DECONV_STRIDE_0_WORD_COUNT                                   (0x1)
+#define RBK_D_DECONV_STRIDE_0_RESET_VAL                    (_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_RESET_MASK              (_MK_MASK_CONST(0x1f001f))
+#define RBK_D_DECONV_STRIDE_0_SW_DEFAULT_VAL               (_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_SW_DEFAULT_MASK              (_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_READ_MASK               (_MK_MASK_CONST(0x1f001f))
+#define RBK_D_DECONV_STRIDE_0_WRITE_MASK              (_MK_MASK_CONST(0x1f001f))
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT         (_MK_SHIFT_CONST(0))
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT))
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_RANGE                        (4:0)
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_WOFFSET                      (0x0)
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT        (_MK_SHIFT_CONST(16))
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_FIELD \
+	(_MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT))
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_RANGE                      (20:16)
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_WOFFSET                      (0x0)
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_DEFAULT      (_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x1f))
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_PERF_ENABLE_0
+#define RBK_D_PERF_ENABLE_0                            (_MK_ADDR_CONST(0x10058))
+#define RBK_D_PERF_ENABLE_0_SECURE                                         (0x0)
+#define RBK_D_PERF_ENABLE_0_DUAL                                           (0x0)
+#define RBK_D_PERF_ENABLE_0_SCR                                              (0)
+#define RBK_D_PERF_ENABLE_0_WORD_COUNT                                     (0x1)
+#define RBK_D_PERF_ENABLE_0_RESET_VAL                      (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_ENABLE_0_RESET_MASK                     (_MK_MASK_CONST(0x1))
+#define RBK_D_PERF_ENABLE_0_SW_DEFAULT_VAL                 (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_ENABLE_0_SW_DEFAULT_MASK                (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_ENABLE_0_READ_MASK                      (_MK_MASK_CONST(0x1))
+#define RBK_D_PERF_ENABLE_0_WRITE_MASK                     (_MK_MASK_CONST(0x1))
+#define RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT                   (_MK_SHIFT_CONST(0))
+#define RBK_D_PERF_ENABLE_0_PERF_EN_FIELD \
+	(_MK_FIELD_CONST(0x1, RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT))
+#define RBK_D_PERF_ENABLE_0_PERF_EN_RANGE                                  (0:0)
+#define RBK_D_PERF_ENABLE_0_PERF_EN_WOFFSET                                (0x0)
+#define RBK_D_PERF_ENABLE_0_PERF_EN_DEFAULT                (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_ENABLE_0_PERF_EN_DEFAULT_MASK           (_MK_MASK_CONST(0x1))
+#define RBK_D_PERF_ENABLE_0_PERF_EN_SW_DEFAULT             (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_ENABLE_0_PERF_EN_SW_DEFAULT_MASK        (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_ENABLE_0_PERF_EN_PARITY_PROTECTION      (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_ENABLE_0_PERF_EN_PLATFORM_DEPENDENT     (_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_PERF_READ_STALL_0
+#define RBK_D_PERF_READ_STALL_0                        (_MK_ADDR_CONST(0x1005c))
+#define RBK_D_PERF_READ_STALL_0_SECURE                                     (0x0)
+#define RBK_D_PERF_READ_STALL_0_DUAL                                       (0x0)
+#define RBK_D_PERF_READ_STALL_0_SCR                                          (0)
+#define RBK_D_PERF_READ_STALL_0_WORD_COUNT                                 (0x1)
+#define RBK_D_PERF_READ_STALL_0_RESET_VAL                  (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_READ_STALL_0_RESET_MASK          (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_PERF_READ_STALL_0_SW_DEFAULT_VAL             (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_READ_STALL_0_SW_DEFAULT_MASK            (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_READ_STALL_0_READ_MASK           (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_PERF_READ_STALL_0_WRITE_MASK                 (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT          (_MK_SHIFT_CONST(0))
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT))
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_RANGE                        (31:0)
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_WOFFSET                       (0x0)
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_DEFAULT       (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SW_DEFAULT    (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+// Register RBK_D_PERF_WRITE_STALL_0
+#define RBK_D_PERF_WRITE_STALL_0                       (_MK_ADDR_CONST(0x10060))
+#define RBK_D_PERF_WRITE_STALL_0_SECURE                                    (0x0)
+#define RBK_D_PERF_WRITE_STALL_0_DUAL                                      (0x0)
+#define RBK_D_PERF_WRITE_STALL_0_SCR                                         (0)
+#define RBK_D_PERF_WRITE_STALL_0_WORD_COUNT                                (0x1)
+#define RBK_D_PERF_WRITE_STALL_0_RESET_VAL                 (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_WRITE_STALL_0_RESET_MASK         (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_PERF_WRITE_STALL_0_SW_DEFAULT_VAL            (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_WRITE_STALL_0_SW_DEFAULT_MASK           (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_WRITE_STALL_0_READ_MASK          (_MK_MASK_CONST(0xffffffff))
+#define RBK_D_PERF_WRITE_STALL_0_WRITE_MASK                (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT         (_MK_SHIFT_CONST(0))
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_FIELD \
+	(_MK_FIELD_CONST(0xffffffff, \
+	RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT))
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_RANGE                       (31:0)
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_WOFFSET                      (0x0)
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_DEFAULT      (_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_DEFAULT_MASK \
+	(_MK_MASK_CONST(0xffffffff))
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SW_DEFAULT \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SW_DEFAULT_MASK \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_PARITY_PROTECTION \
+	(_MK_MASK_CONST(0x0))
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_PLATFORM_DEPENDENT \
+	(_MK_MASK_CONST(0x1))
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARREGS(_op_) \
+(_op_(GLB_S_NVDLA_HW_VERSION_0) \
+_op_(GLB_S_INTR_MASK_0) \
+_op_(GLB_S_INTR_SET_0) \
+_op_(GLB_S_INTR_STATUS_0) \
+_op_(MCIF_CFG_RD_WEIGHT_0_0) \
+_op_(MCIF_CFG_RD_WEIGHT_1_0) \
+_op_(MCIF_CFG_RD_WEIGHT_2_0) \
+_op_(MCIF_CFG_WR_WEIGHT_0_0) \
+_op_(MCIF_CFG_WR_WEIGHT_1_0) \
+_op_(MCIF_CFG_OUTSTANDING_CNT_0) \
+_op_(MCIF_STATUS_0) \
+_op_(CVIF_CFG_RD_WEIGHT_0_0) \
+_op_(CVIF_CFG_RD_WEIGHT_1_0) \
+_op_(CVIF_CFG_RD_WEIGHT_2_0) \
+_op_(CVIF_CFG_WR_WEIGHT_0_0) \
+_op_(CVIF_CFG_WR_WEIGHT_1_0) \
+_op_(CVIF_CFG_OUTSTANDING_CNT_0) \
+_op_(CVIF_STATUS_0) \
+_op_(BDMA_CFG_SRC_ADDR_LOW_0) \
+_op_(BDMA_CFG_SRC_ADDR_HIGH_0) \
+_op_(BDMA_CFG_DST_ADDR_LOW_0) \
+_op_(BDMA_CFG_DST_ADDR_HIGH_0) \
+_op_(BDMA_CFG_LINE_0) \
+_op_(BDMA_CFG_CMD_0) \
+_op_(BDMA_CFG_LINE_REPEAT_0) \
+_op_(BDMA_CFG_SRC_LINE_0) \
+_op_(BDMA_CFG_DST_LINE_0) \
+_op_(BDMA_CFG_SURF_REPEAT_0) \
+_op_(BDMA_CFG_SRC_SURF_0) \
+_op_(BDMA_CFG_DST_SURF_0) \
+_op_(BDMA_CFG_OP_0) \
+_op_(BDMA_CFG_LAUNCH0_0) \
+_op_(BDMA_CFG_LAUNCH1_0) \
+_op_(BDMA_CFG_STATUS_0) \
+_op_(BDMA_STATUS_0) \
+_op_(BDMA_STATUS_GRP0_READ_STALL_0) \
+_op_(BDMA_STATUS_GRP0_WRITE_STALL_0) \
+_op_(BDMA_STATUS_GRP1_READ_STALL_0) \
+_op_(BDMA_STATUS_GRP1_WRITE_STALL_0) \
+_op_(CDMA_S_STATUS_0) \
+_op_(CDMA_S_POINTER_0) \
+_op_(CDMA_S_ARBITER_0) \
+_op_(CDMA_S_CBUF_FLUSH_STATUS_0) \
+_op_(CDMA_D_OP_ENABLE_0) \
+_op_(CDMA_D_MISC_CFG_0) \
+_op_(CDMA_D_DATAIN_FORMAT_0) \
+_op_(CDMA_D_DATAIN_SIZE_0_0) \
+_op_(CDMA_D_DATAIN_SIZE_1_0) \
+_op_(CDMA_D_DATAIN_SIZE_EXT_0_0) \
+_op_(CDMA_D_PIXEL_OFFSET_0) \
+_op_(CDMA_D_DAIN_RAM_TYPE_0) \
+_op_(CDMA_D_DAIN_ADDR_HIGH_0_0) \
+_op_(CDMA_D_DAIN_ADDR_LOW_0_0) \
+_op_(CDMA_D_DAIN_ADDR_HIGH_1_0) \
+_op_(CDMA_D_DAIN_ADDR_LOW_1_0) \
+_op_(CDMA_D_LINE_STRIDE_0) \
+_op_(CDMA_D_LINE_UV_STRIDE_0) \
+_op_(CDMA_D_SURF_STRIDE_0) \
+_op_(CDMA_D_DAIN_MAP_0) \
+_op_(CDMA_D_RESERVED_X_CFG_0) \
+_op_(CDMA_D_RESERVED_Y_CFG_0) \
+_op_(CDMA_D_BATCH_NUMBER_0) \
+_op_(CDMA_D_BATCH_STRIDE_0) \
+_op_(CDMA_D_ENTRY_PER_SLICE_0) \
+_op_(CDMA_D_FETCH_GRAIN_0) \
+_op_(CDMA_D_WEIGHT_FORMAT_0) \
+_op_(CDMA_D_WEIGHT_SIZE_0_0) \
+_op_(CDMA_D_WEIGHT_SIZE_1_0) \
+_op_(CDMA_D_WEIGHT_RAM_TYPE_0) \
+_op_(CDMA_D_WEIGHT_ADDR_HIGH_0) \
+_op_(CDMA_D_WEIGHT_ADDR_LOW_0) \
+_op_(CDMA_D_WEIGHT_BYTES_0) \
+_op_(CDMA_D_WGS_ADDR_HIGH_0) \
+_op_(CDMA_D_WGS_ADDR_LOW_0) \
+_op_(CDMA_D_WMB_ADDR_HIGH_0) \
+_op_(CDMA_D_WMB_ADDR_LOW_0) \
+_op_(CDMA_D_WMB_BYTES_0) \
+_op_(CDMA_D_MEAN_FORMAT_0) \
+_op_(CDMA_D_MEAN_GLOBAL_0_0) \
+_op_(CDMA_D_MEAN_GLOBAL_1_0) \
+_op_(CDMA_D_CVT_CFG_0) \
+_op_(CDMA_D_CVT_OFFSET_0) \
+_op_(CDMA_D_CVT_SCALE_0) \
+_op_(CDMA_D_CONV_STRIDE_0) \
+_op_(CDMA_D_ZERO_PADDING_0) \
+_op_(CDMA_D_ZERO_PADDING_VALUE_0) \
+_op_(CDMA_D_BANK_0) \
+_op_(CDMA_D_NAN_FLUSH_TO_ZERO_0) \
+_op_(CDMA_D_NAN_INPUT_DATA_NUM_0) \
+_op_(CDMA_D_NAN_INPUT_WEIGHT_NUM_0) \
+_op_(CDMA_D_INF_INPUT_DATA_NUM_0) \
+_op_(CDMA_D_INF_INPUT_WEIGHT_NUM_0) \
+_op_(CDMA_D_PERF_ENABLE_0) \
+_op_(CDMA_D_PERF_DAT_READ_STALL_0) \
+_op_(CDMA_D_PERF_WT_READ_STALL_0) \
+_op_(CDMA_D_PERF_DAT_READ_LATENCY_0) \
+_op_(CDMA_D_PERF_WT_READ_LATENCY_0) \
+_op_(CDMA_D_CYA_0) \
+_op_(CSC_S_STATUS_0) \
+_op_(CSC_S_POINTER_0) \
+_op_(CSC_D_OP_ENABLE_0) \
+_op_(CSC_D_MISC_CFG_0) \
+_op_(CSC_D_DATAIN_FORMAT_0) \
+_op_(CSC_D_DATAIN_SIZE_EXT_0_0) \
+_op_(CSC_D_DATAIN_SIZE_EXT_1_0) \
+_op_(CSC_D_BATCH_NUMBER_0) \
+_op_(CSC_D_POST_Y_EXTENSION_0) \
+_op_(CSC_D_ENTRY_PER_SLICE_0) \
+_op_(CSC_D_WEIGHT_FORMAT_0) \
+_op_(CSC_D_WEIGHT_SIZE_EXT_0_0) \
+_op_(CSC_D_WEIGHT_SIZE_EXT_1_0) \
+_op_(CSC_D_WEIGHT_BYTES_0) \
+_op_(CSC_D_WMB_BYTES_0) \
+_op_(CSC_D_DATAOUT_SIZE_0_0) \
+_op_(CSC_D_DATAOUT_SIZE_1_0) \
+_op_(CSC_D_ATOMICS_0) \
+_op_(CSC_D_RELEASE_0) \
+_op_(CSC_D_CONV_STRIDE_EXT_0) \
+_op_(CSC_D_DILATION_EXT_0) \
+_op_(CSC_D_ZERO_PADDING_0) \
+_op_(CSC_D_ZERO_PADDING_VALUE_0) \
+_op_(CSC_D_BANK_0) \
+_op_(CSC_D_PRA_CFG_0) \
+_op_(CSC_D_CYA_0) \
+_op_(CMAC_A_S_STATUS_0) \
+_op_(CMAC_A_S_POINTER_0) \
+_op_(CMAC_A_D_OP_ENABLE_0) \
+_op_(CMAC_A_D_MISC_CFG_0) \
+_op_(CMAC_B_S_STATUS_0) \
+_op_(CMAC_B_S_POINTER_0) \
+_op_(CMAC_B_D_OP_ENABLE_0) \
+_op_(CMAC_B_D_MISC_CFG_0) \
+_op_(CACC_S_STATUS_0) \
+_op_(CACC_S_POINTER_0) \
+_op_(CACC_D_OP_ENABLE_0) \
+_op_(CACC_D_MISC_CFG_0) \
+_op_(CACC_D_DATAOUT_SIZE_0_0) \
+_op_(CACC_D_DATAOUT_SIZE_1_0) \
+_op_(CACC_D_DATAOUT_ADDR_0) \
+_op_(CACC_D_BATCH_NUMBER_0) \
+_op_(CACC_D_LINE_STRIDE_0) \
+_op_(CACC_D_SURF_STRIDE_0) \
+_op_(CACC_D_DATAOUT_MAP_0) \
+_op_(CACC_D_CLIP_CFG_0) \
+_op_(CACC_D_OUT_SATURATION_0) \
+_op_(CACC_D_CYA_0) \
+_op_(SDP_RDMA_S_STATUS_0) \
+_op_(SDP_RDMA_S_POINTER_0) \
+_op_(SDP_RDMA_D_OP_ENABLE_0) \
+_op_(SDP_RDMA_D_DATA_CUBE_WIDTH_0) \
+_op_(SDP_RDMA_D_DATA_CUBE_HEIGHT_0) \
+_op_(SDP_RDMA_D_DATA_CUBE_CHANNEL_0) \
+_op_(SDP_RDMA_D_SRC_BASE_ADDR_LOW_0) \
+_op_(SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0) \
+_op_(SDP_RDMA_D_SRC_LINE_STRIDE_0) \
+_op_(SDP_RDMA_D_SRC_SURFACE_STRIDE_0) \
+_op_(SDP_RDMA_D_BRDMA_CFG_0) \
+_op_(SDP_RDMA_D_BS_BASE_ADDR_LOW_0) \
+_op_(SDP_RDMA_D_BS_BASE_ADDR_HIGH_0) \
+_op_(SDP_RDMA_D_BS_LINE_STRIDE_0) \
+_op_(SDP_RDMA_D_BS_SURFACE_STRIDE_0) \
+_op_(SDP_RDMA_D_BS_BATCH_STRIDE_0) \
+_op_(SDP_RDMA_D_NRDMA_CFG_0) \
+_op_(SDP_RDMA_D_BN_BASE_ADDR_LOW_0) \
+_op_(SDP_RDMA_D_BN_BASE_ADDR_HIGH_0) \
+_op_(SDP_RDMA_D_BN_LINE_STRIDE_0) \
+_op_(SDP_RDMA_D_BN_SURFACE_STRIDE_0) \
+_op_(SDP_RDMA_D_BN_BATCH_STRIDE_0) \
+_op_(SDP_RDMA_D_ERDMA_CFG_0) \
+_op_(SDP_RDMA_D_EW_BASE_ADDR_LOW_0) \
+_op_(SDP_RDMA_D_EW_BASE_ADDR_HIGH_0) \
+_op_(SDP_RDMA_D_EW_LINE_STRIDE_0) \
+_op_(SDP_RDMA_D_EW_SURFACE_STRIDE_0) \
+_op_(SDP_RDMA_D_EW_BATCH_STRIDE_0) \
+_op_(SDP_RDMA_D_FEATURE_MODE_CFG_0) \
+_op_(SDP_RDMA_D_SRC_DMA_CFG_0) \
+_op_(SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0) \
+_op_(SDP_RDMA_D_STATUS_INF_INPUT_NUM_0) \
+_op_(SDP_RDMA_D_PERF_ENABLE_0) \
+_op_(SDP_RDMA_D_PERF_MRDMA_READ_STALL_0) \
+_op_(SDP_RDMA_D_PERF_BRDMA_READ_STALL_0) \
+_op_(SDP_RDMA_D_PERF_NRDMA_READ_STALL_0) \
+_op_(SDP_RDMA_D_PERF_ERDMA_READ_STALL_0) \
+_op_(SDP_S_STATUS_0) \
+_op_(SDP_S_POINTER_0) \
+_op_(SDP_S_LUT_ACCESS_CFG_0) \
+_op_(SDP_S_LUT_ACCESS_DATA_0) \
+_op_(SDP_S_LUT_CFG_0) \
+_op_(SDP_S_LUT_INFO_0) \
+_op_(SDP_S_LUT_LE_START_0) \
+_op_(SDP_S_LUT_LE_END_0) \
+_op_(SDP_S_LUT_LO_START_0) \
+_op_(SDP_S_LUT_LO_END_0) \
+_op_(SDP_S_LUT_LE_SLOPE_SCALE_0) \
+_op_(SDP_S_LUT_LE_SLOPE_SHIFT_0) \
+_op_(SDP_S_LUT_LO_SLOPE_SCALE_0) \
+_op_(SDP_S_LUT_LO_SLOPE_SHIFT_0) \
+_op_(SDP_D_OP_ENABLE_0) \
+_op_(SDP_D_DATA_CUBE_WIDTH_0) \
+_op_(SDP_D_DATA_CUBE_HEIGHT_0) \
+_op_(SDP_D_DATA_CUBE_CHANNEL_0) \
+_op_(SDP_D_DST_BASE_ADDR_LOW_0) \
+_op_(SDP_D_DST_BASE_ADDR_HIGH_0) \
+_op_(SDP_D_DST_LINE_STRIDE_0) \
+_op_(SDP_D_DST_SURFACE_STRIDE_0) \
+_op_(SDP_D_DP_BS_CFG_0) \
+_op_(SDP_D_DP_BS_ALU_CFG_0) \
+_op_(SDP_D_DP_BS_ALU_SRC_VALUE_0) \
+_op_(SDP_D_DP_BS_MUL_CFG_0) \
+_op_(SDP_D_DP_BS_MUL_SRC_VALUE_0) \
+_op_(SDP_D_DP_BN_CFG_0) \
+_op_(SDP_D_DP_BN_ALU_CFG_0) \
+_op_(SDP_D_DP_BN_ALU_SRC_VALUE_0) \
+_op_(SDP_D_DP_BN_MUL_CFG_0) \
+_op_(SDP_D_DP_BN_MUL_SRC_VALUE_0) \
+_op_(SDP_D_DP_EW_CFG_0) \
+_op_(SDP_D_DP_EW_ALU_CFG_0) \
+_op_(SDP_D_DP_EW_ALU_SRC_VALUE_0) \
+_op_(SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0) \
+_op_(SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0) \
+_op_(SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0) \
+_op_(SDP_D_DP_EW_MUL_CFG_0) \
+_op_(SDP_D_DP_EW_MUL_SRC_VALUE_0) \
+_op_(SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0) \
+_op_(SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0) \
+_op_(SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0) \
+_op_(SDP_D_DP_EW_TRUNCATE_VALUE_0) \
+_op_(SDP_D_FEATURE_MODE_CFG_0) \
+_op_(SDP_D_DST_DMA_CFG_0) \
+_op_(SDP_D_DST_BATCH_STRIDE_0) \
+_op_(SDP_D_DATA_FORMAT_0) \
+_op_(SDP_D_CVT_OFFSET_0) \
+_op_(SDP_D_CVT_SCALE_0) \
+_op_(SDP_D_CVT_SHIFT_0) \
+_op_(SDP_D_STATUS_0) \
+_op_(SDP_D_STATUS_NAN_INPUT_NUM_0) \
+_op_(SDP_D_STATUS_INF_INPUT_NUM_0) \
+_op_(SDP_D_STATUS_NAN_OUTPUT_NUM_0) \
+_op_(SDP_D_PERF_ENABLE_0) \
+_op_(SDP_D_PERF_WDMA_WRITE_STALL_0) \
+_op_(SDP_D_PERF_LUT_UFLOW_0) \
+_op_(SDP_D_PERF_LUT_OFLOW_0) \
+_op_(SDP_D_PERF_OUT_SATURATION_0) \
+_op_(SDP_D_PERF_LUT_HYBRID_0) \
+_op_(SDP_D_PERF_LUT_LE_HIT_0) \
+_op_(SDP_D_PERF_LUT_LO_HIT_0) \
+_op_(PDP_RDMA_S_STATUS_0) \
+_op_(PDP_RDMA_S_POINTER_0) \
+_op_(PDP_RDMA_D_OP_ENABLE_0) \
+_op_(PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0) \
+_op_(PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0) \
+_op_(PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0) \
+_op_(PDP_RDMA_D_FLYING_MODE_0) \
+_op_(PDP_RDMA_D_SRC_BASE_ADDR_LOW_0) \
+_op_(PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0) \
+_op_(PDP_RDMA_D_SRC_LINE_STRIDE_0) \
+_op_(PDP_RDMA_D_SRC_SURFACE_STRIDE_0) \
+_op_(PDP_RDMA_D_SRC_RAM_CFG_0) \
+_op_(PDP_RDMA_D_DATA_FORMAT_0) \
+_op_(PDP_RDMA_D_OPERATION_MODE_CFG_0) \
+_op_(PDP_RDMA_D_POOLING_KERNEL_CFG_0) \
+_op_(PDP_RDMA_D_POOLING_PADDING_CFG_0) \
+_op_(PDP_RDMA_D_PARTIAL_WIDTH_IN_0) \
+_op_(PDP_RDMA_D_PERF_ENABLE_0) \
+_op_(PDP_RDMA_D_PERF_READ_STALL_0) \
+_op_(PDP_RDMA_D_CYA_0) \
+_op_(PDP_S_STATUS_0) \
+_op_(PDP_S_POINTER_0) \
+_op_(PDP_D_OP_ENABLE_0) \
+_op_(PDP_D_DATA_CUBE_IN_WIDTH_0) \
+_op_(PDP_D_DATA_CUBE_IN_HEIGHT_0) \
+_op_(PDP_D_DATA_CUBE_IN_CHANNEL_0) \
+_op_(PDP_D_DATA_CUBE_OUT_WIDTH_0) \
+_op_(PDP_D_DATA_CUBE_OUT_HEIGHT_0) \
+_op_(PDP_D_DATA_CUBE_OUT_CHANNEL_0) \
+_op_(PDP_D_OPERATION_MODE_CFG_0) \
+_op_(PDP_D_NAN_FLUSH_TO_ZERO_0) \
+_op_(PDP_D_PARTIAL_WIDTH_IN_0) \
+_op_(PDP_D_PARTIAL_WIDTH_OUT_0) \
+_op_(PDP_D_POOLING_KERNEL_CFG_0) \
+_op_(PDP_D_RECIP_KERNEL_WIDTH_0) \
+_op_(PDP_D_RECIP_KERNEL_HEIGHT_0) \
+_op_(PDP_D_POOLING_PADDING_CFG_0) \
+_op_(PDP_D_POOLING_PADDING_VALUE_1_CFG_0) \
+_op_(PDP_D_POOLING_PADDING_VALUE_2_CFG_0) \
+_op_(PDP_D_POOLING_PADDING_VALUE_3_CFG_0) \
+_op_(PDP_D_POOLING_PADDING_VALUE_4_CFG_0) \
+_op_(PDP_D_POOLING_PADDING_VALUE_5_CFG_0) \
+_op_(PDP_D_POOLING_PADDING_VALUE_6_CFG_0) \
+_op_(PDP_D_POOLING_PADDING_VALUE_7_CFG_0) \
+_op_(PDP_D_SRC_BASE_ADDR_LOW_0) \
+_op_(PDP_D_SRC_BASE_ADDR_HIGH_0) \
+_op_(PDP_D_SRC_LINE_STRIDE_0) \
+_op_(PDP_D_SRC_SURFACE_STRIDE_0) \
+_op_(PDP_D_DST_BASE_ADDR_LOW_0) \
+_op_(PDP_D_DST_BASE_ADDR_HIGH_0) \
+_op_(PDP_D_DST_LINE_STRIDE_0) \
+_op_(PDP_D_DST_SURFACE_STRIDE_0) \
+_op_(PDP_D_DST_RAM_CFG_0) \
+_op_(PDP_D_DATA_FORMAT_0) \
+_op_(PDP_D_INF_INPUT_NUM_0) \
+_op_(PDP_D_NAN_INPUT_NUM_0) \
+_op_(PDP_D_NAN_OUTPUT_NUM_0) \
+_op_(PDP_D_PERF_ENABLE_0) \
+_op_(PDP_D_PERF_WRITE_STALL_0) \
+_op_(PDP_D_CYA_0) \
+_op_(CDP_RDMA_S_STATUS_0) \
+_op_(CDP_RDMA_S_POINTER_0) \
+_op_(CDP_RDMA_D_OP_ENABLE_0) \
+_op_(CDP_RDMA_D_DATA_CUBE_WIDTH_0) \
+_op_(CDP_RDMA_D_DATA_CUBE_HEIGHT_0) \
+_op_(CDP_RDMA_D_DATA_CUBE_CHANNEL_0) \
+_op_(CDP_RDMA_D_SRC_BASE_ADDR_LOW_0) \
+_op_(CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0) \
+_op_(CDP_RDMA_D_SRC_LINE_STRIDE_0) \
+_op_(CDP_RDMA_D_SRC_SURFACE_STRIDE_0) \
+_op_(CDP_RDMA_D_SRC_DMA_CFG_0) \
+_op_(CDP_RDMA_D_SRC_COMPRESSION_EN_0) \
+_op_(CDP_RDMA_D_OPERATION_MODE_0) \
+_op_(CDP_RDMA_D_DATA_FORMAT_0) \
+_op_(CDP_RDMA_D_PERF_ENABLE_0) \
+_op_(CDP_RDMA_D_PERF_READ_STALL_0) \
+_op_(CDP_RDMA_D_CYA_0) \
+_op_(CDP_S_STATUS_0) \
+_op_(CDP_S_POINTER_0) \
+_op_(CDP_S_LUT_ACCESS_CFG_0) \
+_op_(CDP_S_LUT_ACCESS_DATA_0) \
+_op_(CDP_S_LUT_CFG_0) \
+_op_(CDP_S_LUT_INFO_0) \
+_op_(CDP_S_LUT_LE_START_LOW_0) \
+_op_(CDP_S_LUT_LE_START_HIGH_0) \
+_op_(CDP_S_LUT_LE_END_LOW_0) \
+_op_(CDP_S_LUT_LE_END_HIGH_0) \
+_op_(CDP_S_LUT_LO_START_LOW_0) \
+_op_(CDP_S_LUT_LO_START_HIGH_0) \
+_op_(CDP_S_LUT_LO_END_LOW_0) \
+_op_(CDP_S_LUT_LO_END_HIGH_0) \
+_op_(CDP_S_LUT_LE_SLOPE_SCALE_0) \
+_op_(CDP_S_LUT_LE_SLOPE_SHIFT_0) \
+_op_(CDP_S_LUT_LO_SLOPE_SCALE_0) \
+_op_(CDP_S_LUT_LO_SLOPE_SHIFT_0) \
+_op_(CDP_D_OP_ENABLE_0) \
+_op_(CDP_D_FUNC_BYPASS_0) \
+_op_(CDP_D_DST_BASE_ADDR_LOW_0) \
+_op_(CDP_D_DST_BASE_ADDR_HIGH_0) \
+_op_(CDP_D_DST_LINE_STRIDE_0) \
+_op_(CDP_D_DST_SURFACE_STRIDE_0) \
+_op_(CDP_D_DST_DMA_CFG_0) \
+_op_(CDP_D_DST_COMPRESSION_EN_0) \
+_op_(CDP_D_DATA_FORMAT_0) \
+_op_(CDP_D_NAN_FLUSH_TO_ZERO_0) \
+_op_(CDP_D_LRN_CFG_0) \
+_op_(CDP_D_DATIN_OFFSET_0) \
+_op_(CDP_D_DATIN_SCALE_0) \
+_op_(CDP_D_DATIN_SHIFTER_0) \
+_op_(CDP_D_DATOUT_OFFSET_0) \
+_op_(CDP_D_DATOUT_SCALE_0) \
+_op_(CDP_D_DATOUT_SHIFTER_0) \
+_op_(CDP_D_NAN_INPUT_NUM_0) \
+_op_(CDP_D_INF_INPUT_NUM_0) \
+_op_(CDP_D_NAN_OUTPUT_NUM_0) \
+_op_(CDP_D_OUT_SATURATION_0) \
+_op_(CDP_D_PERF_ENABLE_0) \
+_op_(CDP_D_PERF_WRITE_STALL_0) \
+_op_(CDP_D_PERF_LUT_UFLOW_0) \
+_op_(CDP_D_PERF_LUT_OFLOW_0) \
+_op_(CDP_D_PERF_LUT_HYBRID_0) \
+_op_(CDP_D_PERF_LUT_LE_HIT_0) \
+_op_(CDP_D_PERF_LUT_LO_HIT_0) \
+_op_(CDP_D_CYA_0) \
+_op_(RBK_S_STATUS_0) \
+_op_(RBK_S_POINTER_0) \
+_op_(RBK_D_OP_ENABLE_0) \
+_op_(RBK_D_MISC_CFG_0) \
+_op_(RBK_D_DAIN_RAM_TYPE_0) \
+_op_(RBK_D_DATAIN_SIZE_0_0) \
+_op_(RBK_D_DATAIN_SIZE_1_0) \
+_op_(RBK_D_DAIN_ADDR_HIGH_0) \
+_op_(RBK_D_DAIN_ADDR_LOW_0) \
+_op_(RBK_D_DAIN_LINE_STRIDE_0) \
+_op_(RBK_D_DAIN_SURF_STRIDE_0) \
+_op_(RBK_D_DAIN_PLANAR_STRIDE_0) \
+_op_(RBK_D_DAOUT_RAM_TYPE_0) \
+_op_(RBK_D_DATAOUT_SIZE_1_0) \
+_op_(RBK_D_DAOUT_ADDR_HIGH_0) \
+_op_(RBK_D_DAOUT_ADDR_LOW_0) \
+_op_(RBK_D_DAOUT_LINE_STRIDE_0) \
+_op_(RBK_D_CONTRACT_STRIDE_0_0) \
+_op_(RBK_D_CONTRACT_STRIDE_1_0) \
+_op_(RBK_D_DAOUT_SURF_STRIDE_0) \
+_op_(RBK_D_DAOUT_PLANAR_STRIDE_0) \
+_op_(RBK_D_DECONV_STRIDE_0) \
+_op_(RBK_D_PERF_ENABLE_0) \
+_op_(RBK_D_PERF_READ_STALL_0) \
+_op_(RBK_D_PERF_WRITE_STALL_0))
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_NVDLA_GLB                                      (0x00000000)
+#define BASE_ADDRESS_NVDLA_MCIF                                     (0x00002000)
+#define BASE_ADDRESS_NVDLA_CVIF                                     (0x00003000)
+#define BASE_ADDRESS_NVDLA_BDMA                                     (0x00004000)
+#define BASE_ADDRESS_NVDLA_CDMA                                     (0x00005000)
+#define BASE_ADDRESS_NVDLA_CSC                                      (0x00006000)
+#define BASE_ADDRESS_NVDLA_CMAC_A                                   (0x00007000)
+#define BASE_ADDRESS_NVDLA_CMAC_B                                   (0x00008000)
+#define BASE_ADDRESS_NVDLA_CACC                                     (0x00009000)
+#define BASE_ADDRESS_NVDLA_SDP_RDMA                                 (0x0000a000)
+#define BASE_ADDRESS_NVDLA_SDP                                      (0x0000b000)
+#define BASE_ADDRESS_NVDLA_PDP_RDMA                                 (0x0000c000)
+#define BASE_ADDRESS_NVDLA_PDP                                      (0x0000d000)
+#define BASE_ADDRESS_NVDLA_CDP_RDMA                                 (0x0000e000)
+#define BASE_ADDRESS_NVDLA_CDP                                      (0x0000f000)
+#define BASE_ADDRESS_NVDLA_RBK                                      (0x00010000)
+
+//
+// ARNVDLA REGISTER BANKS
+//
+
+#define GLB0_FIRST_REG                                                  (0x0000)
+#define GLB0_LAST_REG                                                   (0x000c)
+#define MCIF0_FIRST_REG                                                 (0x2000)
+#define MCIF0_LAST_REG                                                  (0x2018)
+#define CVIF0_FIRST_REG                                                 (0x3000)
+#define CVIF0_LAST_REG                                                  (0x3018)
+#define BDMA0_FIRST_REG                                                 (0x4000)
+#define BDMA0_LAST_REG                                                  (0x4050)
+#define CDMA0_FIRST_REG                                                 (0x5000)
+#define CDMA0_LAST_REG                                                  (0x50e8)
+#define CSC0_FIRST_REG                                                  (0x6000)
+#define CSC0_LAST_REG                                                   (0x6064)
+#define CMAC_A0_FIRST_REG                                               (0x7000)
+#define CMAC_A0_LAST_REG                                                (0x700c)
+#define CMAC_B0_FIRST_REG                                               (0x8000)
+#define CMAC_B0_LAST_REG                                                (0x800c)
+#define CACC0_FIRST_REG                                                 (0x9000)
+#define CACC0_LAST_REG                                                  (0x9034)
+#define SDP_RDMA0_FIRST_REG                                             (0xa000)
+#define SDP_RDMA0_LAST_REG                                              (0xa090)
+#define SDP0_FIRST_REG                                                  (0xb000)
+#define SDP0_LAST_REG                                                   (0xb0f8)
+#define PDP_RDMA0_FIRST_REG                                             (0xc000)
+#define PDP_RDMA0_LAST_REG                                              (0xc04c)
+#define PDP0_FIRST_REG                                                  (0xd000)
+#define PDP0_LAST_REG                                                   (0xd09c)
+#define CDP_RDMA0_FIRST_REG                                             (0xe000)
+#define CDP_RDMA0_LAST_REG                                              (0xe040)
+#define CDP0_FIRST_REG                                                  (0xf000)
+#define CDP0_LAST_REG                                                   (0xf0b8)
+#define RBK0_FIRST_REG                                                 (0x10000)
+#define RBK0_LAST_REG                                                  (0x10060)
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+#define _MK_SHIFT_CONST(_constant_)                                 (_constant_)
+#endif
+#ifndef _MK_MASK_CONST
+#define _MK_MASK_CONST(_constant_)                                  (_constant_)
+#endif
+#ifndef _MK_ENUM_CONST
+#define _MK_ENUM_CONST(_constant_)                          ((_constant_ ## UL))
+#endif
+#ifndef _MK_ADDR_CONST
+#define _MK_ADDR_CONST(_constant_)                                  (_constant_)
+#endif
+#ifndef _MK_FIELD_CONST
+#define _MK_FIELD_CONST(_mask_, _shift_) \
+	((_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)))
+#endif
+
+#endif // ifndef ___ARH_INC_
diff --git a/drivers/nvdla/include/opendla_small.h b/drivers/nvdla/include/opendla_small.h
new file mode 100644
index 000000000000..dfcb3b0f847f
--- /dev/null
+++ b/drivers/nvdla/include/opendla_small.h
@@ -0,0 +1,6433 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __OPENDLA_SMALL_H_
+#define __OPENDLA_SMALL_H_
+
+// Register NVDLA_CFGROM_CFGROM_HW_VERSION_0
+#define NVDLA_CFGROM_CFGROM_HW_VERSION_0			_MK_ADDR_CONST(0x0)
+#define NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_GLB_DESC_0
+#define NVDLA_CFGROM_CFGROM_GLB_DESC_0			_MK_ADDR_CONST(0x4)
+#define NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CIF_DESC_0
+#define NVDLA_CFGROM_CFGROM_CIF_DESC_0			_MK_ADDR_CONST(0x8)
+#define NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0			_MK_ADDR_CONST(0xc)
+#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0			_MK_ADDR_CONST(0x10)
+#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0			_MK_ADDR_CONST(0x14)
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0			_MK_ADDR_CONST(0x18)
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0			_MK_ADDR_CONST(0x1c)
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_FIELD			_MK_FIELD_CONST(0x7ffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0			_MK_ADDR_CONST(0x20)
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_FIELD			_MK_FIELD_CONST(0x7ffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_DESC_0
+#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0			_MK_ADDR_CONST(0x24)
+#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0			_MK_ADDR_CONST(0x28)
+#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0			_MK_ADDR_CONST(0x2c)
+#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0			_MK_ADDR_CONST(0x30)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0			_MK_ADDR_CONST(0x34)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0			_MK_ADDR_CONST(0x38)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0			_MK_ADDR_CONST(0x3c)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0			_MK_ADDR_CONST(0x40)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0			_MK_ADDR_CONST(0x44)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0			_MK_ADDR_CONST(0x48)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0			_MK_ADDR_CONST(0x4c)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0
+#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0			_MK_ADDR_CONST(0x50)
+#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0
+#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0			_MK_ADDR_CONST(0x54)
+#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0
+#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0			_MK_ADDR_CONST(0x58)
+#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CBUF_DESC_0
+#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0			_MK_ADDR_CONST(0x5c)
+#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0			_MK_ADDR_CONST(0x60)
+#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0			_MK_ADDR_CONST(0x64)
+#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0			_MK_ADDR_CONST(0x68)
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0			_MK_ADDR_CONST(0x6c)
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0			_MK_ADDR_CONST(0x70)
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0			_MK_ADDR_CONST(0x74)
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_DESC_0
+#define NVDLA_CFGROM_CFGROM_CSC_DESC_0			_MK_ADDR_CONST(0x78)
+#define NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0			_MK_ADDR_CONST(0x7c)
+#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0			_MK_ADDR_CONST(0x80)
+#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0			_MK_ADDR_CONST(0x84)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0			_MK_ADDR_CONST(0x88)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0			_MK_ADDR_CONST(0x8c)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0			_MK_ADDR_CONST(0x90)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0			_MK_ADDR_CONST(0x94)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0			_MK_ADDR_CONST(0x98)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0			_MK_ADDR_CONST(0x9c)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0			_MK_ADDR_CONST(0xa0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0			_MK_ADDR_CONST(0xa4)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0
+#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0			_MK_ADDR_CONST(0xa8)
+#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0
+#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0			_MK_ADDR_CONST(0xac)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0			_MK_ADDR_CONST(0xb0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0			_MK_ADDR_CONST(0xb4)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0			_MK_ADDR_CONST(0xb8)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0			_MK_ADDR_CONST(0xbc)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0			_MK_ADDR_CONST(0xc0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0			_MK_ADDR_CONST(0xc4)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0			_MK_ADDR_CONST(0xc8)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0
+#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0			_MK_ADDR_CONST(0xcc)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0			_MK_ADDR_CONST(0xd0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0			_MK_ADDR_CONST(0xd4)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0			_MK_ADDR_CONST(0xd8)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0			_MK_ADDR_CONST(0xdc)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0			_MK_ADDR_CONST(0xe0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0			_MK_ADDR_CONST(0xe4)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0			_MK_ADDR_CONST(0xe8)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CACC_DESC_0
+#define NVDLA_CFGROM_CFGROM_CACC_DESC_0			_MK_ADDR_CONST(0xec)
+#define NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0			_MK_ADDR_CONST(0xf0)
+#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0			_MK_ADDR_CONST(0xf4)
+#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0			_MK_ADDR_CONST(0xf8)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0			_MK_ADDR_CONST(0xfc)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0			_MK_ADDR_CONST(0x100)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0			_MK_ADDR_CONST(0x104)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0			_MK_ADDR_CONST(0x108)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0
+#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0			_MK_ADDR_CONST(0x10c)
+#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0			_MK_ADDR_CONST(0x110)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0			_MK_ADDR_CONST(0x114)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0			_MK_ADDR_CONST(0x118)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0			_MK_ADDR_CONST(0x11c)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0			_MK_ADDR_CONST(0x120)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_DESC_0
+#define NVDLA_CFGROM_CFGROM_SDP_DESC_0			_MK_ADDR_CONST(0x124)
+#define NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0			_MK_ADDR_CONST(0x128)
+#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0			_MK_ADDR_CONST(0x12c)
+#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0
+#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0			_MK_ADDR_CONST(0x130)
+#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0
+#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0			_MK_ADDR_CONST(0x134)
+#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0
+#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0			_MK_ADDR_CONST(0x138)
+#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0
+#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0			_MK_ADDR_CONST(0x13c)
+#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0
+#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0			_MK_ADDR_CONST(0x140)
+#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0
+#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0			_MK_ADDR_CONST(0x144)
+#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0
+#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0			_MK_ADDR_CONST(0x148)
+#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0			_MK_ADDR_CONST(0x14c)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0			_MK_ADDR_CONST(0x150)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0			_MK_ADDR_CONST(0x154)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0			_MK_ADDR_CONST(0x158)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0			_MK_ADDR_CONST(0x15c)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_DESC_0
+#define NVDLA_CFGROM_CFGROM_PDP_DESC_0			_MK_ADDR_CONST(0x160)
+#define NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0			_MK_ADDR_CONST(0x164)
+#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0			_MK_ADDR_CONST(0x168)
+#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0
+#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0			_MK_ADDR_CONST(0x16c)
+#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0
+#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0			_MK_ADDR_CONST(0x170)
+#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0			_MK_ADDR_CONST(0x174)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0			_MK_ADDR_CONST(0x178)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0			_MK_ADDR_CONST(0x17c)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0			_MK_ADDR_CONST(0x180)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0			_MK_ADDR_CONST(0x184)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_DESC_0
+#define NVDLA_CFGROM_CFGROM_CDP_DESC_0			_MK_ADDR_CONST(0x188)
+#define NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0
+#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0			_MK_ADDR_CONST(0x18c)
+#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0
+#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0			_MK_ADDR_CONST(0x190)
+#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0
+#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0			_MK_ADDR_CONST(0x194)
+#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_FIELD			_MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0
+#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0			_MK_ADDR_CONST(0x198)
+#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_SHIFT)
+
+
+// Register NVDLA_CFGROM_CFGROM_END_OF_LIST_0
+#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0			_MK_ADDR_CONST(0x19c)
+#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_FIELD			_MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register GLB_S_NVDLA_HW_VERSION_0
+#define GLB_S_NVDLA_HW_VERSION_0			_MK_ADDR_CONST(0x1000)
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT			_MK_SHIFT_CONST(0)
+#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_FIELD			_MK_FIELD_CONST(0xff, GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT)
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT			_MK_SHIFT_CONST(8)
+#define GLB_S_NVDLA_HW_VERSION_0_MINOR_FIELD			_MK_FIELD_CONST(0xffff, GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT)
+
+
+// Register GLB_S_INTR_MASK_0
+#define GLB_S_INTR_MASK_0			_MK_ADDR_CONST(0x1004)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT			_MK_SHIFT_CONST(0)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT			_MK_SHIFT_CONST(1)
+#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT			_MK_SHIFT_CONST(2)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT			_MK_SHIFT_CONST(3)
+#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT			_MK_SHIFT_CONST(4)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT			_MK_SHIFT_CONST(5)
+#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT			_MK_SHIFT_CONST(6)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT			_MK_SHIFT_CONST(7)
+#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT			_MK_SHIFT_CONST(8)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT			_MK_SHIFT_CONST(9)
+#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT			_MK_SHIFT_CONST(16)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT			_MK_SHIFT_CONST(17)
+#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT			_MK_SHIFT_CONST(18)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT			_MK_SHIFT_CONST(19)
+#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT			_MK_SHIFT_CONST(20)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT			_MK_SHIFT_CONST(21)
+#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT)
+
+
+// Register GLB_S_INTR_SET_0
+#define GLB_S_INTR_SET_0			_MK_ADDR_CONST(0x1008)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT			_MK_SHIFT_CONST(0)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT			_MK_SHIFT_CONST(1)
+#define GLB_S_INTR_SET_0_SDP_DONE_SET1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT			_MK_SHIFT_CONST(2)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT			_MK_SHIFT_CONST(3)
+#define GLB_S_INTR_SET_0_CDP_DONE_SET1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT			_MK_SHIFT_CONST(4)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT			_MK_SHIFT_CONST(5)
+#define GLB_S_INTR_SET_0_PDP_DONE_SET1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT			_MK_SHIFT_CONST(6)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT			_MK_SHIFT_CONST(7)
+#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT			_MK_SHIFT_CONST(8)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT			_MK_SHIFT_CONST(9)
+#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT			_MK_SHIFT_CONST(16)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT			_MK_SHIFT_CONST(17)
+#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT			_MK_SHIFT_CONST(18)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT			_MK_SHIFT_CONST(19)
+#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT			_MK_SHIFT_CONST(20)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT			_MK_SHIFT_CONST(21)
+#define GLB_S_INTR_SET_0_CACC_DONE_SET1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT)
+
+
+// Register GLB_S_INTR_STATUS_0
+#define GLB_S_INTR_STATUS_0			_MK_ADDR_CONST(0x100c)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT			_MK_SHIFT_CONST(0)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT			_MK_SHIFT_CONST(1)
+#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT			_MK_SHIFT_CONST(2)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT			_MK_SHIFT_CONST(3)
+#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT			_MK_SHIFT_CONST(4)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT			_MK_SHIFT_CONST(5)
+#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT			_MK_SHIFT_CONST(6)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT			_MK_SHIFT_CONST(7)
+#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT			_MK_SHIFT_CONST(8)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT			_MK_SHIFT_CONST(9)
+#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT			_MK_SHIFT_CONST(16)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT			_MK_SHIFT_CONST(17)
+#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT			_MK_SHIFT_CONST(18)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT			_MK_SHIFT_CONST(19)
+#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT			_MK_SHIFT_CONST(20)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT			_MK_SHIFT_CONST(21)
+#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_FIELD			_MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register NVDLA_MCIF_CFG_RD_WEIGHT_0_0
+#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0			_MK_ADDR_CONST(0x2000)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT)
+
+
+// Register NVDLA_MCIF_CFG_RD_WEIGHT_1_0
+#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0			_MK_ADDR_CONST(0x2004)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT)
+
+
+// Register NVDLA_MCIF_CFG_RD_WEIGHT_2_0
+#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0			_MK_ADDR_CONST(0x2008)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT)
+
+
+// Register NVDLA_MCIF_CFG_WR_WEIGHT_0_0
+#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0			_MK_ADDR_CONST(0x200c)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT)
+
+
+// Register NVDLA_MCIF_CFG_WR_WEIGHT_1_0
+#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0			_MK_ADDR_CONST(0x2010)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT)
+
+
+// Register NVDLA_MCIF_CFG_OUTSTANDING_CNT_0
+#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0			_MK_ADDR_CONST(0x2014)
+#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT)
+#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD			_MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT)
+
+
+// Register NVDLA_MCIF_STATUS_0
+#define NVDLA_MCIF_STATUS_0			_MK_ADDR_CONST(0x2018)
+#define NVDLA_MCIF_STATUS_0_IDLE_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_MCIF_STATUS_0_IDLE_FIELD			_MK_FIELD_CONST(0x1, NVDLA_MCIF_STATUS_0_IDLE_SHIFT)
+#define NVDLA_MCIF_STATUS_0_IDLE_NO			_MK_ENUM_CONST(0x0)
+#define NVDLA_MCIF_STATUS_0_IDLE_YES			_MK_ENUM_CONST(0x1)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register CDMA_S_STATUS_0
+#define CDMA_S_STATUS_0			_MK_ADDR_CONST(0x3000)
+#define CDMA_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_0_SHIFT)
+#define CDMA_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define CDMA_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define CDMA_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define CDMA_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_1_SHIFT)
+#define CDMA_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define CDMA_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define CDMA_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register CDMA_S_POINTER_0
+#define CDMA_S_POINTER_0			_MK_ADDR_CONST(0x3004)
+#define CDMA_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_PRODUCER_SHIFT)
+#define CDMA_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CDMA_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define CDMA_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_CONSUMER_SHIFT)
+#define CDMA_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CDMA_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_S_ARBITER_0
+#define CDMA_S_ARBITER_0			_MK_ADDR_CONST(0x3008)
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_S_ARBITER_0_ARB_WEIGHT_FIELD			_MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT)
+#define CDMA_S_ARBITER_0_ARB_WMB_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_S_ARBITER_0_ARB_WMB_FIELD			_MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WMB_SHIFT)
+
+
+// Register CDMA_S_CBUF_FLUSH_STATUS_0
+#define CDMA_S_CBUF_FLUSH_STATUS_0			_MK_ADDR_CONST(0x300c)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_FIELD			_MK_FIELD_CONST(0x1, CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT)
+
+
+// Register CDMA_D_OP_ENABLE_0
+#define CDMA_D_OP_ENABLE_0			_MK_ADDR_CONST(0x3010)
+#define CDMA_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define CDMA_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_D_MISC_CFG_0
+#define CDMA_D_MISC_CFG_0			_MK_ADDR_CONST(0x3014)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_DIRECT			_MK_ENUM_CONST(0x0)
+#define CDMA_D_MISC_CFG_0_CONV_MODE_WINOGRAD			_MK_ENUM_CONST(0x1)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT			_MK_SHIFT_CONST(8)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_FIELD			_MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define CDMA_D_MISC_CFG_0_IN_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT			_MK_SHIFT_CONST(12)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FIELD			_MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_MISC_CFG_0_DATA_REUSE_ENABLE			_MK_ENUM_CONST(0x1)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT			_MK_SHIFT_CONST(20)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE			_MK_ENUM_CONST(0x1)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT			_MK_SHIFT_CONST(24)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE			_MK_ENUM_CONST(0x1)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT			_MK_SHIFT_CONST(28)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_D_DATAIN_FORMAT_0
+#define CDMA_D_DATAIN_FORMAT_0			_MK_ADDR_CONST(0x3018)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL			_MK_ENUM_CONST(0x1)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT			_MK_SHIFT_CONST(8)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_FIELD			_MK_FIELD_CONST(0x3f, CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8			_MK_ENUM_CONST(0x0)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10			_MK_ENUM_CONST(0x1)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R12			_MK_ENUM_CONST(0x2)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16			_MK_ENUM_CONST(0x3)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_I			_MK_ENUM_CONST(0x4)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_F			_MK_ENUM_CONST(0x5)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16			_MK_ENUM_CONST(0x6)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X16B16G16R16			_MK_ENUM_CONST(0x7)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16_F			_MK_ENUM_CONST(0x8)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16			_MK_ENUM_CONST(0x9)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V16U16Y16A16			_MK_ENUM_CONST(0xa)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16_F			_MK_ENUM_CONST(0xb)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8B8G8R8			_MK_ENUM_CONST(0xc)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8R8G8B8			_MK_ENUM_CONST(0xd)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8A8			_MK_ENUM_CONST(0xe)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8A8			_MK_ENUM_CONST(0xf)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8B8G8R8			_MK_ENUM_CONST(0x10)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8R8G8B8			_MK_ENUM_CONST(0x11)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8X8			_MK_ENUM_CONST(0x12)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8X8			_MK_ENUM_CONST(0x13)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2B10G10R10			_MK_ENUM_CONST(0x14)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2R10G10B10			_MK_ENUM_CONST(0x15)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B10G10R10A2			_MK_ENUM_CONST(0x16)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10G10B10A2			_MK_ENUM_CONST(0x17)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2Y10U10V10			_MK_ENUM_CONST(0x18)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V10U10Y10A2			_MK_ENUM_CONST(0x19)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8Y8U8V8			_MK_ENUM_CONST(0x1a)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V8U8Y8A8			_MK_ENUM_CONST(0x1b)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___U8V8_N444			_MK_ENUM_CONST(0x1c)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___V8U8_N444			_MK_ENUM_CONST(0x1d)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___U10V10_N444			_MK_ENUM_CONST(0x1e)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___V10U10_N444			_MK_ENUM_CONST(0x1f)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___U12V12_N444			_MK_ENUM_CONST(0x20)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___V12U12_N444			_MK_ENUM_CONST(0x21)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___U16V16_N444			_MK_ENUM_CONST(0x22)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___V16U16_N444			_MK_ENUM_CONST(0x23)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PITCH_LINEAR			_MK_ENUM_CONST(0x0)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RESERVED_LINEAR			_MK_ENUM_CONST(0x1)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT			_MK_SHIFT_CONST(20)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_UNSIGNED_INT			_MK_ENUM_CONST(0x0)
+#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SIGNED_INT			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_D_DATAIN_SIZE_0_0
+#define CDMA_D_DATAIN_SIZE_0_0			_MK_ADDR_CONST(0x301c)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT)
+
+
+// Register CDMA_D_DATAIN_SIZE_1_0
+#define CDMA_D_DATAIN_SIZE_1_0			_MK_ADDR_CONST(0x3020)
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT)
+
+
+// Register CDMA_D_DATAIN_SIZE_EXT_0_0
+#define CDMA_D_DATAIN_SIZE_EXT_0_0			_MK_ADDR_CONST(0x3024)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD			_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD			_MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT)
+
+
+// Register CDMA_D_PIXEL_OFFSET_0
+#define CDMA_D_PIXEL_OFFSET_0			_MK_ADDR_CONST(0x3028)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_FIELD			_MK_FIELD_CONST(0x1f, CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_FIELD			_MK_FIELD_CONST(0x7, CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT)
+
+
+// Register CDMA_D_DAIN_RAM_TYPE_0
+#define CDMA_D_DAIN_RAM_TYPE_0			_MK_ADDR_CONST(0x302c)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF			_MK_ENUM_CONST(0x0)
+#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_D_DAIN_ADDR_HIGH_0_0
+#define CDMA_D_DAIN_ADDR_HIGH_0_0			_MK_ADDR_CONST(0x3030)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT)
+
+
+// Register CDMA_D_DAIN_ADDR_LOW_0_0
+#define CDMA_D_DAIN_ADDR_LOW_0_0			_MK_ADDR_CONST(0x3034)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT)
+
+
+// Register CDMA_D_DAIN_ADDR_HIGH_1_0
+#define CDMA_D_DAIN_ADDR_HIGH_1_0			_MK_ADDR_CONST(0x3038)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT)
+
+
+// Register CDMA_D_DAIN_ADDR_LOW_1_0
+#define CDMA_D_DAIN_ADDR_LOW_1_0			_MK_ADDR_CONST(0x303c)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT)
+
+
+// Register CDMA_D_LINE_STRIDE_0
+#define CDMA_D_LINE_STRIDE_0			_MK_ADDR_CONST(0x3040)
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT)
+
+
+// Register CDMA_D_LINE_UV_STRIDE_0
+#define CDMA_D_LINE_UV_STRIDE_0			_MK_ADDR_CONST(0x3044)
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT)
+
+
+// Register CDMA_D_SURF_STRIDE_0
+#define CDMA_D_SURF_STRIDE_0			_MK_ADDR_CONST(0x3048)
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT)
+
+
+// Register CDMA_D_DAIN_MAP_0
+#define CDMA_D_DAIN_MAP_0			_MK_ADDR_CONST(0x304c)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FALSE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_DAIN_MAP_0_LINE_PACKED_TRUE			_MK_ENUM_CONST(0x1)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FALSE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_DAIN_MAP_0_SURF_PACKED_TRUE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_D_RESERVED_X_CFG_0
+#define CDMA_D_RESERVED_X_CFG_0			_MK_ADDR_CONST(0x3050)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_FIELD			_MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_FIELD			_MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT)
+
+
+// Register CDMA_D_RESERVED_Y_CFG_0
+#define CDMA_D_RESERVED_Y_CFG_0			_MK_ADDR_CONST(0x3054)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_FIELD			_MK_FIELD_CONST(0x7, CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_FIELD			_MK_FIELD_CONST(0x1f, CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT)
+
+
+// Register CDMA_D_BATCH_NUMBER_0
+#define CDMA_D_BATCH_NUMBER_0			_MK_ADDR_CONST(0x3058)
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_BATCH_NUMBER_0_BATCHES_FIELD			_MK_FIELD_CONST(0x1f, CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT)
+
+
+// Register CDMA_D_BATCH_STRIDE_0
+#define CDMA_D_BATCH_STRIDE_0			_MK_ADDR_CONST(0x305c)
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT)
+
+
+// Register CDMA_D_ENTRY_PER_SLICE_0
+#define CDMA_D_ENTRY_PER_SLICE_0			_MK_ADDR_CONST(0x3060)
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD			_MK_FIELD_CONST(0x3fff, CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT)
+
+
+// Register CDMA_D_FETCH_GRAIN_0
+#define CDMA_D_FETCH_GRAIN_0			_MK_ADDR_CONST(0x3064)
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_FETCH_GRAIN_0_GRAINS_FIELD			_MK_FIELD_CONST(0xfff, CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT)
+
+
+// Register CDMA_D_WEIGHT_FORMAT_0
+#define CDMA_D_WEIGHT_FORMAT_0			_MK_ADDR_CONST(0x3068)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED			_MK_ENUM_CONST(0x0)
+#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_D_WEIGHT_SIZE_0_0
+#define CDMA_D_WEIGHT_SIZE_0_0			_MK_ADDR_CONST(0x306c)
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_FIELD			_MK_FIELD_CONST(0x3ffff, CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT)
+
+
+// Register CDMA_D_WEIGHT_SIZE_1_0
+#define CDMA_D_WEIGHT_SIZE_1_0			_MK_ADDR_CONST(0x3070)
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_FIELD			_MK_FIELD_CONST(0x1fff, CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT)
+
+
+// Register CDMA_D_WEIGHT_RAM_TYPE_0
+#define CDMA_D_WEIGHT_RAM_TYPE_0			_MK_ADDR_CONST(0x3074)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_CVIF			_MK_ENUM_CONST(0x0)
+#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_MCIF			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_D_WEIGHT_ADDR_HIGH_0
+#define CDMA_D_WEIGHT_ADDR_HIGH_0			_MK_ADDR_CONST(0x3078)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT)
+
+
+// Register CDMA_D_WEIGHT_ADDR_LOW_0
+#define CDMA_D_WEIGHT_ADDR_LOW_0			_MK_ADDR_CONST(0x307c)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT)
+
+
+// Register CDMA_D_WEIGHT_BYTES_0
+#define CDMA_D_WEIGHT_BYTES_0			_MK_ADDR_CONST(0x3080)
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT)
+
+
+// Register CDMA_D_WGS_ADDR_HIGH_0
+#define CDMA_D_WGS_ADDR_HIGH_0			_MK_ADDR_CONST(0x3084)
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT)
+
+
+// Register CDMA_D_WGS_ADDR_LOW_0
+#define CDMA_D_WGS_ADDR_LOW_0			_MK_ADDR_CONST(0x3088)
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT)
+
+
+// Register CDMA_D_WMB_ADDR_HIGH_0
+#define CDMA_D_WMB_ADDR_HIGH_0			_MK_ADDR_CONST(0x308c)
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT)
+
+
+// Register CDMA_D_WMB_ADDR_LOW_0
+#define CDMA_D_WMB_ADDR_LOW_0			_MK_ADDR_CONST(0x3090)
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT)
+
+
+// Register CDMA_D_WMB_BYTES_0
+#define CDMA_D_WMB_BYTES_0			_MK_ADDR_CONST(0x3094)
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_WMB_BYTES_0_WMB_BYTES_FIELD			_MK_FIELD_CONST(0xfffffff, CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT)
+
+
+// Register CDMA_D_MEAN_FORMAT_0
+#define CDMA_D_MEAN_FORMAT_0			_MK_ADDR_CONST(0x3098)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_D_MEAN_GLOBAL_0_0
+#define CDMA_D_MEAN_GLOBAL_0_0			_MK_ADDR_CONST(0x309c)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_FIELD			_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_FIELD			_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT)
+
+
+// Register CDMA_D_MEAN_GLOBAL_1_0
+#define CDMA_D_MEAN_GLOBAL_1_0			_MK_ADDR_CONST(0x30a0)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_FIELD			_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_FIELD			_MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT)
+
+
+// Register CDMA_D_CVT_CFG_0
+#define CDMA_D_CVT_CFG_0			_MK_ADDR_CONST(0x30a4)
+#define CDMA_D_CVT_CFG_0_CVT_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_CVT_CFG_0_CVT_EN_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_CVT_CFG_0_CVT_EN_SHIFT)
+#define CDMA_D_CVT_CFG_0_CVT_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_CVT_CFG_0_CVT_EN_ENABLE			_MK_ENUM_CONST(0x1)
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT			_MK_SHIFT_CONST(4)
+#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_FIELD			_MK_FIELD_CONST(0x3f, CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT)
+
+
+// Register CDMA_D_CVT_OFFSET_0
+#define CDMA_D_CVT_OFFSET_0			_MK_ADDR_CONST(0x30a8)
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_FIELD			_MK_FIELD_CONST(0xffff, CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT)
+
+
+// Register CDMA_D_CVT_SCALE_0
+#define CDMA_D_CVT_SCALE_0			_MK_ADDR_CONST(0x30ac)
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_CVT_SCALE_0_CVT_SCALE_FIELD			_MK_FIELD_CONST(0xffff, CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT)
+
+
+// Register CDMA_D_CONV_STRIDE_0
+#define CDMA_D_CONV_STRIDE_0			_MK_ADDR_CONST(0x30b0)
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_FIELD			_MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT)
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_FIELD			_MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT)
+
+
+// Register CDMA_D_ZERO_PADDING_0
+#define CDMA_D_ZERO_PADDING_0			_MK_ADDR_CONST(0x30b4)
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_FIELD			_MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT)
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT			_MK_SHIFT_CONST(8)
+#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_FIELD			_MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT)
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_ZERO_PADDING_0_PAD_TOP_FIELD			_MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT)
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT			_MK_SHIFT_CONST(24)
+#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_FIELD			_MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT)
+
+
+// Register CDMA_D_ZERO_PADDING_VALUE_0
+#define CDMA_D_ZERO_PADDING_VALUE_0			_MK_ADDR_CONST(0x30b8)
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD			_MK_FIELD_CONST(0xffff, CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT)
+
+
+// Register CDMA_D_BANK_0
+#define CDMA_D_BANK_0			_MK_ADDR_CONST(0x30bc)
+#define CDMA_D_BANK_0_DATA_BANK_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_BANK_0_DATA_BANK_FIELD			_MK_FIELD_CONST(0x1f, CDMA_D_BANK_0_DATA_BANK_SHIFT)
+#define CDMA_D_BANK_0_WEIGHT_BANK_SHIFT			_MK_SHIFT_CONST(16)
+#define CDMA_D_BANK_0_WEIGHT_BANK_FIELD			_MK_FIELD_CONST(0x1f, CDMA_D_BANK_0_WEIGHT_BANK_SHIFT)
+
+
+// Register CDMA_D_NAN_FLUSH_TO_ZERO_0
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0			_MK_ADDR_CONST(0x30c0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDMA_D_NAN_INPUT_DATA_NUM_0
+#define CDMA_D_NAN_INPUT_DATA_NUM_0			_MK_ADDR_CONST(0x30c4)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT)
+
+
+// Register CDMA_D_NAN_INPUT_WEIGHT_NUM_0
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0			_MK_ADDR_CONST(0x30c8)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT)
+
+
+// Register CDMA_D_INF_INPUT_DATA_NUM_0
+#define CDMA_D_INF_INPUT_DATA_NUM_0			_MK_ADDR_CONST(0x30cc)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT)
+
+
+// Register CDMA_D_INF_INPUT_WEIGHT_NUM_0
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0			_MK_ADDR_CONST(0x30d0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT)
+
+
+// Register CDMA_D_PERF_ENABLE_0
+#define CDMA_D_PERF_ENABLE_0			_MK_ADDR_CONST(0x30d4)
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_PERF_ENABLE_0_DMA_EN_FIELD			_MK_FIELD_CONST(0x1, CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT)
+
+
+// Register CDMA_D_PERF_DAT_READ_STALL_0
+#define CDMA_D_PERF_DAT_READ_STALL_0			_MK_ADDR_CONST(0x30d8)
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT)
+
+
+// Register CDMA_D_PERF_WT_READ_STALL_0
+#define CDMA_D_PERF_WT_READ_STALL_0			_MK_ADDR_CONST(0x30dc)
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT)
+
+
+// Register CDMA_D_PERF_DAT_READ_LATENCY_0
+#define CDMA_D_PERF_DAT_READ_LATENCY_0			_MK_ADDR_CONST(0x30e0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT)
+
+
+// Register CDMA_D_PERF_WT_READ_LATENCY_0
+#define CDMA_D_PERF_WT_READ_LATENCY_0			_MK_ADDR_CONST(0x30e4)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT)
+
+
+// Register CDMA_D_CYA_0
+#define CDMA_D_CYA_0			_MK_ADDR_CONST(0x30e8)
+#define CDMA_D_CYA_0_CYA_SHIFT			_MK_SHIFT_CONST(0)
+#define CDMA_D_CYA_0_CYA_FIELD			_MK_FIELD_CONST(0xffffffff, CDMA_D_CYA_0_CYA_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register CSC_S_STATUS_0
+#define CSC_S_STATUS_0			_MK_ADDR_CONST(0x4000)
+#define CSC_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_0_SHIFT)
+#define CSC_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define CSC_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define CSC_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define CSC_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_1_SHIFT)
+#define CSC_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define CSC_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define CSC_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register CSC_S_POINTER_0
+#define CSC_S_POINTER_0			_MK_ADDR_CONST(0x4004)
+#define CSC_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, CSC_S_POINTER_0_PRODUCER_SHIFT)
+#define CSC_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CSC_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define CSC_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, CSC_S_POINTER_0_CONSUMER_SHIFT)
+#define CSC_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CSC_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register CSC_D_OP_ENABLE_0
+#define CSC_D_OP_ENABLE_0			_MK_ADDR_CONST(0x4008)
+#define CSC_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, CSC_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define CSC_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CSC_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CSC_D_MISC_CFG_0
+#define CSC_D_MISC_CFG_0			_MK_ADDR_CONST(0x400c)
+#define CSC_D_MISC_CFG_0_CONV_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_MISC_CFG_0_CONV_MODE_FIELD			_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_CONV_MODE_SHIFT)
+#define CSC_D_MISC_CFG_0_CONV_MODE_DIRECT			_MK_ENUM_CONST(0x0)
+#define CSC_D_MISC_CFG_0_CONV_MODE_WINOGRAD			_MK_ENUM_CONST(0x1)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT			_MK_SHIFT_CONST(8)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_FIELD			_MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define CSC_D_MISC_CFG_0_IN_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT			_MK_SHIFT_CONST(12)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_FIELD			_MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define CSC_D_MISC_CFG_0_PROC_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_FIELD			_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_DISABLE			_MK_ENUM_CONST(0x0)
+#define CSC_D_MISC_CFG_0_DATA_REUSE_ENABLE			_MK_ENUM_CONST(0x1)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT			_MK_SHIFT_CONST(20)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_FIELD			_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE			_MK_ENUM_CONST(0x0)
+#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE			_MK_ENUM_CONST(0x1)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT			_MK_SHIFT_CONST(24)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD			_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE			_MK_ENUM_CONST(0x0)
+#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE			_MK_ENUM_CONST(0x1)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT			_MK_SHIFT_CONST(28)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD			_MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE			_MK_ENUM_CONST(0x0)
+#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CSC_D_DATAIN_FORMAT_0
+#define CSC_D_DATAIN_FORMAT_0			_MK_ADDR_CONST(0x4010)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD			_MK_FIELD_CONST(0x1, CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE			_MK_ENUM_CONST(0x0)
+#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL			_MK_ENUM_CONST(0x1)
+
+
+// Register CSC_D_DATAIN_SIZE_EXT_0_0
+#define CSC_D_DATAIN_SIZE_EXT_0_0			_MK_ADDR_CONST(0x4014)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD			_MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD			_MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT)
+
+
+// Register CSC_D_DATAIN_SIZE_EXT_1_0
+#define CSC_D_DATAIN_SIZE_EXT_1_0			_MK_ADDR_CONST(0x4018)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_FIELD			_MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT)
+
+
+// Register CSC_D_BATCH_NUMBER_0
+#define CSC_D_BATCH_NUMBER_0			_MK_ADDR_CONST(0x401c)
+#define CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_BATCH_NUMBER_0_BATCHES_FIELD			_MK_FIELD_CONST(0x1f, CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT)
+
+
+// Register CSC_D_POST_Y_EXTENSION_0
+#define CSC_D_POST_Y_EXTENSION_0			_MK_ADDR_CONST(0x4020)
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_FIELD			_MK_FIELD_CONST(0x3, CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT)
+
+
+// Register CSC_D_ENTRY_PER_SLICE_0
+#define CSC_D_ENTRY_PER_SLICE_0			_MK_ADDR_CONST(0x4024)
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD			_MK_FIELD_CONST(0x3fff, CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT)
+
+
+// Register CSC_D_WEIGHT_FORMAT_0
+#define CSC_D_WEIGHT_FORMAT_0			_MK_ADDR_CONST(0x4028)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD			_MK_FIELD_CONST(0x1, CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED			_MK_ENUM_CONST(0x0)
+#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED			_MK_ENUM_CONST(0x1)
+
+
+// Register CSC_D_WEIGHT_SIZE_EXT_0_0
+#define CSC_D_WEIGHT_SIZE_EXT_0_0			_MK_ADDR_CONST(0x402c)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_FIELD			_MK_FIELD_CONST(0x1f, CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_FIELD			_MK_FIELD_CONST(0x1f, CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT)
+
+
+// Register CSC_D_WEIGHT_SIZE_EXT_1_0
+#define CSC_D_WEIGHT_SIZE_EXT_1_0			_MK_ADDR_CONST(0x4030)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_FIELD			_MK_FIELD_CONST(0x1fff, CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_FIELD			_MK_FIELD_CONST(0x1fff, CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT)
+
+
+// Register CSC_D_WEIGHT_BYTES_0
+#define CSC_D_WEIGHT_BYTES_0			_MK_ADDR_CONST(0x4034)
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD			_MK_FIELD_CONST(0xffffffff, CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT)
+
+
+// Register CSC_D_WMB_BYTES_0
+#define CSC_D_WMB_BYTES_0			_MK_ADDR_CONST(0x4038)
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_WMB_BYTES_0_WMB_BYTES_FIELD			_MK_FIELD_CONST(0xfffffff, CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT)
+
+
+// Register CSC_D_DATAOUT_SIZE_0_0
+#define CSC_D_DATAOUT_SIZE_0_0			_MK_ADDR_CONST(0x403c)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT)
+
+
+// Register CSC_D_DATAOUT_SIZE_1_0
+#define CSC_D_DATAOUT_SIZE_1_0			_MK_ADDR_CONST(0x4040)
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT)
+
+
+// Register CSC_D_ATOMICS_0
+#define CSC_D_ATOMICS_0			_MK_ADDR_CONST(0x4044)
+#define CSC_D_ATOMICS_0_ATOMICS_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_ATOMICS_0_ATOMICS_FIELD			_MK_FIELD_CONST(0x1fffff, CSC_D_ATOMICS_0_ATOMICS_SHIFT)
+
+
+// Register CSC_D_RELEASE_0
+#define CSC_D_RELEASE_0			_MK_ADDR_CONST(0x4048)
+#define CSC_D_RELEASE_0_RLS_SLICES_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_RELEASE_0_RLS_SLICES_FIELD			_MK_FIELD_CONST(0xfff, CSC_D_RELEASE_0_RLS_SLICES_SHIFT)
+
+
+// Register CSC_D_CONV_STRIDE_EXT_0
+#define CSC_D_CONV_STRIDE_EXT_0			_MK_ADDR_CONST(0x404c)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_FIELD			_MK_FIELD_CONST(0x7, CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_FIELD			_MK_FIELD_CONST(0x7, CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT)
+
+
+// Register CSC_D_DILATION_EXT_0
+#define CSC_D_DILATION_EXT_0			_MK_ADDR_CONST(0x4050)
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_FIELD			_MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT)
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_FIELD			_MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT)
+
+
+// Register CSC_D_ZERO_PADDING_0
+#define CSC_D_ZERO_PADDING_0			_MK_ADDR_CONST(0x4054)
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_ZERO_PADDING_0_PAD_LEFT_FIELD			_MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT)
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_D_ZERO_PADDING_0_PAD_TOP_FIELD			_MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT)
+
+
+// Register CSC_D_ZERO_PADDING_VALUE_0
+#define CSC_D_ZERO_PADDING_VALUE_0			_MK_ADDR_CONST(0x4058)
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD			_MK_FIELD_CONST(0xffff, CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT)
+
+
+// Register CSC_D_BANK_0
+#define CSC_D_BANK_0			_MK_ADDR_CONST(0x405c)
+#define CSC_D_BANK_0_DATA_BANK_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_BANK_0_DATA_BANK_FIELD			_MK_FIELD_CONST(0x1f, CSC_D_BANK_0_DATA_BANK_SHIFT)
+#define CSC_D_BANK_0_WEIGHT_BANK_SHIFT			_MK_SHIFT_CONST(16)
+#define CSC_D_BANK_0_WEIGHT_BANK_FIELD			_MK_FIELD_CONST(0x1f, CSC_D_BANK_0_WEIGHT_BANK_SHIFT)
+
+
+// Register CSC_D_PRA_CFG_0
+#define CSC_D_PRA_CFG_0			_MK_ADDR_CONST(0x4060)
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_FIELD			_MK_FIELD_CONST(0x3, CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT)
+
+
+// Register CSC_D_CYA_0
+#define CSC_D_CYA_0			_MK_ADDR_CONST(0x4064)
+#define CSC_D_CYA_0_CYA_SHIFT			_MK_SHIFT_CONST(0)
+#define CSC_D_CYA_0_CYA_FIELD			_MK_FIELD_CONST(0xffffffff, CSC_D_CYA_0_CYA_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register CMAC_A_S_STATUS_0
+#define CMAC_A_S_STATUS_0			_MK_ADDR_CONST(0x5000)
+#define CMAC_A_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define CMAC_A_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_0_SHIFT)
+#define CMAC_A_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define CMAC_A_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define CMAC_A_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define CMAC_A_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define CMAC_A_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_1_SHIFT)
+#define CMAC_A_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define CMAC_A_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define CMAC_A_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register CMAC_A_S_POINTER_0
+#define CMAC_A_S_POINTER_0			_MK_ADDR_CONST(0x5004)
+#define CMAC_A_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define CMAC_A_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_PRODUCER_SHIFT)
+#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define CMAC_A_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define CMAC_A_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_CONSUMER_SHIFT)
+#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register CMAC_A_D_OP_ENABLE_0
+#define CMAC_A_D_OP_ENABLE_0			_MK_ADDR_CONST(0x5008)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CMAC_A_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CMAC_A_D_MISC_CFG_0
+#define CMAC_A_D_MISC_CFG_0			_MK_ADDR_CONST(0x500c)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_FIELD			_MK_FIELD_CONST(0x1, CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DIRECT			_MK_ENUM_CONST(0x0)
+#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WINOGRAD			_MK_ENUM_CONST(0x1)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT			_MK_SHIFT_CONST(12)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FIELD			_MK_FIELD_CONST(0x3, CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register CMAC_B_S_STATUS_0
+#define CMAC_B_S_STATUS_0			_MK_ADDR_CONST(0x6000)
+#define CMAC_B_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define CMAC_B_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_0_SHIFT)
+#define CMAC_B_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define CMAC_B_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define CMAC_B_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define CMAC_B_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define CMAC_B_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_1_SHIFT)
+#define CMAC_B_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define CMAC_B_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define CMAC_B_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register CMAC_B_S_POINTER_0
+#define CMAC_B_S_POINTER_0			_MK_ADDR_CONST(0x6004)
+#define CMAC_B_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define CMAC_B_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_PRODUCER_SHIFT)
+#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define CMAC_B_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define CMAC_B_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_CONSUMER_SHIFT)
+#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register CMAC_B_D_OP_ENABLE_0
+#define CMAC_B_D_OP_ENABLE_0			_MK_ADDR_CONST(0x6008)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CMAC_B_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CMAC_B_D_MISC_CFG_0
+#define CMAC_B_D_MISC_CFG_0			_MK_ADDR_CONST(0x600c)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_FIELD			_MK_FIELD_CONST(0x1, CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DIRECT			_MK_ENUM_CONST(0x0)
+#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WINOGRAD			_MK_ENUM_CONST(0x1)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT			_MK_SHIFT_CONST(12)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FIELD			_MK_FIELD_CONST(0x3, CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register CACC_S_STATUS_0
+#define CACC_S_STATUS_0			_MK_ADDR_CONST(0x7000)
+#define CACC_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_0_SHIFT)
+#define CACC_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define CACC_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define CACC_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define CACC_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define CACC_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_1_SHIFT)
+#define CACC_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define CACC_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define CACC_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register CACC_S_POINTER_0
+#define CACC_S_POINTER_0			_MK_ADDR_CONST(0x7004)
+#define CACC_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, CACC_S_POINTER_0_PRODUCER_SHIFT)
+#define CACC_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CACC_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define CACC_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define CACC_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, CACC_S_POINTER_0_CONSUMER_SHIFT)
+#define CACC_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CACC_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register CACC_D_OP_ENABLE_0
+#define CACC_D_OP_ENABLE_0			_MK_ADDR_CONST(0x7008)
+#define CACC_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, CACC_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define CACC_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CACC_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CACC_D_MISC_CFG_0
+#define CACC_D_MISC_CFG_0			_MK_ADDR_CONST(0x700c)
+#define CACC_D_MISC_CFG_0_CONV_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_MISC_CFG_0_CONV_MODE_FIELD			_MK_FIELD_CONST(0x1, CACC_D_MISC_CFG_0_CONV_MODE_SHIFT)
+#define CACC_D_MISC_CFG_0_CONV_MODE_DIRECT			_MK_ENUM_CONST(0x0)
+#define CACC_D_MISC_CFG_0_CONV_MODE_WINOGRAD			_MK_ENUM_CONST(0x1)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT			_MK_SHIFT_CONST(12)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_FIELD			_MK_FIELD_CONST(0x3, CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define CACC_D_MISC_CFG_0_PROC_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+
+
+// Register CACC_D_DATAOUT_SIZE_0_0
+#define CACC_D_DATAOUT_SIZE_0_0			_MK_ADDR_CONST(0x7010)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT			_MK_SHIFT_CONST(16)
+#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT)
+
+
+// Register CACC_D_DATAOUT_SIZE_1_0
+#define CACC_D_DATAOUT_SIZE_1_0			_MK_ADDR_CONST(0x7014)
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT)
+
+
+// Register CACC_D_DATAOUT_ADDR_0
+#define CACC_D_DATAOUT_ADDR_0			_MK_ADDR_CONST(0x7018)
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_FIELD			_MK_FIELD_CONST(0xffffffff, CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT)
+
+
+// Register CACC_D_BATCH_NUMBER_0
+#define CACC_D_BATCH_NUMBER_0			_MK_ADDR_CONST(0x701c)
+#define CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_BATCH_NUMBER_0_BATCHES_FIELD			_MK_FIELD_CONST(0x1f, CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT)
+
+
+// Register CACC_D_LINE_STRIDE_0
+#define CACC_D_LINE_STRIDE_0			_MK_ADDR_CONST(0x7020)
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffff, CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT)
+
+
+// Register CACC_D_SURF_STRIDE_0
+#define CACC_D_SURF_STRIDE_0			_MK_ADDR_CONST(0x7024)
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_FIELD			_MK_FIELD_CONST(0xffffff, CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT)
+
+
+// Register CACC_D_DATAOUT_MAP_0
+#define CACC_D_DATAOUT_MAP_0			_MK_ADDR_CONST(0x7028)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FIELD			_MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FALSE			_MK_ENUM_CONST(0x0)
+#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE			_MK_ENUM_CONST(0x1)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT			_MK_SHIFT_CONST(16)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FIELD			_MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FALSE			_MK_ENUM_CONST(0x0)
+#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE			_MK_ENUM_CONST(0x1)
+
+
+// Register CACC_D_CLIP_CFG_0
+#define CACC_D_CLIP_CFG_0			_MK_ADDR_CONST(0x702c)
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_FIELD			_MK_FIELD_CONST(0x1f, CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT)
+
+
+// Register CACC_D_OUT_SATURATION_0
+#define CACC_D_OUT_SATURATION_0			_MK_ADDR_CONST(0x7030)
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_OUT_SATURATION_0_SAT_COUNT_FIELD			_MK_FIELD_CONST(0xffffffff, CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT)
+
+
+// Register CACC_D_CYA_0
+#define CACC_D_CYA_0			_MK_ADDR_CONST(0x7034)
+#define CACC_D_CYA_0_CYA_SHIFT			_MK_SHIFT_CONST(0)
+#define CACC_D_CYA_0_CYA_FIELD			_MK_FIELD_CONST(0xffffffff, CACC_D_CYA_0_CYA_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register SDP_RDMA_S_STATUS_0
+#define SDP_RDMA_S_STATUS_0			_MK_ADDR_CONST(0x8000)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register SDP_RDMA_S_POINTER_0
+#define SDP_RDMA_S_POINTER_0			_MK_ADDR_CONST(0x8004)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_RDMA_D_OP_ENABLE_0
+#define SDP_RDMA_D_OP_ENABLE_0			_MK_ADDR_CONST(0x8008)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_RDMA_D_DATA_CUBE_WIDTH_0
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0			_MK_ADDR_CONST(0x800c)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT)
+
+
+// Register SDP_RDMA_D_DATA_CUBE_HEIGHT_0
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0			_MK_ADDR_CONST(0x8010)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT)
+
+
+// Register SDP_RDMA_D_DATA_CUBE_CHANNEL_0
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0			_MK_ADDR_CONST(0x8014)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT)
+
+
+// Register SDP_RDMA_D_SRC_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0x8018)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT)
+
+
+// Register SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0x801c)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register SDP_RDMA_D_SRC_LINE_STRIDE_0
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0			_MK_ADDR_CONST(0x8020)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_SRC_SURFACE_STRIDE_0
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0			_MK_ADDR_CONST(0x8024)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_BRDMA_CFG_0
+#define SDP_RDMA_D_BRDMA_CFG_0			_MK_ADDR_CONST(0x8028)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_NO			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_YES			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_FIELD			_MK_FIELD_CONST(0x3, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_MUL			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_ALU			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_BOTH			_MK_ENUM_CONST(0x2)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT			_MK_SHIFT_CONST(3)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_ONE_BYTE			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_TWO_BYTE			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT			_MK_SHIFT_CONST(4)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_KERNEL			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_ELEMENT			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(5)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_CV			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_RDMA_D_BS_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0x802c)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT)
+
+
+// Register SDP_RDMA_D_BS_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0x8030)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register SDP_RDMA_D_BS_LINE_STRIDE_0
+#define SDP_RDMA_D_BS_LINE_STRIDE_0			_MK_ADDR_CONST(0x8034)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_BS_SURFACE_STRIDE_0
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0			_MK_ADDR_CONST(0x8038)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_BS_BATCH_STRIDE_0
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0			_MK_ADDR_CONST(0x803c)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_NRDMA_CFG_0
+#define SDP_RDMA_D_NRDMA_CFG_0			_MK_ADDR_CONST(0x8040)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_NO			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_YES			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_FIELD			_MK_FIELD_CONST(0x3, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_MUL			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_ALU			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_BOTH			_MK_ENUM_CONST(0x2)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT			_MK_SHIFT_CONST(3)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_ONE_BYTE			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_TWO_BYTE			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT			_MK_SHIFT_CONST(4)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_KERNEL			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_ELEMENT			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(5)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_CV			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_RDMA_D_BN_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0x8044)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT)
+
+
+// Register SDP_RDMA_D_BN_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0x8048)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register SDP_RDMA_D_BN_LINE_STRIDE_0
+#define SDP_RDMA_D_BN_LINE_STRIDE_0			_MK_ADDR_CONST(0x804c)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_BN_SURFACE_STRIDE_0
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0			_MK_ADDR_CONST(0x8050)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_BN_BATCH_STRIDE_0
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0			_MK_ADDR_CONST(0x8054)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_ERDMA_CFG_0
+#define SDP_RDMA_D_ERDMA_CFG_0			_MK_ADDR_CONST(0x8058)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_NO			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_YES			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_FIELD			_MK_FIELD_CONST(0x3, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_MUL			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_ALU			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_BOTH			_MK_ENUM_CONST(0x2)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT			_MK_SHIFT_CONST(3)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_ONE_BYTE			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_TWO_BYTE			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT			_MK_SHIFT_CONST(4)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_KERNEL			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_ELEMENT			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(5)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_CV			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_RDMA_D_EW_BASE_ADDR_LOW_0
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0x805c)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT)
+
+
+// Register SDP_RDMA_D_EW_BASE_ADDR_HIGH_0
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0x8060)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register SDP_RDMA_D_EW_LINE_STRIDE_0
+#define SDP_RDMA_D_EW_LINE_STRIDE_0			_MK_ADDR_CONST(0x8064)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_EW_SURFACE_STRIDE_0
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0			_MK_ADDR_CONST(0x8068)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_EW_BATCH_STRIDE_0
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0			_MK_ADDR_CONST(0x806c)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT)
+
+
+// Register SDP_RDMA_D_FEATURE_MODE_CFG_0
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0			_MK_ADDR_CONST(0x8070)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_ON			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT			_MK_SHIFT_CONST(2)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FIELD			_MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT			_MK_SHIFT_CONST(4)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FIELD			_MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT			_MK_SHIFT_CONST(6)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FIELD			_MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT			_MK_SHIFT_CONST(8)
+#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD			_MK_FIELD_CONST(0x1f, SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT)
+
+
+// Register SDP_RDMA_D_SRC_DMA_CFG_0
+#define SDP_RDMA_D_SRC_DMA_CFG_0			_MK_ADDR_CONST(0x8074)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0			_MK_ADDR_CONST(0x8078)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT)
+
+
+// Register SDP_RDMA_D_STATUS_INF_INPUT_NUM_0
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0			_MK_ADDR_CONST(0x807c)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT)
+
+
+// Register SDP_RDMA_D_PERF_ENABLE_0
+#define SDP_RDMA_D_PERF_ENABLE_0			_MK_ADDR_CONST(0x8080)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_NO			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_YES			_MK_ENUM_CONST(0x1)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD			_MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO			_MK_ENUM_CONST(0x0)
+#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_RDMA_D_PERF_MRDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0			_MK_ADDR_CONST(0x8084)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT)
+
+
+// Register SDP_RDMA_D_PERF_BRDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0			_MK_ADDR_CONST(0x8088)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT)
+
+
+// Register SDP_RDMA_D_PERF_NRDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0			_MK_ADDR_CONST(0x808c)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT)
+
+
+// Register SDP_RDMA_D_PERF_ERDMA_READ_STALL_0
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0			_MK_ADDR_CONST(0x8090)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register SDP_S_STATUS_0
+#define SDP_S_STATUS_0			_MK_ADDR_CONST(0x9000)
+#define SDP_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_0_SHIFT)
+#define SDP_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define SDP_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define SDP_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define SDP_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define SDP_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_1_SHIFT)
+#define SDP_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define SDP_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define SDP_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register SDP_S_POINTER_0
+#define SDP_S_POINTER_0			_MK_ADDR_CONST(0x9004)
+#define SDP_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, SDP_S_POINTER_0_PRODUCER_SHIFT)
+#define SDP_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define SDP_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define SDP_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define SDP_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, SDP_S_POINTER_0_CONSUMER_SHIFT)
+#define SDP_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define SDP_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_S_LUT_ACCESS_CFG_0
+#define SDP_S_LUT_ACCESS_CFG_0			_MK_ADDR_CONST(0x9008)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD			_MK_FIELD_CONST(0x3ff, SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT			_MK_SHIFT_CONST(16)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD			_MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE			_MK_ENUM_CONST(0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO			_MK_ENUM_CONST(0x1)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT			_MK_SHIFT_CONST(17)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD			_MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ			_MK_ENUM_CONST(0x0)
+#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_S_LUT_ACCESS_DATA_0
+#define SDP_S_LUT_ACCESS_DATA_0			_MK_ADDR_CONST(0x900c)
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD			_MK_FIELD_CONST(0xffff, SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT)
+
+
+// Register SDP_S_LUT_CFG_0
+#define SDP_S_LUT_CFG_0			_MK_ADDR_CONST(0x9010)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD			_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT			_MK_ENUM_CONST(0x0)
+#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR			_MK_ENUM_CONST(0x1)
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT			_MK_SHIFT_CONST(4)
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD			_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT)
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE			_MK_ENUM_CONST(0x0)
+#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO			_MK_ENUM_CONST(0x1)
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT			_MK_SHIFT_CONST(5)
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD			_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT)
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE			_MK_ENUM_CONST(0x0)
+#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO			_MK_ENUM_CONST(0x1)
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT			_MK_SHIFT_CONST(6)
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD			_MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT)
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE			_MK_ENUM_CONST(0x0)
+#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_S_LUT_INFO_0
+#define SDP_S_LUT_INFO_0			_MK_ADDR_CONST(0x9014)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD			_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT			_MK_SHIFT_CONST(8)
+#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD			_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT)
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT			_MK_SHIFT_CONST(16)
+#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD			_MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT)
+
+
+// Register SDP_S_LUT_LE_START_0
+#define SDP_S_LUT_LE_START_0			_MK_ADDR_CONST(0x9018)
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_LE_START_0_LUT_LE_START_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT)
+
+
+// Register SDP_S_LUT_LE_END_0
+#define SDP_S_LUT_LE_END_0			_MK_ADDR_CONST(0x901c)
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_LE_END_0_LUT_LE_END_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT)
+
+
+// Register SDP_S_LUT_LO_START_0
+#define SDP_S_LUT_LO_START_0			_MK_ADDR_CONST(0x9020)
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_LO_START_0_LUT_LO_START_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT)
+
+
+// Register SDP_S_LUT_LO_END_0
+#define SDP_S_LUT_LO_END_0			_MK_ADDR_CONST(0x9024)
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_LO_END_0_LUT_LO_END_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT)
+
+
+// Register SDP_S_LUT_LE_SLOPE_SCALE_0
+#define SDP_S_LUT_LE_SLOPE_SCALE_0			_MK_ADDR_CONST(0x9028)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD			_MK_FIELD_CONST(0xffff, SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT			_MK_SHIFT_CONST(16)
+#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD			_MK_FIELD_CONST(0xffff, SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT)
+
+
+// Register SDP_S_LUT_LE_SLOPE_SHIFT_0
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0			_MK_ADDR_CONST(0x902c)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD			_MK_FIELD_CONST(0x1f, SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT			_MK_SHIFT_CONST(5)
+#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD			_MK_FIELD_CONST(0x1f, SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT)
+
+
+// Register SDP_S_LUT_LO_SLOPE_SCALE_0
+#define SDP_S_LUT_LO_SLOPE_SCALE_0			_MK_ADDR_CONST(0x9030)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD			_MK_FIELD_CONST(0xffff, SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT			_MK_SHIFT_CONST(16)
+#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD			_MK_FIELD_CONST(0xffff, SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT)
+
+
+// Register SDP_S_LUT_LO_SLOPE_SHIFT_0
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0			_MK_ADDR_CONST(0x9034)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD			_MK_FIELD_CONST(0x1f, SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT			_MK_SHIFT_CONST(5)
+#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD			_MK_FIELD_CONST(0x1f, SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT)
+
+
+// Register SDP_D_OP_ENABLE_0
+#define SDP_D_OP_ENABLE_0			_MK_ADDR_CONST(0x9038)
+#define SDP_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, SDP_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define SDP_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define SDP_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_D_DATA_CUBE_WIDTH_0
+#define SDP_D_DATA_CUBE_WIDTH_0			_MK_ADDR_CONST(0x903c)
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT)
+
+
+// Register SDP_D_DATA_CUBE_HEIGHT_0
+#define SDP_D_DATA_CUBE_HEIGHT_0			_MK_ADDR_CONST(0x9040)
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT)
+
+
+// Register SDP_D_DATA_CUBE_CHANNEL_0
+#define SDP_D_DATA_CUBE_CHANNEL_0			_MK_ADDR_CONST(0x9044)
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT)
+
+
+// Register SDP_D_DST_BASE_ADDR_LOW_0
+#define SDP_D_DST_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0x9048)
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT)
+
+
+// Register SDP_D_DST_BASE_ADDR_HIGH_0
+#define SDP_D_DST_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0x904c)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register SDP_D_DST_LINE_STRIDE_0
+#define SDP_D_DST_LINE_STRIDE_0			_MK_ADDR_CONST(0x9050)
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT)
+
+
+// Register SDP_D_DST_SURFACE_STRIDE_0
+#define SDP_D_DST_SURFACE_STRIDE_0			_MK_ADDR_CONST(0x9054)
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT)
+
+
+// Register SDP_D_DP_BS_CFG_0
+#define SDP_D_DP_BS_CFG_0			_MK_ADDR_CONST(0x9058)
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT)
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BS_CFG_0_BS_BYPASS_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT			_MK_SHIFT_CONST(2)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_FIELD			_MK_FIELD_CONST(0x3, SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MAX			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MIN			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SUM			_MK_ENUM_CONST(0x2)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT			_MK_SHIFT_CONST(4)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT			_MK_SHIFT_CONST(5)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT			_MK_SHIFT_CONST(6)
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT)
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_D_DP_BS_ALU_CFG_0
+#define SDP_D_DP_BS_ALU_CFG_0			_MK_ADDR_CONST(0x905c)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_REG			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_MEM			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT			_MK_SHIFT_CONST(8)
+#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_FIELD			_MK_FIELD_CONST(0x3f, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT)
+
+
+// Register SDP_D_DP_BS_ALU_SRC_VALUE_0
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0			_MK_ADDR_CONST(0x9060)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_FIELD			_MK_FIELD_CONST(0xffff, SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT)
+
+
+// Register SDP_D_DP_BS_MUL_CFG_0
+#define SDP_D_DP_BS_MUL_CFG_0			_MK_ADDR_CONST(0x9064)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_REG			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_MEM			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT			_MK_SHIFT_CONST(8)
+#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_FIELD			_MK_FIELD_CONST(0xff, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT)
+
+
+// Register SDP_D_DP_BS_MUL_SRC_VALUE_0
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0			_MK_ADDR_CONST(0x9068)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_FIELD			_MK_FIELD_CONST(0xffff, SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT)
+
+
+// Register SDP_D_DP_BN_CFG_0
+#define SDP_D_DP_BN_CFG_0			_MK_ADDR_CONST(0x906c)
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT)
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BN_CFG_0_BN_BYPASS_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT			_MK_SHIFT_CONST(2)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_FIELD			_MK_FIELD_CONST(0x3, SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MAX			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MIN			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SUM			_MK_ENUM_CONST(0x2)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT			_MK_SHIFT_CONST(4)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT			_MK_SHIFT_CONST(5)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT			_MK_SHIFT_CONST(6)
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT)
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_D_DP_BN_ALU_CFG_0
+#define SDP_D_DP_BN_ALU_CFG_0			_MK_ADDR_CONST(0x9070)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_REG			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_MEM			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT			_MK_SHIFT_CONST(8)
+#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_FIELD			_MK_FIELD_CONST(0x3f, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT)
+
+
+// Register SDP_D_DP_BN_ALU_SRC_VALUE_0
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0			_MK_ADDR_CONST(0x9074)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_FIELD			_MK_FIELD_CONST(0xffff, SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT)
+
+
+// Register SDP_D_DP_BN_MUL_CFG_0
+#define SDP_D_DP_BN_MUL_CFG_0			_MK_ADDR_CONST(0x9078)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_REG			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_MEM			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT			_MK_SHIFT_CONST(8)
+#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_FIELD			_MK_FIELD_CONST(0xff, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT)
+
+
+// Register SDP_D_DP_BN_MUL_SRC_VALUE_0
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0			_MK_ADDR_CONST(0x907c)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_FIELD			_MK_FIELD_CONST(0xffff, SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT)
+
+
+// Register SDP_D_DP_EW_CFG_0
+#define SDP_D_DP_EW_CFG_0			_MK_ADDR_CONST(0x9080)
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT)
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_CFG_0_EW_BYPASS_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT			_MK_SHIFT_CONST(2)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_FIELD			_MK_FIELD_CONST(0x3, SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MAX			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MIN			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SUM			_MK_ENUM_CONST(0x2)
+#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_EQL			_MK_ENUM_CONST(0x3)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT			_MK_SHIFT_CONST(4)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT			_MK_SHIFT_CONST(5)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT			_MK_SHIFT_CONST(6)
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT)
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_D_DP_EW_ALU_CFG_0
+#define SDP_D_DP_EW_ALU_CFG_0			_MK_ADDR_CONST(0x9084)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_REG			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_MEM			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_D_DP_EW_ALU_SRC_VALUE_0
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0			_MK_ADDR_CONST(0x9088)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT)
+
+
+// Register SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0			_MK_ADDR_CONST(0x908c)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT)
+
+
+// Register SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0			_MK_ADDR_CONST(0x9090)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_FIELD			_MK_FIELD_CONST(0xffff, SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT)
+
+
+// Register SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0			_MK_ADDR_CONST(0x9094)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_FIELD			_MK_FIELD_CONST(0x3f, SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT)
+
+
+// Register SDP_D_DP_EW_MUL_CFG_0
+#define SDP_D_DP_EW_MUL_CFG_0			_MK_ADDR_CONST(0x9098)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_REG			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_MEM			_MK_ENUM_CONST(0x1)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_D_DP_EW_MUL_SRC_VALUE_0
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0			_MK_ADDR_CONST(0x909c)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT)
+
+
+// Register SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0			_MK_ADDR_CONST(0x90a0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT)
+
+
+// Register SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0			_MK_ADDR_CONST(0x90a4)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_FIELD			_MK_FIELD_CONST(0xffff, SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT)
+
+
+// Register SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0			_MK_ADDR_CONST(0x90a8)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_FIELD			_MK_FIELD_CONST(0x3f, SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT)
+
+
+// Register SDP_D_DP_EW_TRUNCATE_VALUE_0
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0			_MK_ADDR_CONST(0x90ac)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_FIELD			_MK_FIELD_CONST(0x3ff, SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT)
+
+
+// Register SDP_D_FEATURE_MODE_CFG_0
+#define SDP_D_FEATURE_MODE_CFG_0			_MK_ADDR_CONST(0x90b0)
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD			_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT)
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF			_MK_ENUM_CONST(0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON			_MK_ENUM_CONST(0x1)
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_FIELD			_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT)
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_MEM			_MK_ENUM_CONST(0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PDP			_MK_ENUM_CONST(0x1)
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT			_MK_SHIFT_CONST(2)
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD			_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT)
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF			_MK_ENUM_CONST(0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_ON			_MK_ENUM_CONST(0x1)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT			_MK_SHIFT_CONST(3)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_FIELD			_MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DISABLE			_MK_ENUM_CONST(0x0)
+#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_ENABLE			_MK_ENUM_CONST(0x1)
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT			_MK_SHIFT_CONST(8)
+#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD			_MK_FIELD_CONST(0x1f, SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT)
+
+
+// Register SDP_D_DST_DMA_CFG_0
+#define SDP_D_DST_DMA_CFG_0			_MK_ADDR_CONST(0x90b4)
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT)
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV			_MK_ENUM_CONST(0x0)
+#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_D_DST_BATCH_STRIDE_0
+#define SDP_D_DST_BATCH_STRIDE_0			_MK_ADDR_CONST(0x90b8)
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT)
+
+
+// Register SDP_D_DATA_FORMAT_0
+#define SDP_D_DATA_FORMAT_0			_MK_ADDR_CONST(0x90bc)
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FIELD			_MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT)
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT			_MK_SHIFT_CONST(2)
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FIELD			_MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT)
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+
+
+// Register SDP_D_CVT_OFFSET_0
+#define SDP_D_CVT_OFFSET_0			_MK_ADDR_CONST(0x90c0)
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT)
+
+
+// Register SDP_D_CVT_SCALE_0
+#define SDP_D_CVT_SCALE_0			_MK_ADDR_CONST(0x90c4)
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_CVT_SCALE_0_CVT_SCALE_FIELD			_MK_FIELD_CONST(0xffff, SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT)
+
+
+// Register SDP_D_CVT_SHIFT_0
+#define SDP_D_CVT_SHIFT_0			_MK_ADDR_CONST(0x90c8)
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_FIELD			_MK_FIELD_CONST(0x3f, SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT)
+
+
+// Register SDP_D_STATUS_0
+#define SDP_D_STATUS_0			_MK_ADDR_CONST(0x90cc)
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_STATUS_0_STATUS_UNEQUAL_FIELD			_MK_FIELD_CONST(0x1, SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT)
+
+
+// Register SDP_D_STATUS_NAN_INPUT_NUM_0
+#define SDP_D_STATUS_NAN_INPUT_NUM_0			_MK_ADDR_CONST(0x90d0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT)
+
+
+// Register SDP_D_STATUS_INF_INPUT_NUM_0
+#define SDP_D_STATUS_INF_INPUT_NUM_0			_MK_ADDR_CONST(0x90d4)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT)
+
+
+// Register SDP_D_STATUS_NAN_OUTPUT_NUM_0
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0			_MK_ADDR_CONST(0x90d8)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT)
+
+
+// Register SDP_D_PERF_ENABLE_0
+#define SDP_D_PERF_ENABLE_0			_MK_ADDR_CONST(0x90dc)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD			_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT			_MK_SHIFT_CONST(1)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_FIELD			_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT			_MK_SHIFT_CONST(2)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_FIELD			_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_YES			_MK_ENUM_CONST(0x1)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT			_MK_SHIFT_CONST(3)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD			_MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO			_MK_ENUM_CONST(0x0)
+#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register SDP_D_PERF_WDMA_WRITE_STALL_0
+#define SDP_D_PERF_WDMA_WRITE_STALL_0			_MK_ADDR_CONST(0x90e0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT)
+
+
+// Register SDP_D_PERF_LUT_UFLOW_0
+#define SDP_D_PERF_LUT_UFLOW_0			_MK_ADDR_CONST(0x90e4)
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT)
+
+
+// Register SDP_D_PERF_LUT_OFLOW_0
+#define SDP_D_PERF_LUT_OFLOW_0			_MK_ADDR_CONST(0x90e8)
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT)
+
+
+// Register SDP_D_PERF_OUT_SATURATION_0
+#define SDP_D_PERF_OUT_SATURATION_0			_MK_ADDR_CONST(0x90ec)
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT)
+
+
+// Register SDP_D_PERF_LUT_HYBRID_0
+#define SDP_D_PERF_LUT_HYBRID_0			_MK_ADDR_CONST(0x90f0)
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT)
+
+
+// Register SDP_D_PERF_LUT_LE_HIT_0
+#define SDP_D_PERF_LUT_LE_HIT_0			_MK_ADDR_CONST(0x90f4)
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT)
+
+
+// Register SDP_D_PERF_LUT_LO_HIT_0
+#define SDP_D_PERF_LUT_LO_HIT_0			_MK_ADDR_CONST(0x90f8)
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT			_MK_SHIFT_CONST(0)
+#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_FIELD			_MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register PDP_RDMA_S_STATUS_0
+#define PDP_RDMA_S_STATUS_0			_MK_ADDR_CONST(0xa000)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define PDP_RDMA_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define PDP_RDMA_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register PDP_RDMA_S_POINTER_0
+#define PDP_RDMA_S_POINTER_0			_MK_ADDR_CONST(0xa004)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_RDMA_D_OP_ENABLE_0
+#define PDP_RDMA_D_OP_ENABLE_0			_MK_ADDR_CONST(0xa008)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0			_MK_ADDR_CONST(0xa00c)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT)
+
+
+// Register PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0			_MK_ADDR_CONST(0xa010)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT)
+
+
+// Register PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0			_MK_ADDR_CONST(0xa014)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT)
+
+
+// Register PDP_RDMA_D_FLYING_MODE_0
+#define PDP_RDMA_D_FLYING_MODE_0			_MK_ADDR_CONST(0xa018)
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_FIELD			_MK_FIELD_CONST(0x1, PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT)
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_ON_FLYING			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_OFF_FLYING			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_RDMA_D_SRC_BASE_ADDR_LOW_0
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0xa01c)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT)
+
+
+// Register PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0xa020)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register PDP_RDMA_D_SRC_LINE_STRIDE_0
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0			_MK_ADDR_CONST(0xa024)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT)
+
+
+// Register PDP_RDMA_D_SRC_SURFACE_STRIDE_0
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0			_MK_ADDR_CONST(0xa028)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT)
+
+
+// Register PDP_RDMA_D_SRC_RAM_CFG_0
+#define PDP_RDMA_D_SRC_RAM_CFG_0			_MK_ADDR_CONST(0xa02c)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_CV			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_RDMA_D_DATA_FORMAT_0
+#define PDP_RDMA_D_DATA_FORMAT_0			_MK_ADDR_CONST(0xa030)
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD			_MK_FIELD_CONST(0x3, PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT)
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16			_MK_ENUM_CONST(0x1)
+#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16			_MK_ENUM_CONST(0x2)
+
+
+// Register PDP_RDMA_D_OPERATION_MODE_CFG_0
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0			_MK_ADDR_CONST(0xa034)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD			_MK_FIELD_CONST(0xff, PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT)
+
+
+// Register PDP_RDMA_D_POOLING_KERNEL_CFG_0
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0			_MK_ADDR_CONST(0xa038)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD			_MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2			_MK_ENUM_CONST(0x1)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3			_MK_ENUM_CONST(0x2)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4			_MK_ENUM_CONST(0x3)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5			_MK_ENUM_CONST(0x4)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6			_MK_ENUM_CONST(0x5)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7			_MK_ENUM_CONST(0x6)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8			_MK_ENUM_CONST(0x7)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT			_MK_SHIFT_CONST(4)
+#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD			_MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT)
+
+
+// Register PDP_RDMA_D_POOLING_PADDING_CFG_0
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0			_MK_ADDR_CONST(0xa03c)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_FIELD			_MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT)
+
+
+// Register PDP_RDMA_D_PARTIAL_WIDTH_IN_0
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0			_MK_ADDR_CONST(0xa040)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD			_MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT			_MK_SHIFT_CONST(10)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD			_MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT			_MK_SHIFT_CONST(20)
+#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD			_MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT)
+
+
+// Register PDP_RDMA_D_PERF_ENABLE_0
+#define PDP_RDMA_D_PERF_ENABLE_0			_MK_ADDR_CONST(0xa044)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD			_MK_FIELD_CONST(0x1, PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_RDMA_D_PERF_READ_STALL_0
+#define PDP_RDMA_D_PERF_READ_STALL_0			_MK_ADDR_CONST(0xa048)
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT)
+
+
+// Register PDP_RDMA_D_CYA_0
+#define PDP_RDMA_D_CYA_0			_MK_ADDR_CONST(0xa04c)
+#define PDP_RDMA_D_CYA_0_CYA_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_RDMA_D_CYA_0_CYA_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_CYA_0_CYA_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register PDP_S_STATUS_0
+#define PDP_S_STATUS_0			_MK_ADDR_CONST(0xb000)
+#define PDP_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_0_SHIFT)
+#define PDP_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define PDP_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define PDP_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define PDP_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define PDP_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_1_SHIFT)
+#define PDP_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define PDP_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define PDP_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register PDP_S_POINTER_0
+#define PDP_S_POINTER_0			_MK_ADDR_CONST(0xb004)
+#define PDP_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, PDP_S_POINTER_0_PRODUCER_SHIFT)
+#define PDP_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define PDP_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define PDP_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define PDP_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, PDP_S_POINTER_0_CONSUMER_SHIFT)
+#define PDP_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define PDP_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_D_OP_ENABLE_0
+#define PDP_D_OP_ENABLE_0			_MK_ADDR_CONST(0xb008)
+#define PDP_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, PDP_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define PDP_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define PDP_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_D_DATA_CUBE_IN_WIDTH_0
+#define PDP_D_DATA_CUBE_IN_WIDTH_0			_MK_ADDR_CONST(0xb00c)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT)
+
+
+// Register PDP_D_DATA_CUBE_IN_HEIGHT_0
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0			_MK_ADDR_CONST(0xb010)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT)
+
+
+// Register PDP_D_DATA_CUBE_IN_CHANNEL_0
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0			_MK_ADDR_CONST(0xb014)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT)
+
+
+// Register PDP_D_DATA_CUBE_OUT_WIDTH_0
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0			_MK_ADDR_CONST(0xb018)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT)
+
+
+// Register PDP_D_DATA_CUBE_OUT_HEIGHT_0
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0			_MK_ADDR_CONST(0xb01c)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT)
+
+
+// Register PDP_D_DATA_CUBE_OUT_CHANNEL_0
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0			_MK_ADDR_CONST(0xb020)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT)
+
+
+// Register PDP_D_OPERATION_MODE_CFG_0
+#define PDP_D_OPERATION_MODE_CFG_0			_MK_ADDR_CONST(0xb024)
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_FIELD			_MK_FIELD_CONST(0x3, PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT)
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE			_MK_ENUM_CONST(0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX			_MK_ENUM_CONST(0x1)
+#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN			_MK_ENUM_CONST(0x2)
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT			_MK_SHIFT_CONST(4)
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_FIELD			_MK_FIELD_CONST(0x1, PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT)
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING			_MK_ENUM_CONST(0x0)
+#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING			_MK_ENUM_CONST(0x1)
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT			_MK_SHIFT_CONST(8)
+#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD			_MK_FIELD_CONST(0xff, PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT)
+
+
+// Register PDP_D_NAN_FLUSH_TO_ZERO_0
+#define PDP_D_NAN_FLUSH_TO_ZERO_0			_MK_ADDR_CONST(0xb028)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD			_MK_FIELD_CONST(0x1, PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE			_MK_ENUM_CONST(0x0)
+#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_D_PARTIAL_WIDTH_IN_0
+#define PDP_D_PARTIAL_WIDTH_IN_0			_MK_ADDR_CONST(0xb02c)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD			_MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT			_MK_SHIFT_CONST(10)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD			_MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT			_MK_SHIFT_CONST(20)
+#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD			_MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT)
+
+
+// Register PDP_D_PARTIAL_WIDTH_OUT_0
+#define PDP_D_PARTIAL_WIDTH_OUT_0			_MK_ADDR_CONST(0xb030)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_FIELD			_MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT			_MK_SHIFT_CONST(10)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_FIELD			_MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT			_MK_SHIFT_CONST(20)
+#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_FIELD			_MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT)
+
+
+// Register PDP_D_POOLING_KERNEL_CFG_0
+#define PDP_D_POOLING_KERNEL_CFG_0			_MK_ADDR_CONST(0xb034)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD			_MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1			_MK_ENUM_CONST(0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2			_MK_ENUM_CONST(0x1)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3			_MK_ENUM_CONST(0x2)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4			_MK_ENUM_CONST(0x3)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5			_MK_ENUM_CONST(0x4)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6			_MK_ENUM_CONST(0x5)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7			_MK_ENUM_CONST(0x6)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8			_MK_ENUM_CONST(0x7)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT			_MK_SHIFT_CONST(8)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_FIELD			_MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_1			_MK_ENUM_CONST(0x0)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_2			_MK_ENUM_CONST(0x1)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_3			_MK_ENUM_CONST(0x2)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_4			_MK_ENUM_CONST(0x3)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_5			_MK_ENUM_CONST(0x4)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_6			_MK_ENUM_CONST(0x5)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_7			_MK_ENUM_CONST(0x6)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_8			_MK_ENUM_CONST(0x7)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT			_MK_SHIFT_CONST(16)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD			_MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT			_MK_SHIFT_CONST(20)
+#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_FIELD			_MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT)
+
+
+// Register PDP_D_RECIP_KERNEL_WIDTH_0
+#define PDP_D_RECIP_KERNEL_WIDTH_0			_MK_ADDR_CONST(0xb038)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_FIELD			_MK_FIELD_CONST(0x1ffff, PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT)
+
+
+// Register PDP_D_RECIP_KERNEL_HEIGHT_0
+#define PDP_D_RECIP_KERNEL_HEIGHT_0			_MK_ADDR_CONST(0xb03c)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_FIELD			_MK_FIELD_CONST(0x1ffff, PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT)
+
+
+// Register PDP_D_POOLING_PADDING_CFG_0
+#define PDP_D_POOLING_PADDING_CFG_0			_MK_ADDR_CONST(0xb040)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_FIELD			_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT			_MK_SHIFT_CONST(4)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_FIELD			_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT			_MK_SHIFT_CONST(8)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_FIELD			_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT			_MK_SHIFT_CONST(12)
+#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_FIELD			_MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT)
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_1_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0			_MK_ADDR_CONST(0xb044)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_FIELD			_MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT)
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_2_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0			_MK_ADDR_CONST(0xb048)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_FIELD			_MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT)
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_3_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0			_MK_ADDR_CONST(0xb04c)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_FIELD			_MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT)
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_4_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0			_MK_ADDR_CONST(0xb050)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_FIELD			_MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT)
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_5_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0			_MK_ADDR_CONST(0xb054)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_FIELD			_MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT)
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_6_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0			_MK_ADDR_CONST(0xb058)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_FIELD			_MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT)
+
+
+// Register PDP_D_POOLING_PADDING_VALUE_7_CFG_0
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0			_MK_ADDR_CONST(0xb05c)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_FIELD			_MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT)
+
+
+// Register PDP_D_SRC_BASE_ADDR_LOW_0
+#define PDP_D_SRC_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0xb060)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT)
+
+
+// Register PDP_D_SRC_BASE_ADDR_HIGH_0
+#define PDP_D_SRC_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0xb064)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register PDP_D_SRC_LINE_STRIDE_0
+#define PDP_D_SRC_LINE_STRIDE_0			_MK_ADDR_CONST(0xb068)
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT)
+
+
+// Register PDP_D_SRC_SURFACE_STRIDE_0
+#define PDP_D_SRC_SURFACE_STRIDE_0			_MK_ADDR_CONST(0xb06c)
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT)
+
+
+// Register PDP_D_DST_BASE_ADDR_LOW_0
+#define PDP_D_DST_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0xb070)
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT)
+
+
+// Register PDP_D_DST_BASE_ADDR_HIGH_0
+#define PDP_D_DST_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0xb074)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register PDP_D_DST_LINE_STRIDE_0
+#define PDP_D_DST_LINE_STRIDE_0			_MK_ADDR_CONST(0xb078)
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT)
+
+
+// Register PDP_D_DST_SURFACE_STRIDE_0
+#define PDP_D_DST_SURFACE_STRIDE_0			_MK_ADDR_CONST(0xb07c)
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT)
+
+
+// Register PDP_D_DST_RAM_CFG_0
+#define PDP_D_DST_RAM_CFG_0			_MK_ADDR_CONST(0xb080)
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT)
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_CV			_MK_ENUM_CONST(0x0)
+#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_D_DATA_FORMAT_0
+#define PDP_D_DATA_FORMAT_0			_MK_ADDR_CONST(0xb084)
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FIELD			_MK_FIELD_CONST(0x3, PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT)
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT8			_MK_ENUM_CONST(0x0)
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT16			_MK_ENUM_CONST(0x1)
+#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FP16			_MK_ENUM_CONST(0x2)
+
+
+// Register PDP_D_INF_INPUT_NUM_0
+#define PDP_D_INF_INPUT_NUM_0			_MK_ADDR_CONST(0xb088)
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT)
+
+
+// Register PDP_D_NAN_INPUT_NUM_0
+#define PDP_D_NAN_INPUT_NUM_0			_MK_ADDR_CONST(0xb08c)
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT)
+
+
+// Register PDP_D_NAN_OUTPUT_NUM_0
+#define PDP_D_NAN_OUTPUT_NUM_0			_MK_ADDR_CONST(0xb090)
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT)
+
+
+// Register PDP_D_PERF_ENABLE_0
+#define PDP_D_PERF_ENABLE_0			_MK_ADDR_CONST(0xb094)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_FIELD			_MK_FIELD_CONST(0x1, PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define PDP_D_PERF_ENABLE_0_DMA_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register PDP_D_PERF_WRITE_STALL_0
+#define PDP_D_PERF_WRITE_STALL_0			_MK_ADDR_CONST(0xb098)
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT)
+
+
+// Register PDP_D_CYA_0
+#define PDP_D_CYA_0			_MK_ADDR_CONST(0xb09c)
+#define PDP_D_CYA_0_CYA_SHIFT			_MK_SHIFT_CONST(0)
+#define PDP_D_CYA_0_CYA_FIELD			_MK_FIELD_CONST(0xffffffff, PDP_D_CYA_0_CYA_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register CDP_RDMA_S_STATUS_0
+#define CDP_RDMA_S_STATUS_0			_MK_ADDR_CONST(0xc000)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define CDP_RDMA_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define CDP_RDMA_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register CDP_RDMA_S_POINTER_0
+#define CDP_RDMA_S_POINTER_0			_MK_ADDR_CONST(0xc004)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_RDMA_D_OP_ENABLE_0
+#define CDP_RDMA_D_OP_ENABLE_0			_MK_ADDR_CONST(0xc008)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_RDMA_D_DATA_CUBE_WIDTH_0
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0			_MK_ADDR_CONST(0xc00c)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT)
+
+
+// Register CDP_RDMA_D_DATA_CUBE_HEIGHT_0
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0			_MK_ADDR_CONST(0xc010)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT)
+
+
+// Register CDP_RDMA_D_DATA_CUBE_CHANNEL_0
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0			_MK_ADDR_CONST(0xc014)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT)
+
+
+// Register CDP_RDMA_D_SRC_BASE_ADDR_LOW_0
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0xc018)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT)
+
+
+// Register CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0xc01c)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register CDP_RDMA_D_SRC_LINE_STRIDE_0
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0			_MK_ADDR_CONST(0xc020)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT)
+
+
+// Register CDP_RDMA_D_SRC_SURFACE_STRIDE_0
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0			_MK_ADDR_CONST(0xc024)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT)
+
+
+// Register CDP_RDMA_D_SRC_DMA_CFG_0
+#define CDP_RDMA_D_SRC_DMA_CFG_0			_MK_ADDR_CONST(0xc028)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_RDMA_D_SRC_COMPRESSION_EN_0
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0			_MK_ADDR_CONST(0xc02c)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_FIELD			_MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_RDMA_D_OPERATION_MODE_0
+#define CDP_RDMA_D_OPERATION_MODE_0			_MK_ADDR_CONST(0xc030)
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_FIELD			_MK_FIELD_CONST(0x3, CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT)
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_READPHILE			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WRITEPHILE			_MK_ENUM_CONST(0x1)
+#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_ORDINARY			_MK_ENUM_CONST(0x2)
+
+
+// Register CDP_RDMA_D_DATA_FORMAT_0
+#define CDP_RDMA_D_DATA_FORMAT_0			_MK_ADDR_CONST(0xc034)
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD			_MK_FIELD_CONST(0x3, CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT)
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16			_MK_ENUM_CONST(0x1)
+#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16			_MK_ENUM_CONST(0x2)
+
+
+// Register CDP_RDMA_D_PERF_ENABLE_0
+#define CDP_RDMA_D_PERF_ENABLE_0			_MK_ADDR_CONST(0xc038)
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD			_MK_FIELD_CONST(0x1, CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT)
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_RDMA_D_PERF_READ_STALL_0
+#define CDP_RDMA_D_PERF_READ_STALL_0			_MK_ADDR_CONST(0xc03c)
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT)
+
+
+// Register CDP_RDMA_D_CYA_0
+#define CDP_RDMA_D_CYA_0			_MK_ADDR_CONST(0xc040)
+#define CDP_RDMA_D_CYA_0_CYA_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_RDMA_D_CYA_0_CYA_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_CYA_0_CYA_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register CDP_S_STATUS_0
+#define CDP_S_STATUS_0			_MK_ADDR_CONST(0xd000)
+#define CDP_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_0_SHIFT)
+#define CDP_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define CDP_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define CDP_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define CDP_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define CDP_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_1_SHIFT)
+#define CDP_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define CDP_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define CDP_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register CDP_S_POINTER_0
+#define CDP_S_POINTER_0			_MK_ADDR_CONST(0xd004)
+#define CDP_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, CDP_S_POINTER_0_PRODUCER_SHIFT)
+#define CDP_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CDP_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define CDP_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define CDP_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, CDP_S_POINTER_0_CONSUMER_SHIFT)
+#define CDP_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define CDP_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_S_LUT_ACCESS_CFG_0
+#define CDP_S_LUT_ACCESS_CFG_0			_MK_ADDR_CONST(0xd008)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD			_MK_FIELD_CONST(0x3ff, CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT			_MK_SHIFT_CONST(16)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD			_MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE			_MK_ENUM_CONST(0x0)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO			_MK_ENUM_CONST(0x1)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT			_MK_SHIFT_CONST(17)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD			_MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ			_MK_ENUM_CONST(0x0)
+#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_S_LUT_ACCESS_DATA_0
+#define CDP_S_LUT_ACCESS_DATA_0			_MK_ADDR_CONST(0xd00c)
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD			_MK_FIELD_CONST(0xffff, CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT)
+
+
+// Register CDP_S_LUT_CFG_0
+#define CDP_S_LUT_CFG_0			_MK_ADDR_CONST(0xd010)
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD			_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT)
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT			_MK_ENUM_CONST(0x0)
+#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR			_MK_ENUM_CONST(0x1)
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT			_MK_SHIFT_CONST(4)
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD			_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT)
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE			_MK_ENUM_CONST(0x0)
+#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO			_MK_ENUM_CONST(0x1)
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT			_MK_SHIFT_CONST(5)
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD			_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT)
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE			_MK_ENUM_CONST(0x0)
+#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO			_MK_ENUM_CONST(0x1)
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT			_MK_SHIFT_CONST(6)
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD			_MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT)
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE			_MK_ENUM_CONST(0x0)
+#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_S_LUT_INFO_0
+#define CDP_S_LUT_INFO_0			_MK_ADDR_CONST(0xd014)
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD			_MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT)
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT			_MK_SHIFT_CONST(8)
+#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD			_MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT)
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT			_MK_SHIFT_CONST(16)
+#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD			_MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT)
+
+
+// Register CDP_S_LUT_LE_START_LOW_0
+#define CDP_S_LUT_LE_START_LOW_0			_MK_ADDR_CONST(0xd018)
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT)
+
+
+// Register CDP_S_LUT_LE_START_HIGH_0
+#define CDP_S_LUT_LE_START_HIGH_0			_MK_ADDR_CONST(0xd01c)
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_FIELD			_MK_FIELD_CONST(0x3f, CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT)
+
+
+// Register CDP_S_LUT_LE_END_LOW_0
+#define CDP_S_LUT_LE_END_LOW_0			_MK_ADDR_CONST(0xd020)
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT)
+
+
+// Register CDP_S_LUT_LE_END_HIGH_0
+#define CDP_S_LUT_LE_END_HIGH_0			_MK_ADDR_CONST(0xd024)
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_FIELD			_MK_FIELD_CONST(0x3f, CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT)
+
+
+// Register CDP_S_LUT_LO_START_LOW_0
+#define CDP_S_LUT_LO_START_LOW_0			_MK_ADDR_CONST(0xd028)
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT)
+
+
+// Register CDP_S_LUT_LO_START_HIGH_0
+#define CDP_S_LUT_LO_START_HIGH_0			_MK_ADDR_CONST(0xd02c)
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_FIELD			_MK_FIELD_CONST(0x3f, CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT)
+
+
+// Register CDP_S_LUT_LO_END_LOW_0
+#define CDP_S_LUT_LO_END_LOW_0			_MK_ADDR_CONST(0xd030)
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT)
+
+
+// Register CDP_S_LUT_LO_END_HIGH_0
+#define CDP_S_LUT_LO_END_HIGH_0			_MK_ADDR_CONST(0xd034)
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_FIELD			_MK_FIELD_CONST(0x3f, CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT)
+
+
+// Register CDP_S_LUT_LE_SLOPE_SCALE_0
+#define CDP_S_LUT_LE_SLOPE_SCALE_0			_MK_ADDR_CONST(0xd038)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD			_MK_FIELD_CONST(0xffff, CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT			_MK_SHIFT_CONST(16)
+#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD			_MK_FIELD_CONST(0xffff, CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT)
+
+
+// Register CDP_S_LUT_LE_SLOPE_SHIFT_0
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0			_MK_ADDR_CONST(0xd03c)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD			_MK_FIELD_CONST(0x1f, CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT			_MK_SHIFT_CONST(5)
+#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD			_MK_FIELD_CONST(0x1f, CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT)
+
+
+// Register CDP_S_LUT_LO_SLOPE_SCALE_0
+#define CDP_S_LUT_LO_SLOPE_SCALE_0			_MK_ADDR_CONST(0xd040)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD			_MK_FIELD_CONST(0xffff, CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT			_MK_SHIFT_CONST(16)
+#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD			_MK_FIELD_CONST(0xffff, CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT)
+
+
+// Register CDP_S_LUT_LO_SLOPE_SHIFT_0
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0			_MK_ADDR_CONST(0xd044)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD			_MK_FIELD_CONST(0x1f, CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT			_MK_SHIFT_CONST(5)
+#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD			_MK_FIELD_CONST(0x1f, CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT)
+
+
+// Register CDP_D_OP_ENABLE_0
+#define CDP_D_OP_ENABLE_0			_MK_ADDR_CONST(0xd048)
+#define CDP_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, CDP_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define CDP_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_D_FUNC_BYPASS_0
+#define CDP_D_FUNC_BYPASS_0			_MK_ADDR_CONST(0xd04c)
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_FIELD			_MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT)
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_ENABLE			_MK_ENUM_CONST(0x1)
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT			_MK_SHIFT_CONST(1)
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_FIELD			_MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT)
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_D_DST_BASE_ADDR_LOW_0
+#define CDP_D_DST_BASE_ADDR_LOW_0			_MK_ADDR_CONST(0xd050)
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT)
+
+
+// Register CDP_D_DST_BASE_ADDR_HIGH_0
+#define CDP_D_DST_BASE_ADDR_HIGH_0			_MK_ADDR_CONST(0xd054)
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT)
+
+
+// Register CDP_D_DST_LINE_STRIDE_0
+#define CDP_D_DST_LINE_STRIDE_0			_MK_ADDR_CONST(0xd058)
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT)
+
+
+// Register CDP_D_DST_SURFACE_STRIDE_0
+#define CDP_D_DST_SURFACE_STRIDE_0			_MK_ADDR_CONST(0xd05c)
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT)
+
+
+// Register CDP_D_DST_DMA_CFG_0
+#define CDP_D_DST_DMA_CFG_0			_MK_ADDR_CONST(0xd060)
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT)
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV			_MK_ENUM_CONST(0x0)
+#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_D_DST_COMPRESSION_EN_0
+#define CDP_D_DST_COMPRESSION_EN_0			_MK_ADDR_CONST(0xd064)
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_FIELD			_MK_FIELD_CONST(0x1, CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT)
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_D_DATA_FORMAT_0
+#define CDP_D_DATA_FORMAT_0			_MK_ADDR_CONST(0xd068)
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FIELD			_MK_FIELD_CONST(0x3, CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT)
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT8			_MK_ENUM_CONST(0x0)
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT16			_MK_ENUM_CONST(0x1)
+#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FP16			_MK_ENUM_CONST(0x2)
+
+
+// Register CDP_D_NAN_FLUSH_TO_ZERO_0
+#define CDP_D_NAN_FLUSH_TO_ZERO_0			_MK_ADDR_CONST(0xd06c)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD			_MK_FIELD_CONST(0x1, CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_D_LRN_CFG_0
+#define CDP_D_LRN_CFG_0			_MK_ADDR_CONST(0xd070)
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_FIELD			_MK_FIELD_CONST(0x3, CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT)
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN3			_MK_ENUM_CONST(0x0)
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN5			_MK_ENUM_CONST(0x1)
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN7			_MK_ENUM_CONST(0x2)
+#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9			_MK_ENUM_CONST(0x3)
+
+
+// Register CDP_D_DATIN_OFFSET_0
+#define CDP_D_DATIN_OFFSET_0			_MK_ADDR_CONST(0xd074)
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_FIELD			_MK_FIELD_CONST(0xffff, CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT)
+
+
+// Register CDP_D_DATIN_SCALE_0
+#define CDP_D_DATIN_SCALE_0			_MK_ADDR_CONST(0xd078)
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_FIELD			_MK_FIELD_CONST(0xffff, CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT)
+
+
+// Register CDP_D_DATIN_SHIFTER_0
+#define CDP_D_DATIN_SHIFTER_0			_MK_ADDR_CONST(0xd07c)
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_FIELD			_MK_FIELD_CONST(0x1f, CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT)
+
+
+// Register CDP_D_DATOUT_OFFSET_0
+#define CDP_D_DATOUT_OFFSET_0			_MK_ADDR_CONST(0xd080)
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT)
+
+
+// Register CDP_D_DATOUT_SCALE_0
+#define CDP_D_DATOUT_SCALE_0			_MK_ADDR_CONST(0xd084)
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_FIELD			_MK_FIELD_CONST(0xffff, CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT)
+
+
+// Register CDP_D_DATOUT_SHIFTER_0
+#define CDP_D_DATOUT_SHIFTER_0			_MK_ADDR_CONST(0xd088)
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_FIELD			_MK_FIELD_CONST(0x3f, CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT)
+
+
+// Register CDP_D_NAN_INPUT_NUM_0
+#define CDP_D_NAN_INPUT_NUM_0			_MK_ADDR_CONST(0xd08c)
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT)
+
+
+// Register CDP_D_INF_INPUT_NUM_0
+#define CDP_D_INF_INPUT_NUM_0			_MK_ADDR_CONST(0xd090)
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT)
+
+
+// Register CDP_D_NAN_OUTPUT_NUM_0
+#define CDP_D_NAN_OUTPUT_NUM_0			_MK_ADDR_CONST(0xd094)
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT)
+
+
+// Register CDP_D_OUT_SATURATION_0
+#define CDP_D_OUT_SATURATION_0			_MK_ADDR_CONST(0xd098)
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT)
+
+
+// Register CDP_D_PERF_ENABLE_0
+#define CDP_D_PERF_ENABLE_0			_MK_ADDR_CONST(0xd09c)
+#define CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_PERF_ENABLE_0_DMA_EN_FIELD			_MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT)
+#define CDP_D_PERF_ENABLE_0_DMA_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_D_PERF_ENABLE_0_DMA_EN_ENABLE			_MK_ENUM_CONST(0x1)
+#define CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT			_MK_SHIFT_CONST(1)
+#define CDP_D_PERF_ENABLE_0_LUT_EN_FIELD			_MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT)
+#define CDP_D_PERF_ENABLE_0_LUT_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define CDP_D_PERF_ENABLE_0_LUT_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register CDP_D_PERF_WRITE_STALL_0
+#define CDP_D_PERF_WRITE_STALL_0			_MK_ADDR_CONST(0xd0a0)
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT)
+
+
+// Register CDP_D_PERF_LUT_UFLOW_0
+#define CDP_D_PERF_LUT_UFLOW_0			_MK_ADDR_CONST(0xd0a4)
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT)
+
+
+// Register CDP_D_PERF_LUT_OFLOW_0
+#define CDP_D_PERF_LUT_OFLOW_0			_MK_ADDR_CONST(0xd0a8)
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT)
+
+
+// Register CDP_D_PERF_LUT_HYBRID_0
+#define CDP_D_PERF_LUT_HYBRID_0			_MK_ADDR_CONST(0xd0ac)
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT)
+
+
+// Register CDP_D_PERF_LUT_LE_HIT_0
+#define CDP_D_PERF_LUT_LE_HIT_0			_MK_ADDR_CONST(0xd0b0)
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT)
+
+
+// Register CDP_D_PERF_LUT_LO_HIT_0
+#define CDP_D_PERF_LUT_LO_HIT_0			_MK_ADDR_CONST(0xd0b4)
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT)
+
+
+// Register CDP_D_CYA_0
+#define CDP_D_CYA_0			_MK_ADDR_CONST(0xd0b8)
+#define CDP_D_CYA_0_CYA_SHIFT			_MK_SHIFT_CONST(0)
+#define CDP_D_CYA_0_CYA_FIELD			_MK_FIELD_CONST(0xffffffff, CDP_D_CYA_0_CYA_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register NVDLA_GEC_FEATURE_0
+#define NVDLA_GEC_FEATURE_0			_MK_ADDR_CONST(0xe000)
+#define NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_FIELD			_MK_FIELD_CONST(0x3f, NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_SHIFT)
+#define NVDLA_GEC_FEATURE_0_NUM_ERR_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_FEATURE_0_NUM_ERR_FIELD			_MK_FIELD_CONST(0xffff, NVDLA_GEC_FEATURE_0_NUM_ERR_SHIFT)
+
+
+// Register NVDLA_GEC_SWRESET_0
+#define NVDLA_GEC_SWRESET_0			_MK_ADDR_CONST(0xe004)
+#define NVDLA_GEC_SWRESET_0_SWRST_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_SWRESET_0_SWRST_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_SWRESET_0_SWRST_SHIFT)
+
+
+// Register NVDLA_GEC_MISSIONERR_TYPE_0
+#define NVDLA_GEC_MISSIONERR_TYPE_0			_MK_ADDR_CONST(0xe008)
+#define NVDLA_GEC_MISSIONERR_TYPE_0_CODE_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_MISSIONERR_TYPE_0_CODE_FIELD			_MK_FIELD_CONST(0x3f, NVDLA_GEC_MISSIONERR_TYPE_0_CODE_SHIFT)
+
+
+// Register NVDLA_GEC_CURRENT_COUNTER_VALUE_0
+#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0			_MK_ADDR_CONST(0xe00c)
+#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_FIELD			_MK_FIELD_CONST(0x1ff, NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
+
+
+// Register NVDLA_GEC_MISSIONERR_INDEX_0
+#define NVDLA_GEC_MISSIONERR_INDEX_0			_MK_ADDR_CONST(0xe014)
+#define NVDLA_GEC_MISSIONERR_INDEX_0_IDX_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_MISSIONERR_INDEX_0_IDX_FIELD			_MK_FIELD_CONST(0x7f, NVDLA_GEC_MISSIONERR_INDEX_0_IDX_SHIFT)
+
+
+// Register NVDLA_GEC_CORRECTABLE_THRESHOLD_0
+#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0			_MK_ADDR_CONST(0xe018)
+#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_FIELD			_MK_FIELD_CONST(0xff, NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
+
+
+// Register NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0
+#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0			_MK_ADDR_CONST(0xe01c)
+#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD			_MK_FIELD_CONST(0xff, NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
+#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK			_MK_ENUM_CONST(0xe1)
+
+
+// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0			_MK_ADDR_CONST(0xe030)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0			_MK_ADDR_CONST(0xe034)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_FORCE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0			_MK_ADDR_CONST(0xe038)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_SHIFT)
+
+
+// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0			_MK_ADDR_CONST(0xe03c)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0			_MK_ADDR_CONST(0xe040)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0			_MK_ADDR_CONST(0xe044)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_FORCE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0			_MK_ADDR_CONST(0xe048)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_SHIFT)
+
+
+// Register NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0			_MK_ADDR_CONST(0xe050)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_SHIFT)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_RELOAD			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0			_MK_ADDR_CONST(0xe060)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0			_MK_ADDR_CONST(0xe064)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_FORCE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0			_MK_ADDR_CONST(0xe068)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_SHIFT)
+
+
+// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0			_MK_ADDR_CONST(0xe06c)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0			_MK_ADDR_CONST(0xe070)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0			_MK_ADDR_CONST(0xe074)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_FORCE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0			_MK_ADDR_CONST(0xe078)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_SHIFT)
+
+
+// Register NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0			_MK_ADDR_CONST(0xe080)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_SHIFT			_MK_SHIFT_CONST(4)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_SHIFT			_MK_SHIFT_CONST(5)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_SHIFT			_MK_SHIFT_CONST(6)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_SHIFT			_MK_SHIFT_CONST(7)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_SHIFT			_MK_SHIFT_CONST(9)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_SHIFT			_MK_SHIFT_CONST(10)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_SHIFT			_MK_SHIFT_CONST(11)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_SHIFT			_MK_SHIFT_CONST(12)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_SHIFT			_MK_SHIFT_CONST(13)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_SHIFT			_MK_SHIFT_CONST(14)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_SHIFT			_MK_SHIFT_CONST(15)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_SHIFT			_MK_SHIFT_CONST(17)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_SHIFT			_MK_SHIFT_CONST(18)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_SHIFT			_MK_SHIFT_CONST(19)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_SHIFT			_MK_SHIFT_CONST(20)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_SHIFT			_MK_SHIFT_CONST(21)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_SHIFT			_MK_SHIFT_CONST(22)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_SHIFT			_MK_SHIFT_CONST(23)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_SHIFT			_MK_SHIFT_CONST(25)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_SHIFT			_MK_SHIFT_CONST(26)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_SHIFT			_MK_SHIFT_CONST(27)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_SHIFT			_MK_SHIFT_CONST(28)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_SHIFT			_MK_SHIFT_CONST(29)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_SHIFT			_MK_SHIFT_CONST(30)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_RELOAD			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0			_MK_ADDR_CONST(0xe084)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_SHIFT			_MK_SHIFT_CONST(31)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_SHIFT)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0			_MK_ADDR_CONST(0xe090)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0			_MK_ADDR_CONST(0xe094)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_FORCE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0			_MK_ADDR_CONST(0xe098)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_SHIFT)
+
+
+// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0			_MK_ADDR_CONST(0xe09c)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0			_MK_ADDR_CONST(0xe0a0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_ENABLE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_DISABLE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0			_MK_ADDR_CONST(0xe0a4)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_FORCE			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_NOFORCE			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_FORCE			_MK_ENUM_CONST(0x1)
+
+
+// Register NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0			_MK_ADDR_CONST(0xe0a8)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_SHIFT)
+
+
+// Register NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0			_MK_ADDR_CONST(0xe0b0)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_SHIFT			_MK_SHIFT_CONST(1)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_SHIFT			_MK_SHIFT_CONST(2)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_RELOAD			_MK_ENUM_CONST(0x1)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_SHIFT			_MK_SHIFT_CONST(3)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_FIELD			_MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_SHIFT)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_NORELOAD			_MK_ENUM_CONST(0x0)
+#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_RELOAD			_MK_ENUM_CONST(0x1)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register NVDLA_CVIF_CFG_RD_WEIGHT_0_0
+#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0			_MK_ADDR_CONST(0xf000)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT)
+
+
+// Register NVDLA_CVIF_CFG_RD_WEIGHT_1_0
+#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0			_MK_ADDR_CONST(0xf004)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT)
+
+
+// Register NVDLA_CVIF_CFG_RD_WEIGHT_2_0
+#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0			_MK_ADDR_CONST(0xf008)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT)
+
+
+// Register NVDLA_CVIF_CFG_WR_WEIGHT_0_0
+#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0			_MK_ADDR_CONST(0xf00c)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT)
+
+
+// Register NVDLA_CVIF_CFG_WR_WEIGHT_1_0
+#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0			_MK_ADDR_CONST(0xf010)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT			_MK_SHIFT_CONST(16)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT			_MK_SHIFT_CONST(24)
+#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT)
+
+
+// Register NVDLA_CVIF_CFG_OUTSTANDING_CNT_0
+#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0			_MK_ADDR_CONST(0xf014)
+#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT			_MK_SHIFT_CONST(0)
+#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT)
+#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD			_MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT)
+
+
+// Register NVDLA_CVIF_STATUS_0
+#define NVDLA_CVIF_STATUS_0			_MK_ADDR_CONST(0xf018)
+#define NVDLA_CVIF_STATUS_0_IDLE_SHIFT			_MK_SHIFT_CONST(8)
+#define NVDLA_CVIF_STATUS_0_IDLE_FIELD			_MK_FIELD_CONST(0x1, NVDLA_CVIF_STATUS_0_IDLE_SHIFT)
+#define NVDLA_CVIF_STATUS_0_IDLE_NO			_MK_ENUM_CONST(0x0)
+#define NVDLA_CVIF_STATUS_0_IDLE_YES			_MK_ENUM_CONST(0x1)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register BDMA_CFG_SRC_ADDR_LOW_0
+#define BDMA_CFG_SRC_ADDR_LOW_0			_MK_ADDR_CONST(0x10000)
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT			_MK_SHIFT_CONST(5)
+#define BDMA_CFG_SRC_ADDR_LOW_0_V32_FIELD			_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT)
+
+
+// Register BDMA_CFG_SRC_ADDR_HIGH_0
+#define BDMA_CFG_SRC_ADDR_HIGH_0			_MK_ADDR_CONST(0x10004)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_FIELD			_MK_FIELD_CONST(0xffffffff, BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT)
+
+
+// Register BDMA_CFG_DST_ADDR_LOW_0
+#define BDMA_CFG_DST_ADDR_LOW_0			_MK_ADDR_CONST(0x10008)
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT			_MK_SHIFT_CONST(5)
+#define BDMA_CFG_DST_ADDR_LOW_0_V32_FIELD			_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT)
+
+
+// Register BDMA_CFG_DST_ADDR_HIGH_0
+#define BDMA_CFG_DST_ADDR_HIGH_0			_MK_ADDR_CONST(0x1000c)
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_DST_ADDR_HIGH_0_V8_FIELD			_MK_FIELD_CONST(0xffffffff, BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT)
+
+
+// Register BDMA_CFG_LINE_0
+#define BDMA_CFG_LINE_0			_MK_ADDR_CONST(0x10010)
+#define BDMA_CFG_LINE_0_SIZE_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_LINE_0_SIZE_FIELD			_MK_FIELD_CONST(0x1fff, BDMA_CFG_LINE_0_SIZE_SHIFT)
+
+
+// Register BDMA_CFG_CMD_0
+#define BDMA_CFG_CMD_0			_MK_ADDR_CONST(0x10014)
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT)
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_CVSRAM			_MK_ENUM_CONST(0x0)
+#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(1)
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT)
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_CVSRAM			_MK_ENUM_CONST(0x0)
+#define BDMA_CFG_CMD_0_DST_RAM_TYPE_MC			_MK_ENUM_CONST(0x1)
+
+
+// Register BDMA_CFG_LINE_REPEAT_0
+#define BDMA_CFG_LINE_REPEAT_0			_MK_ADDR_CONST(0x10018)
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_LINE_REPEAT_0_NUMBER_FIELD			_MK_FIELD_CONST(0xffffff, BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT)
+
+
+// Register BDMA_CFG_SRC_LINE_0
+#define BDMA_CFG_SRC_LINE_0			_MK_ADDR_CONST(0x1001c)
+#define BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define BDMA_CFG_SRC_LINE_0_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT)
+
+
+// Register BDMA_CFG_DST_LINE_0
+#define BDMA_CFG_DST_LINE_0			_MK_ADDR_CONST(0x10020)
+#define BDMA_CFG_DST_LINE_0_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define BDMA_CFG_DST_LINE_0_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_LINE_0_STRIDE_SHIFT)
+
+
+// Register BDMA_CFG_SURF_REPEAT_0
+#define BDMA_CFG_SURF_REPEAT_0			_MK_ADDR_CONST(0x10024)
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_SURF_REPEAT_0_NUMBER_FIELD			_MK_FIELD_CONST(0xffffff, BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT)
+
+
+// Register BDMA_CFG_SRC_SURF_0
+#define BDMA_CFG_SRC_SURF_0			_MK_ADDR_CONST(0x10028)
+#define BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define BDMA_CFG_SRC_SURF_0_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT)
+
+
+// Register BDMA_CFG_DST_SURF_0
+#define BDMA_CFG_DST_SURF_0			_MK_ADDR_CONST(0x1002c)
+#define BDMA_CFG_DST_SURF_0_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define BDMA_CFG_DST_SURF_0_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_SURF_0_STRIDE_SHIFT)
+
+
+// Register BDMA_CFG_OP_0
+#define BDMA_CFG_OP_0			_MK_ADDR_CONST(0x10030)
+#define BDMA_CFG_OP_0_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_OP_0_EN_FIELD			_MK_FIELD_CONST(0x1, BDMA_CFG_OP_0_EN_SHIFT)
+#define BDMA_CFG_OP_0_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define BDMA_CFG_OP_0_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register BDMA_CFG_LAUNCH0_0
+#define BDMA_CFG_LAUNCH0_0			_MK_ADDR_CONST(0x10034)
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_FIELD			_MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT)
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_NO			_MK_ENUM_CONST(0x0)
+#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register BDMA_CFG_LAUNCH1_0
+#define BDMA_CFG_LAUNCH1_0			_MK_ADDR_CONST(0x10038)
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_FIELD			_MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT)
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_NO			_MK_ENUM_CONST(0x0)
+#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register BDMA_CFG_STATUS_0
+#define BDMA_CFG_STATUS_0			_MK_ADDR_CONST(0x1003c)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_FIELD			_MK_FIELD_CONST(0x1, BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_NO			_MK_ENUM_CONST(0x0)
+#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register BDMA_STATUS_0
+#define BDMA_STATUS_0			_MK_ADDR_CONST(0x10040)
+#define BDMA_STATUS_0_FREE_SLOT_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_STATUS_0_FREE_SLOT_FIELD			_MK_FIELD_CONST(0xff, BDMA_STATUS_0_FREE_SLOT_SHIFT)
+#define BDMA_STATUS_0_IDLE_SHIFT			_MK_SHIFT_CONST(8)
+#define BDMA_STATUS_0_IDLE_FIELD			_MK_FIELD_CONST(0x1, BDMA_STATUS_0_IDLE_SHIFT)
+#define BDMA_STATUS_0_IDLE_NO			_MK_ENUM_CONST(0x0)
+#define BDMA_STATUS_0_IDLE_YES			_MK_ENUM_CONST(0x1)
+#define BDMA_STATUS_0_GRP0_BUSY_SHIFT			_MK_SHIFT_CONST(9)
+#define BDMA_STATUS_0_GRP0_BUSY_FIELD			_MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP0_BUSY_SHIFT)
+#define BDMA_STATUS_0_GRP0_BUSY_NO			_MK_ENUM_CONST(0x0)
+#define BDMA_STATUS_0_GRP0_BUSY_YES			_MK_ENUM_CONST(0x1)
+#define BDMA_STATUS_0_GRP1_BUSY_SHIFT			_MK_SHIFT_CONST(10)
+#define BDMA_STATUS_0_GRP1_BUSY_FIELD			_MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP1_BUSY_SHIFT)
+#define BDMA_STATUS_0_GRP1_BUSY_NO			_MK_ENUM_CONST(0x0)
+#define BDMA_STATUS_0_GRP1_BUSY_YES			_MK_ENUM_CONST(0x1)
+
+
+// Register BDMA_STATUS_GRP0_READ_STALL_0
+#define BDMA_STATUS_GRP0_READ_STALL_0			_MK_ADDR_CONST(0x10044)
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_FIELD			_MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT)
+
+
+// Register BDMA_STATUS_GRP0_WRITE_STALL_0
+#define BDMA_STATUS_GRP0_WRITE_STALL_0			_MK_ADDR_CONST(0x10048)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_FIELD			_MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT)
+
+
+// Register BDMA_STATUS_GRP1_READ_STALL_0
+#define BDMA_STATUS_GRP1_READ_STALL_0			_MK_ADDR_CONST(0x1004c)
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_FIELD			_MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT)
+
+
+// Register BDMA_STATUS_GRP1_WRITE_STALL_0
+#define BDMA_STATUS_GRP1_WRITE_STALL_0			_MK_ADDR_CONST(0x10050)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT			_MK_SHIFT_CONST(0)
+#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_FIELD			_MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+// Register RBK_S_STATUS_0
+#define RBK_S_STATUS_0			_MK_ADDR_CONST(0x11000)
+#define RBK_S_STATUS_0_STATUS_0_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_S_STATUS_0_STATUS_0_FIELD			_MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_0_SHIFT)
+#define RBK_S_STATUS_0_STATUS_0_IDLE			_MK_ENUM_CONST(0x0)
+#define RBK_S_STATUS_0_STATUS_0_RUNNING			_MK_ENUM_CONST(0x1)
+#define RBK_S_STATUS_0_STATUS_0_PENDING			_MK_ENUM_CONST(0x2)
+#define RBK_S_STATUS_0_STATUS_1_SHIFT			_MK_SHIFT_CONST(16)
+#define RBK_S_STATUS_0_STATUS_1_FIELD			_MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_1_SHIFT)
+#define RBK_S_STATUS_0_STATUS_1_IDLE			_MK_ENUM_CONST(0x0)
+#define RBK_S_STATUS_0_STATUS_1_RUNNING			_MK_ENUM_CONST(0x1)
+#define RBK_S_STATUS_0_STATUS_1_PENDING			_MK_ENUM_CONST(0x2)
+
+
+// Register RBK_S_POINTER_0
+#define RBK_S_POINTER_0			_MK_ADDR_CONST(0x11004)
+#define RBK_S_POINTER_0_PRODUCER_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_S_POINTER_0_PRODUCER_FIELD			_MK_FIELD_CONST(0x1, RBK_S_POINTER_0_PRODUCER_SHIFT)
+#define RBK_S_POINTER_0_PRODUCER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define RBK_S_POINTER_0_PRODUCER_GROUP_1			_MK_ENUM_CONST(0x1)
+#define RBK_S_POINTER_0_CONSUMER_SHIFT			_MK_SHIFT_CONST(16)
+#define RBK_S_POINTER_0_CONSUMER_FIELD			_MK_FIELD_CONST(0x1, RBK_S_POINTER_0_CONSUMER_SHIFT)
+#define RBK_S_POINTER_0_CONSUMER_GROUP_0			_MK_ENUM_CONST(0x0)
+#define RBK_S_POINTER_0_CONSUMER_GROUP_1			_MK_ENUM_CONST(0x1)
+
+
+// Register RBK_D_OP_ENABLE_0
+#define RBK_D_OP_ENABLE_0			_MK_ADDR_CONST(0x11008)
+#define RBK_D_OP_ENABLE_0_OP_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_OP_ENABLE_0_OP_EN_FIELD			_MK_FIELD_CONST(0x1, RBK_D_OP_ENABLE_0_OP_EN_SHIFT)
+#define RBK_D_OP_ENABLE_0_OP_EN_DISABLE			_MK_ENUM_CONST(0x0)
+#define RBK_D_OP_ENABLE_0_OP_EN_ENABLE			_MK_ENUM_CONST(0x1)
+
+
+// Register RBK_D_MISC_CFG_0
+#define RBK_D_MISC_CFG_0			_MK_ADDR_CONST(0x1100c)
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_FIELD			_MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT)
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_CONTRACT			_MK_ENUM_CONST(0x0)
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_SPLIT			_MK_ENUM_CONST(0x1)
+#define RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE			_MK_ENUM_CONST(0x2)
+#define RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT			_MK_SHIFT_CONST(8)
+#define RBK_D_MISC_CFG_0_IN_PRECISION_FIELD			_MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT)
+#define RBK_D_MISC_CFG_0_IN_PRECISION_INT8			_MK_ENUM_CONST(0x0)
+#define RBK_D_MISC_CFG_0_IN_PRECISION_INT16			_MK_ENUM_CONST(0x1)
+#define RBK_D_MISC_CFG_0_IN_PRECISION_FP16			_MK_ENUM_CONST(0x2)
+
+
+// Register RBK_D_DAIN_RAM_TYPE_0
+#define RBK_D_DAIN_RAM_TYPE_0			_MK_ADDR_CONST(0x11010)
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT)
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF			_MK_ENUM_CONST(0x0)
+#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF			_MK_ENUM_CONST(0x1)
+
+
+// Register RBK_D_DATAIN_SIZE_0_0
+#define RBK_D_DATAIN_SIZE_0_0			_MK_ADDR_CONST(0x11014)
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD			_MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT)
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT			_MK_SHIFT_CONST(16)
+#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD			_MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT)
+
+
+// Register RBK_D_DATAIN_SIZE_1_0
+#define RBK_D_DATAIN_SIZE_1_0			_MK_ADDR_CONST(0x11018)
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT)
+
+
+// Register RBK_D_DAIN_ADDR_HIGH_0
+#define RBK_D_DAIN_ADDR_HIGH_0			_MK_ADDR_CONST(0x1101c)
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT)
+
+
+// Register RBK_D_DAIN_ADDR_LOW_0
+#define RBK_D_DAIN_ADDR_LOW_0			_MK_ADDR_CONST(0x11020)
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT)
+
+
+// Register RBK_D_DAIN_LINE_STRIDE_0
+#define RBK_D_DAIN_LINE_STRIDE_0			_MK_ADDR_CONST(0x11024)
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT)
+
+
+// Register RBK_D_DAIN_SURF_STRIDE_0
+#define RBK_D_DAIN_SURF_STRIDE_0			_MK_ADDR_CONST(0x11028)
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT)
+
+
+// Register RBK_D_DAIN_PLANAR_STRIDE_0
+#define RBK_D_DAIN_PLANAR_STRIDE_0			_MK_ADDR_CONST(0x1102c)
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT)
+
+
+// Register RBK_D_DAOUT_RAM_TYPE_0
+#define RBK_D_DAOUT_RAM_TYPE_0			_MK_ADDR_CONST(0x11030)
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_FIELD			_MK_FIELD_CONST(0x1, RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT)
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_CVIF			_MK_ENUM_CONST(0x0)
+#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_MCIF			_MK_ENUM_CONST(0x1)
+
+
+// Register RBK_D_DATAOUT_SIZE_1_0
+#define RBK_D_DATAOUT_SIZE_1_0			_MK_ADDR_CONST(0x11034)
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD			_MK_FIELD_CONST(0x1fff, RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT)
+
+
+// Register RBK_D_DAOUT_ADDR_HIGH_0
+#define RBK_D_DAOUT_ADDR_HIGH_0			_MK_ADDR_CONST(0x11038)
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_FIELD			_MK_FIELD_CONST(0xffffffff, RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT)
+
+
+// Register RBK_D_DAOUT_ADDR_LOW_0
+#define RBK_D_DAOUT_ADDR_LOW_0			_MK_ADDR_CONST(0x1103c)
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT)
+
+
+// Register RBK_D_DAOUT_LINE_STRIDE_0
+#define RBK_D_DAOUT_LINE_STRIDE_0			_MK_ADDR_CONST(0x11040)
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT)
+
+
+// Register RBK_D_CONTRACT_STRIDE_0_0
+#define RBK_D_CONTRACT_STRIDE_0_0			_MK_ADDR_CONST(0x11044)
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT)
+
+
+// Register RBK_D_CONTRACT_STRIDE_1_0
+#define RBK_D_CONTRACT_STRIDE_1_0			_MK_ADDR_CONST(0x11048)
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT)
+
+
+// Register RBK_D_DAOUT_SURF_STRIDE_0
+#define RBK_D_DAOUT_SURF_STRIDE_0			_MK_ADDR_CONST(0x1104c)
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT)
+
+
+// Register RBK_D_DAOUT_PLANAR_STRIDE_0
+#define RBK_D_DAOUT_PLANAR_STRIDE_0			_MK_ADDR_CONST(0x11050)
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT			_MK_SHIFT_CONST(5)
+#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_FIELD			_MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT)
+
+
+// Register RBK_D_DECONV_STRIDE_0
+#define RBK_D_DECONV_STRIDE_0			_MK_ADDR_CONST(0x11054)
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_FIELD			_MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT)
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT			_MK_SHIFT_CONST(16)
+#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_FIELD			_MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT)
+
+
+// Register RBK_D_PERF_ENABLE_0
+#define RBK_D_PERF_ENABLE_0			_MK_ADDR_CONST(0x11058)
+#define RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_PERF_ENABLE_0_PERF_EN_FIELD			_MK_FIELD_CONST(0x1, RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT)
+
+
+// Register RBK_D_PERF_READ_STALL_0
+#define RBK_D_PERF_READ_STALL_0			_MK_ADDR_CONST(0x1105c)
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_FIELD			_MK_FIELD_CONST(0xffffffff, RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT)
+
+
+// Register RBK_D_PERF_WRITE_STALL_0
+#define RBK_D_PERF_WRITE_STALL_0			_MK_ADDR_CONST(0x11060)
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT			_MK_SHIFT_CONST(0)
+#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_FIELD			_MK_FIELD_CONST(0xffffffff, RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT)
+
+
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_FIELD_CONST
+  #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_))
+#endif
+
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_NVDLA_CFGROM	0x0
+#define BASE_ADDRESS_NVDLA_GLB	0x1000
+#define BASE_ADDRESS_NVDLA_MCIF	0x2000
+#define BASE_ADDRESS_NVDLA_CDMA	0x3000
+#define BASE_ADDRESS_NVDLA_CSC	0x4000
+#define BASE_ADDRESS_NVDLA_CMAC_A	0x5000
+#define BASE_ADDRESS_NVDLA_CMAC_B	0x6000
+#define BASE_ADDRESS_NVDLA_CACC	0x7000
+#define BASE_ADDRESS_NVDLA_SDP_RDMA	0x8000
+#define BASE_ADDRESS_NVDLA_SDP	0x9000
+#define BASE_ADDRESS_NVDLA_PDP_RDMA	0xa000
+#define BASE_ADDRESS_NVDLA_PDP	0xb000
+#define BASE_ADDRESS_NVDLA_CDP_RDMA	0xc000
+#define BASE_ADDRESS_NVDLA_CDP	0xd000
+#define BASE_ADDRESS_NVDLA_GEC	0xe000
+#define BASE_ADDRESS_NVDLA_CVIF	0xf000
+#define BASE_ADDRESS_NVDLA_BDMA	0x10000
+#define BASE_ADDRESS_NVDLA_RBK	0x11000
+
+#endif
diff --git a/drivers/nvdla/nvdla_core_callbacks.c b/drivers/nvdla/nvdla_core_callbacks.c
new file mode 100644
index 000000000000..a6150aec6088
--- /dev/null
+++ b/drivers/nvdla/nvdla_core_callbacks.c
@@ -0,0 +1,443 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/dma-buf.h>
+#include <linux/dma-mapping.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/time.h>
+#include <linux/uaccess.h>
+
+#include <nvdla_interface.h>
+#include <nvdla_linux.h>
+#include <nvdla_ioctl.h>
+#include <opendla.h>
+
+static struct nvdla_config nvdla_config_os_initial = {
+	.atom_size = 32,
+	.bdma_enable = true,
+	.rubik_enable = true,
+	.weight_compress_support = true,
+};
+
+static struct nvdla_config nvdla_config_small = {
+	.atom_size = 8,
+	.bdma_enable = false,
+	.rubik_enable = false,
+	.weight_compress_support = false,
+};
+
+static struct nvdla_config nvdla_config_large = {
+	.atom_size = 32,
+	.bdma_enable = false,
+	.rubik_enable = false,
+	.weight_compress_support = false,
+};
+
+void __printf(1, 2) dla_debug(const char *str, ...)
+{
+	va_list args;
+	va_start(args, str);
+	vprintk(pr_fmt(str), args);
+	va_end(args);
+}
+
+void __printf(1, 2) dla_info(const char *str, ...)
+{
+	va_list args;
+	va_start(args, str);
+	vprintk(str, args);
+	va_end(args);
+}
+
+void __printf(1, 2) dla_warn(const char *str, ...)
+{
+	va_list args;
+	va_start(args, str);
+	vprintk(str, args);
+	va_end(args);
+}
+
+void __printf(1, 2) dla_error(const char *str, ...)
+{
+	va_list args;
+	va_start(args, str);
+	vprintk(str, args);
+	va_end(args);
+}
+
+void *dla_memset(void *src, int ch, uint64_t len)
+{
+	memset(src, ch, len);
+	return src;
+}
+
+void *dla_memcpy(void *dest, const void *src, uint64_t len)
+{
+	return memcpy(dest, src, len);
+}
+
+int64_t dla_get_time_us(void)
+{
+	return div_u64(ktime_get_ns(), NSEC_PER_USEC);
+}
+
+void dla_reg_write(void *driver_context, uint32_t addr, uint32_t reg)
+{
+	struct nvdla_device *nvdla_dev =
+			(struct nvdla_device *)driver_context;
+
+	if (!nvdla_dev)
+		return;
+
+	writel(reg, nvdla_dev->base + addr);
+}
+
+uint32_t dla_reg_read(void *driver_context, uint32_t addr)
+{
+	struct nvdla_device *nvdla_dev =
+			(struct nvdla_device *)driver_context;
+
+	if (!nvdla_dev)
+		return 0;
+
+	return readl(nvdla_dev->base + addr);
+}
+
+static irqreturn_t nvdla_engine_isr(int32_t irq, void *data)
+{
+	unsigned long flags;
+	struct nvdla_device *nvdla_dev = (struct nvdla_device *)data;
+
+	if (!nvdla_dev)
+		return IRQ_NONE;
+
+	spin_lock_irqsave(&nvdla_dev->nvdla_lock, flags);
+	dla_isr_handler(nvdla_dev->engine_context);
+	complete(&nvdla_dev->event_notifier);
+	spin_unlock_irqrestore(&nvdla_dev->nvdla_lock, flags);
+
+	return IRQ_HANDLED;
+}
+
+static int32_t dla_read_dma_address(void *driver_context, void *task_data,
+						int16_t index, void *dst)
+{
+	int32_t ret = 0;
+	struct nvdla_mem_handle *handles;
+	dma_addr_t *phys_addr = (dma_addr_t *)(dst);
+	struct nvdla_device *nvdla_dev =
+			(struct nvdla_device *)driver_context;
+	struct nvdla_task *task = (struct nvdla_task *)task_data;
+
+	if (index == -1 || index > task->num_addresses)
+		return -EINVAL;
+
+	handles = (struct nvdla_mem_handle *)task->address_list;
+	ret = nvdla_gem_dma_addr(nvdla_dev->drm, task->file,
+					handles[index].handle,
+					phys_addr);
+
+	/* Add offset to IOVA address */
+	*phys_addr = *phys_addr + handles[index].offset;
+
+	return ret;
+}
+
+static int32_t dla_read_cpu_address(void *driver_context, void *task_data,
+						int16_t index, void *dst)
+{
+	uint64_t *temp = (uint64_t *)dst;
+	struct nvdla_task *task = (struct nvdla_task *)task_data;
+
+	if (index == -1 || index > task->num_addresses)
+		return -EINVAL;
+
+	*temp = (uint64_t)index;
+	return 0;
+}
+
+int32_t dla_get_dma_address(void *driver_context, void *task_data,
+					int16_t index, void *dst_ptr,
+					uint32_t destination)
+{
+	int32_t ret = 0;
+
+	if (destination == DESTINATION_PROCESSOR) {
+		ret = dla_read_cpu_address(driver_context, task_data,
+						index, dst_ptr);
+	} else if (destination == DESTINATION_DMA) {
+		ret = dla_read_dma_address(driver_context, task_data,
+						index, dst_ptr);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+int32_t dla_data_write(void *driver_context, void *task_data,
+				void *src, uint64_t dst,
+				uint32_t size, uint64_t offset)
+{
+	int32_t ret;
+	void *ptr = NULL;
+	struct dma_buf *buf;
+	struct iosys_map map;
+	struct nvdla_mem_handle *handles;
+	struct nvdla_task *task = (struct nvdla_task *)task_data;
+	uint64_t dma_addr = 0;
+
+	dla_get_dma_address(driver_context, task_data,dst, (void *)&dma_addr, DESTINATION_DMA);
+	handles = task->address_list;
+	buf = dma_buf_get(handles[dst].handle);
+	if (IS_ERR(buf)) {
+		pr_err("%s: Failed get dma_buf for handle=%d\n", __func__,
+						handles[dst].handle);
+		return -EFAULT;
+	}
+
+	ret = dma_buf_begin_cpu_access(buf, DMA_BIDIRECTIONAL);
+	if (ret)
+		goto put_dma_buf;
+
+	ret = dma_buf_vmap(buf, &map);
+	ptr = ret ? NULL : map.vaddr;
+	if (!ptr) {
+		pr_err("%s: Failed to vmap dma_buf for handle=%d\n", __func__,
+						handles[dst].handle);
+		ret = -ENOMEM;
+		goto end_cpu_access;
+	}
+
+	memcpy((void *)((uint8_t *)ptr + offset), src, size);
+	dma_buf_vunmap(buf, &map);
+
+end_cpu_access:
+	dma_buf_end_cpu_access(buf, DMA_BIDIRECTIONAL);
+
+put_dma_buf:
+	dma_buf_put(buf);
+
+	return ret;
+}
+
+int32_t dla_data_read(void *driver_context, void *task_data,
+				uint64_t src, void *dst,
+				uint32_t size, uint64_t offset)
+{
+	int32_t ret;
+	void *ptr = NULL;
+	struct dma_buf *buf;
+	struct iosys_map map;
+	struct nvdla_mem_handle *handles;
+	struct nvdla_task *task = (struct nvdla_task *)task_data;
+	uint64_t dma_addr = 0;
+
+	dla_get_dma_address(driver_context, task_data, src, (void *)&dma_addr, DESTINATION_DMA);
+	handles = task->address_list;
+
+	buf = dma_buf_get(handles[src].handle);
+	if (IS_ERR(buf)) {
+		pr_err("%s: Failed get dma_buf for handle=%d\n", __func__,
+						handles[src].handle);
+		return -EFAULT;
+	}
+
+	ret = dma_buf_begin_cpu_access(buf, DMA_BIDIRECTIONAL);
+	if (ret)
+		goto put_dma_buf;
+
+	ret = dma_buf_vmap(buf, &map);
+	ptr = ret ? NULL : map.vaddr;
+	if (!ptr) {
+		pr_err("%s: Failed to vmap dma_buf for handle=%d\n", __func__,
+						handles[src].handle);
+		ret = -ENOMEM;
+		goto end_cpu_access;
+	}
+
+	memcpy(dst, (void *)(((uint8_t *)ptr) + offset), size);
+	dma_buf_vunmap(buf, &map);
+
+end_cpu_access:
+	dma_buf_end_cpu_access(buf, DMA_BIDIRECTIONAL);
+
+put_dma_buf:
+	dma_buf_put(buf);
+
+	return ret;
+}
+
+int32_t nvdla_task_submit(struct nvdla_device *nvdla_dev, struct nvdla_task *task)
+{
+	int32_t err = 0;
+	uint32_t task_complete = 0;
+
+	nvdla_dev->task = task;
+
+	err = dla_execute_task(nvdla_dev->engine_context, (void *)task, nvdla_dev->config_data);
+	if (err) {
+		pr_err("Task execution failed\n");
+		return err;
+	}
+
+	pr_debug("Wait for task complete\n");
+
+	while (1) {
+		unsigned long flags;
+
+		wait_for_completion(&nvdla_dev->event_notifier);
+
+		spin_lock_irqsave(&nvdla_dev->nvdla_lock, flags);
+
+		err = dla_process_events(nvdla_dev->engine_context, &task_complete);
+
+		spin_unlock_irqrestore(&nvdla_dev->nvdla_lock, flags);
+
+		if (err || task_complete)
+			break;
+	}
+
+	pr_debug("Task complete\n");
+	dla_clear_task(nvdla_dev->engine_context);
+
+	return err;
+}
+
+/* driver probe and init */
+static const struct of_device_id nvdla_of_match[] = {
+	{
+		.compatible = "nvidia,nvdla_os_initial",
+		.data = &nvdla_config_os_initial,
+	},
+	{
+		.compatible = "nvidia,nv_small",
+		.data = &nvdla_config_small,
+	},
+	{
+		.compatible = "nvidia,nv_large",
+		.data = &nvdla_config_large,
+	},
+	{ },
+};
+
+static int nvdla_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct nvdla_device *nvdla_dev;
+	const struct of_device_id *match;
+	int err;
+
+	if (!pdev->dev.of_node)
+		return -EINVAL;
+
+	match = of_match_device(nvdla_of_match, &pdev->dev);
+	if (!match) {
+		pr_err("Missing DT entry!\n");
+		return -EINVAL;
+	}
+
+	pr_err("Probe NVDLA config %s\n", match->compatible);
+
+	nvdla_dev = devm_kzalloc(dev, sizeof(*nvdla_dev), GFP_KERNEL);
+	if (!nvdla_dev)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, nvdla_dev);
+	nvdla_dev->pdev = pdev;
+	nvdla_dev->config_data = (struct nvdla_config *)match->data;
+
+	init_completion(&nvdla_dev->event_notifier);
+
+	nvdla_dev->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(nvdla_dev->base))
+		return PTR_ERR(nvdla_dev->base);
+
+	nvdla_dev->irq = platform_get_irq(pdev, 0);
+	if (nvdla_dev->irq < 0)
+		return nvdla_dev->irq;
+
+	err = devm_request_irq(&pdev->dev, nvdla_dev->irq,
+				nvdla_engine_isr, 0,
+				dev_name(&pdev->dev), nvdla_dev);
+	if (err)
+		return err;
+
+	dla_register_driver(&nvdla_dev->engine_context, (void *)nvdla_dev);
+	dla_clear_task(nvdla_dev->engine_context);
+
+	err = nvdla_drm_probe(nvdla_dev);
+	if (err)
+		dev_err(&pdev->dev, "failed to register drm device\n");
+
+	return err;
+}
+
+static int __exit nvdla_remove(struct platform_device *pdev)
+{
+	struct nvdla_device *nvdla_dev = dev_get_drvdata(&pdev->dev);
+
+	nvdla_drm_remove(nvdla_dev);
+
+	return 0;
+}
+
+static struct platform_driver nvdla_driver = {
+	.probe = nvdla_probe,
+	.remove = __exit_p(nvdla_remove),
+	.driver = {
+		.name = "NVDLA",
+		.of_match_table = of_match_ptr(nvdla_of_match),
+	},
+};
+module_platform_driver(nvdla_driver);
+
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_AUTHOR("NVIDIA");
+MODULE_DESCRIPTION("Nvidia Deep Learning Accelerator driver");
+
+MODULE_IMPORT_NS(DMA_BUF);
diff --git a/drivers/nvdla/nvdla_gem.c b/drivers/nvdla/nvdla_gem.c
new file mode 100644
index 000000000000..7d6105eeaad0
--- /dev/null
+++ b/drivers/nvdla/nvdla_gem.c
@@ -0,0 +1,475 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <drm/drm_device.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_gem.h>
+#include <drm/drm_gem_dma_helper.h>
+
+#include <linux/dma-buf.h>
+#include <linux/dma-mapping.h>
+#include <linux/dma-map-ops.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <nvdla_linux.h>
+#include <nvdla_ioctl.h>
+#include <opendla.h>
+#define to_nvdla_obj(x) container_of(x, struct nvdla_gem_object, object)
+
+struct nvdla_gem_object {
+	struct drm_gem_object object;
+
+	void *kvaddr;
+	dma_addr_t dma_addr;
+	unsigned long dma_attrs;
+};
+
+static int32_t nvdla_fill_task_desc(struct nvdla_ioctl_submit_task *local_task,
+				struct nvdla_task *task)
+{
+	struct nvdla_mem_handle *handles;
+
+	/* update task desc fields */
+	task->num_addresses = local_task->num_addresses;
+
+	handles = kzalloc(local_task->num_addresses *
+				sizeof(struct nvdla_mem_handle), GFP_KERNEL);
+	if (handles == NULL)
+		return -EFAULT;
+
+	/* get user addresses list */
+	if (copy_from_user(handles,
+		(void __user *)(unsigned long)local_task->address_list,
+		(task->num_addresses *
+			sizeof(struct nvdla_mem_handle)))) {
+		pr_err("failed to copy address list from user ptr\n");
+		kfree(handles);
+		return -EFAULT;
+	}
+
+	task->address_list = handles;
+	return 0;
+}
+
+static int32_t nvdla_submit(struct drm_device *drm, void *arg,
+					struct drm_file *file)
+{
+	int32_t err = 0;
+	struct nvdla_task *task;
+	struct nvdla_ioctl_submit_task local_task;
+	struct nvdla_ioctl_submit_task __user *user_task;
+	struct nvdla_device *nvdla_dev = dev_get_drvdata(drm->dev);
+	struct nvdla_submit_args *args =
+			(struct nvdla_submit_args *)arg;
+
+	user_task = (struct nvdla_ioctl_submit_task __user *)
+			(uintptr_t)args->tasks;
+	if (!user_task)
+		return -EINVAL;
+
+	/* IOCTL copy descriptors */
+	if (copy_from_user(&local_task, (void __user *)user_task,
+			(sizeof(*user_task))))
+		return -EFAULT;
+
+	task = kzalloc(sizeof(*task), GFP_KERNEL);
+	if (task == NULL)
+		return -EFAULT;
+
+	nvdla_dev->task = task;
+	kref_init(&task->ref);
+	task->nvdla_dev = nvdla_dev;
+	task->file = file;
+
+	/* update task desc fields */
+	err = nvdla_fill_task_desc(&local_task, task);
+	if (err)
+		goto free_task_desc;
+
+	err = nvdla_task_submit(nvdla_dev, task);
+
+	kfree(task->address_list);
+
+free_task_desc:
+	kfree(task);
+	return err;
+}
+
+static int32_t nvdla_gem_alloc(struct nvdla_gem_object *nobj)
+{
+	struct drm_gem_object *dobj = &nobj->object;
+	struct drm_device *drm = dobj->dev;
+
+	nobj->dma_attrs = DMA_ATTR_WRITE_COMBINE;
+
+	nobj->kvaddr = dma_alloc_attrs(drm->dev, dobj->size, &nobj->dma_addr,
+						GFP_KERNEL, nobj->dma_attrs);
+
+	if (!nobj->kvaddr)
+		return -ENOMEM;
+
+	return 0;
+}
+
+static void nvdla_gem_free(struct nvdla_gem_object *nobj)
+{
+	struct drm_gem_object *dobj = &nobj->object;
+	struct drm_device *drm = dobj->dev;
+
+	dma_free_attrs(drm->dev, dobj->size, nobj->kvaddr, nobj->dma_addr,
+				nobj->dma_attrs);
+}
+
+static void nvdla_gem_free_object(struct drm_gem_object *dobj)
+{
+	struct nvdla_gem_object *nobj;
+
+	drm_gem_free_mmap_offset(dobj);
+
+	nobj = to_nvdla_obj(dobj);
+
+	nvdla_gem_free(nobj);
+
+	kfree(nobj);
+}
+
+static struct sg_table
+*nvdla_drm_gem_prime_get_sg_table(struct drm_gem_object *dobj)
+{
+	int32_t ret;
+	struct sg_table *sgt;
+	struct drm_device *drm = dobj->dev;
+	struct nvdla_gem_object *nobj = to_nvdla_obj(dobj);
+
+	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt)
+		return ERR_PTR(-ENOMEM);
+
+	ret = dma_get_sgtable_attrs(drm->dev, sgt, nobj->kvaddr,
+			nobj->dma_addr, dobj->size,
+			nobj->dma_attrs);
+	if (ret) {
+		DRM_ERROR("failed to allocate sgt, %d\n", ret);
+		kfree(sgt);
+		return ERR_PTR(ret);
+	}
+
+	return sgt;
+}
+
+static int nvdla_drm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map)
+{
+	struct nvdla_gem_object *nobj = to_nvdla_obj(obj);
+	if (nobj->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING)
+		return -ENOMEM;
+	iosys_map_set_vaddr(map, nobj->kvaddr);
+	return 0;
+}
+
+static void nvdla_drm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map)
+{
+    /* Nothing to do */
+}
+
+static const struct drm_gem_object_funcs nvdla_gem_funcs = {
+	.free			= nvdla_gem_free_object,
+	.export			= drm_gem_prime_export,
+	.vmap			= nvdla_drm_gem_prime_vmap,
+	.vunmap			= nvdla_drm_gem_prime_vunmap,
+	.get_sg_table	= nvdla_drm_gem_prime_get_sg_table,
+	.vm_ops			= &drm_gem_dma_vm_ops,
+};
+
+static struct nvdla_gem_object *
+nvdla_gem_create_object(struct drm_device *drm, uint32_t size)
+{
+	int32_t ret;
+	struct drm_gem_object *dobj;
+	struct nvdla_gem_object *nobj;
+
+	size = round_up(size, PAGE_SIZE);
+
+	nobj = kzalloc(sizeof(*nobj), GFP_KERNEL);
+	if (!nobj)
+		return ERR_PTR(-ENOMEM);
+
+	dobj = &nobj->object;
+	dobj->funcs = &nvdla_gem_funcs;
+
+	drm_gem_private_object_init(drm, dobj, size);
+
+	ret = nvdla_gem_alloc(nobj);
+	if (ret)
+		goto free_nvdla_obj;
+
+	return nobj;
+
+free_nvdla_obj:
+	kfree(nobj);
+	return ERR_PTR(ret);
+}
+
+static struct nvdla_gem_object *
+nvdla_gem_create_with_handle(struct drm_file *file_priv,
+				struct drm_device *drm, uint32_t size,
+				uint32_t *handle)
+{
+	int32_t ret;
+	struct drm_gem_object *dobj;
+	struct nvdla_gem_object *nobj;
+
+	nobj = nvdla_gem_create_object(drm, size);
+	if (IS_ERR(nobj))
+		return ERR_CAST(nobj);
+
+	dobj = &nobj->object;
+
+	ret = drm_gem_handle_create(file_priv, dobj, handle);
+	if (ret)
+		goto free_drm_object;
+
+	drm_gem_object_put(dobj);
+
+	return nobj;
+
+free_drm_object:
+	nvdla_gem_free_object(dobj);
+
+	return ERR_PTR(ret);
+}
+
+static int32_t nvdla_gem_create(struct drm_device *drm, void *data,
+				struct drm_file *file)
+{
+	struct nvdla_gem_object *nobj;
+	struct nvdla_gem_create_args *args = data;
+
+	nobj = nvdla_gem_create_with_handle(file, drm, args->size,
+					 &args->handle);
+	if (IS_ERR(nobj))
+		return PTR_ERR(nobj);
+
+	return 0;
+}
+
+static int32_t nvdla_drm_gem_object_mmap(struct drm_gem_object *dobj,
+					struct vm_area_struct *vma)
+{
+	int32_t ret;
+	struct nvdla_gem_object *nobj = to_nvdla_obj(dobj);
+	struct drm_device *drm = dobj->dev;
+
+	vm_flags_clear(vma, VM_PFNMAP);
+	vma->vm_pgoff = 0;
+
+	ret = dma_mmap_attrs(drm->dev, vma, nobj->kvaddr, nobj->dma_addr,
+			     dobj->size, nobj->dma_attrs);
+	if (ret)
+		drm_gem_vm_close(vma);
+
+	return ret;
+}
+
+static int32_t nvdla_drm_gem_mmap_buf(struct drm_gem_object *obj,
+				struct vm_area_struct *vma)
+{
+	int32_t ret;
+
+	ret = drm_gem_mmap_obj(obj, obj->size, vma);
+	if (ret)
+		return ret;
+
+	return nvdla_drm_gem_object_mmap(obj, vma);
+}
+
+static int32_t nvdla_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+	int32_t ret;
+	struct drm_gem_object *obj;
+
+	ret = drm_gem_mmap(filp, vma);
+	if (ret)
+		return ret;
+
+	obj = vma->vm_private_data;
+
+	return nvdla_drm_gem_object_mmap(obj, vma);
+}
+
+int32_t nvdla_gem_dma_addr(struct drm_device *dev, struct drm_file *file,
+			uint32_t fd, dma_addr_t *addr)
+{
+	int32_t ret;
+	uint32_t handle;
+	struct nvdla_gem_object *nobj;
+	struct drm_gem_object *dobj;
+
+	ret = drm_gem_prime_fd_to_handle(dev, file, fd, &handle);
+	if (ret)
+		return ret;
+
+	dobj = drm_gem_object_lookup(file, handle);
+	if (!dobj)
+		return -EINVAL;
+
+	nobj = to_nvdla_obj(dobj);
+
+	*addr = nobj->dma_addr;
+
+	drm_gem_object_put(dobj);
+
+	return 0;
+}
+
+static int32_t nvdla_gem_map_offset(struct drm_device *drm, void *data,
+				struct drm_file *file)
+{
+	int32_t ret;
+	struct drm_gem_object *dobj;
+	struct nvdla_gem_map_offset_args *args = data;
+
+	dobj = drm_gem_object_lookup(file, args->handle);
+	if (!dobj)
+		return -EINVAL;
+
+	ret = drm_gem_create_mmap_offset(dobj);
+	if (ret)
+		goto out;
+
+	args->offset = drm_vma_node_offset_addr(&dobj->vma_node);
+
+out:
+	drm_gem_object_put(dobj);
+
+	return 0;
+}
+
+static int32_t nvdla_gem_destroy(struct drm_device *drm, void *data,
+				struct drm_file *file)
+{
+	struct nvdla_gem_destroy_args *args = data;
+
+	return drm_gem_handle_delete(file, args->handle);
+}
+
+static const struct file_operations nvdla_drm_fops = {
+	.owner = THIS_MODULE,
+	.open = drm_open,
+	.release = drm_release,
+	.unlocked_ioctl = drm_ioctl,
+	.mmap = nvdla_drm_gem_mmap,
+	.poll = drm_poll,
+	.read = drm_read,
+#ifdef CONFIG_COMPAT
+	.compat_ioctl = drm_compat_ioctl,
+#endif
+	.llseek = noop_llseek,
+};
+
+static const struct drm_ioctl_desc nvdla_drm_ioctls[] = {
+	DRM_IOCTL_DEF_DRV(NVDLA_SUBMIT, nvdla_submit, DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(NVDLA_GEM_CREATE, nvdla_gem_create, DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(NVDLA_GEM_MMAP, nvdla_gem_map_offset, DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(NVDLA_GEM_DESTROY, nvdla_gem_destroy, DRM_RENDER_ALLOW),
+};
+
+static struct drm_driver nvdla_drm_driver = {
+	.driver_features = DRIVER_GEM | DRIVER_RENDER,
+
+	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+	.gem_prime_import = drm_gem_prime_import,
+	.gem_prime_mmap		= nvdla_drm_gem_mmap_buf,
+
+	.ioctls = nvdla_drm_ioctls,
+	.num_ioctls = ARRAY_SIZE(nvdla_drm_ioctls),
+	.fops = &nvdla_drm_fops,
+
+	.name = "nvdla",
+	.desc = "NVDLA driver",
+	.date = "20171017",
+	.major = 0,
+	.minor = 0,
+	.patchlevel = 0,
+};
+
+int32_t nvdla_drm_probe(struct nvdla_device *nvdla_dev)
+{
+	int32_t err;
+	struct drm_device *drm;
+	struct drm_driver *driver = &nvdla_drm_driver;
+	struct resource res_cma;
+	struct device_node *node;
+
+	drm = drm_dev_alloc(driver, &nvdla_dev->pdev->dev);
+	if (IS_ERR(drm))
+		return PTR_ERR(drm);
+
+	nvdla_dev->drm = drm;
+
+	err = drm_dev_register(drm, 0);
+	if (err < 0)
+		goto unref;
+
+	/**
+	 * TODO Register separate driver for memory and use DT node to
+	 * read memory range
+	 */
+	node = of_parse_phandle(drm->dev->of_node, "memory-region", 0);
+	if(node ){
+		dev_info(drm->dev, "Get mem from memory-region\n");
+		of_address_to_resource(node, 0, &res_cma);
+		err = dma_declare_coherent_memory(drm->dev, res_cma.start, res_cma.start,resource_size(&res_cma));
+	} else {
+		dev_info(drm->dev, "NVDLA using the default mem.\n");
+		err = dma_declare_coherent_memory(drm->dev, 0xC0000000, 0xC0000000, 0x40000000);
+	}
+
+	if (err < 0) {
+		goto unref;
+	}
+
+	return 0;
+
+unref:
+	drm_dev_put(drm);
+	return err;
+}
+
+void nvdla_drm_remove(struct nvdla_device *nvdla_dev)
+{
+	drm_dev_unregister(nvdla_dev->drm);
+	drm_dev_put(nvdla_dev->drm);
+}
diff --git a/drivers/nvdla/pdp.c b/drivers/nvdla/pdp.c
new file mode 100644
index 000000000000..fc98fd7ad386
--- /dev/null
+++ b/drivers/nvdla/pdp.c
@@ -0,0 +1,528 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "common.h"
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+#define MAX_SPLIT_NUM	64
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a)	(sizeof(a) / sizeof((a[0])))
+#endif
+
+static const uint8_t map_ram[] = {
+	FIELD_ENUM(PDP_RDMA_D_SRC_RAM_CFG_0, SRC_RAM_TYPE, MC),
+	FIELD_ENUM(PDP_RDMA_D_SRC_RAM_CFG_0, SRC_RAM_TYPE, CV),
+};
+
+static const uint8_t map_pool[] = {
+	FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
+			POOLING_METHOD, POOLING_METHOD_AVERAGE),
+	FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
+			POOLING_METHOD, POOLING_METHOD_MAX),
+	FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
+			POOLING_METHOD, POOLING_METHOD_MIN),
+};
+
+static const uint8_t map_precision[] = {
+	FIELD_ENUM(PDP_D_DATA_FORMAT_0, INPUT_DATA, INT8),
+	FIELD_ENUM(PDP_D_DATA_FORMAT_0, INPUT_DATA, INT16),
+	FIELD_ENUM(PDP_D_DATA_FORMAT_0, INPUT_DATA, FP16),
+};
+
+static const uint8_t map_pool_kernel[] = {
+	FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_1),
+	FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_2),
+	FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_3),
+	FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_4),
+	FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_5),
+	FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_6),
+	FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_7),
+	FIELD_ENUM(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH, KERNEL_WIDTH_8),
+};
+
+/* The reciprocal of kernel width: 1/1, 1/2, 1/3, ... */
+static const uint32_t recip_kernel_size[2][8] = {
+	/*
+	 * INT8/16
+	 * 1      1/2     1/3     1/4     1/5     1/6     1/7     1/8
+	 */
+	{0x10000, 0x8000, 0x5555, 0x4000, 0x3333, 0x2aaa, 0x2492, 0x2000},
+	{0x7c00, 0x7800, 0x7555,  0x7400, 0x7266, 0x7155, 0x7092, 0x7000},
+};
+
+#if STAT_ENABLE
+void
+dla_pdp_stat_data(struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	uint64_t end_time = 0;
+	struct dla_pdp_stat_desc *pdp_stat;
+
+	pdp_stat = &processor->stat_data_desc->pdp_stat;
+
+	end_time = dla_get_time_us();
+
+	pdp_stat->write_stall = pdp_reg_read(D_PERF_WRITE_STALL);
+	pdp_stat->runtime = (uint32_t)(end_time - group->start_time);
+}
+
+void
+dla_pdp_dump_stat(struct dla_processor *processor)
+{
+	struct dla_pdp_stat_desc *pdp_stat;
+
+	pdp_stat = &processor->stat_data_desc->pdp_stat;
+
+	dla_debug_pdp_stats(pdp_stat);
+}
+#endif /* STAT_ENABLE */
+
+static uint32_t
+get_fly_mode(uint8_t type)
+{
+	uint32_t val;
+
+	val = type == DLA_MEM_HW ?
+			FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
+						FLYING_MODE, ON_FLYING) :
+			FIELD_ENUM(PDP_D_OPERATION_MODE_CFG_0,
+						FLYING_MODE, OFF_FLYING);
+
+	return val;
+}
+
+void
+dla_pdp_set_producer(int32_t group_id, int32_t rdma_group_id)
+{
+	uint32_t reg;
+
+	dla_trace("Enter: %s", __func__);
+
+	dla_debug("group id %d rdma id %d\n", group_id, rdma_group_id);
+
+	reg = group_id << SHIFT(PDP_S_POINTER_0, PRODUCER);
+	pdp_reg_write(S_POINTER, reg);
+
+	reg = rdma_group_id << SHIFT(PDP_RDMA_S_POINTER_0, PRODUCER);
+	pdp_rdma_reg_write(S_POINTER, reg);
+
+	dla_trace("Exit: %s", __func__);
+}
+
+int
+dla_pdp_enable(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	uint32_t reg;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_trace("Enter: %s", __func__);
+
+	if (!group) {
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (engine->stat_enable == (uint32_t)1) {
+		reg = FIELD_ENUM(PDP_D_PERF_ENABLE_0, DMA_EN, ENABLE);
+		pdp_reg_write(D_PERF_ENABLE, reg);
+		group->start_time = dla_get_time_us();
+	}
+
+	dla_debug("rdma needed %u\n", group->is_rdma_needed);
+
+	/**
+	 * enable all sub-modules
+	 */
+	if (group->is_rdma_needed) {
+		reg = FIELD_ENUM(PDP_RDMA_D_OP_ENABLE_0, OP_EN, ENABLE);
+		pdp_rdma_reg_write(D_OP_ENABLE, reg);
+	}
+	reg = FIELD_ENUM(PDP_D_OP_ENABLE_0, OP_EN, ENABLE);
+	pdp_reg_write(D_OP_ENABLE, reg);
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+void
+dla_pdp_rdma_check(struct dla_processor_group *group)
+{
+	struct dla_pdp_surface_desc *pdp_surface;
+
+	pdp_surface = &group->surface_desc->pdp_surface;
+
+	group->is_rdma_needed = 0;
+
+	if (pdp_surface->src_data.type != DLA_MEM_HW)
+		group->is_rdma_needed = 1;
+}
+
+static int
+validate_strides(uint8_t stride_x, uint8_t stride_y)
+{
+	int32_t ret = 0;
+
+	if (stride_x < 1 || stride_y < 1 || stride_x > 8 || stride_y > 8) {
+		dla_error("Invalid Stride (x[%d], y[%d])\n", stride_x, stride_y);
+		ret = ERR(INVALID_INPUT);
+	}
+
+	RETURN(ret);
+}
+
+static int
+vaildate_pdp_configs(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	struct dla_pdp_op_desc *pdp_op;
+	struct dla_pdp_surface_desc *pdp_surface;
+
+	dla_trace("Enter: %s", __func__);
+
+	pdp_op = &group->operation_desc->pdp_op;
+	pdp_surface = &group->surface_desc->pdp_surface;
+
+	if (pdp_surface->dst_data.type == DLA_MEM_HW) {
+		dla_error("Destination buffer for PDP has to be either MC or CV");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	ret = validate_data_cube(pdp_surface->src_data, pdp_surface->dst_data,
+								DLA_MEM_HW);
+	if (ret)
+		goto exit;
+
+	ret = validate_precision(pdp_op->precision, ARRAY_SIZE(map_precision));
+	if (ret)
+		goto exit;
+
+	ret = validate_strides(pdp_op->stride_x, pdp_op->stride_y);
+	if (ret)
+		goto exit;
+
+	if (pdp_op->split_num > MAX_SPLIT_NUM) {
+		dla_error("Invalid split_num: %u\n", pdp_op->split_num);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (pdp_op->pool_width >= ARRAY_SIZE(map_pool_kernel)) {
+		dla_error("Invalid pool_width: %u\n", pdp_op->pool_width);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (pdp_op->pool_height >= ARRAY_SIZE(map_pool_kernel)) {
+		dla_error("Invalid pool_height: %u\n", pdp_op->pool_height);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	if (pdp_op->pool_mode >= ARRAY_SIZE(map_pool)) {
+		dla_error("Invalid pool_mode: %u\n", pdp_op->pool_mode);
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+static int
+processor_pdp_program(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	uint32_t reg, high, low;
+	uint64_t input_address = 0;
+	uint64_t output_address = 0;
+	struct dla_engine *engine = dla_get_engine();
+	struct dla_pdp_op_desc *pdp_op;
+	struct dla_pdp_surface_desc *pdp_surface;
+
+	dla_trace("Enter: %s", __func__);
+
+	pdp_op = &group->operation_desc->pdp_op;
+	pdp_surface = &group->surface_desc->pdp_surface;
+
+	ret = vaildate_pdp_configs(group);
+	if (ret)
+		goto exit;
+
+	ret = dla_read_input_address(&pdp_surface->src_data,
+					&input_address,
+					group->op_desc->index,
+					group->roi_index,
+					1);
+	if (ret)
+		goto exit;
+
+	if (pdp_surface->dst_data.address != -1)
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					pdp_surface->dst_data.address,
+					pdp_surface->dst_data.offset,
+					(void *)&output_address,
+					DESTINATION_DMA);
+
+	if (pdp_surface->src_data.type != DLA_MEM_HW) {
+		/* PDP RDMA */
+		pdp_rdma_reg_write(D_DATA_CUBE_IN_WIDTH,
+				pdp_surface->src_data.width - 1);
+		pdp_rdma_reg_write(D_DATA_CUBE_IN_HEIGHT,
+				pdp_surface->src_data.height - 1);
+		pdp_rdma_reg_write(D_DATA_CUBE_IN_CHANNEL,
+				pdp_surface->src_data.channel - 1);
+
+		high = HIGH32BITS(input_address);
+		low  = LOW32BITS(input_address);
+		pdp_rdma_reg_write(D_SRC_BASE_ADDR_HIGH, high);
+		pdp_rdma_reg_write(D_SRC_BASE_ADDR_LOW, low);
+		pdp_rdma_reg_write(D_SRC_LINE_STRIDE,
+				pdp_surface->src_data.line_stride);
+		pdp_rdma_reg_write(D_SRC_SURFACE_STRIDE,
+				pdp_surface->src_data.surf_stride);
+
+		reg = (map_precision[pdp_op->precision]
+			<< SHIFT(PDP_RDMA_D_DATA_FORMAT_0, INPUT_DATA));
+		pdp_rdma_reg_write(D_DATA_FORMAT, reg);
+
+		reg = map_ram[pdp_surface->src_data.type]
+			<< SHIFT(PDP_RDMA_D_SRC_RAM_CFG_0, SRC_RAM_TYPE);
+		pdp_rdma_reg_write(D_SRC_RAM_CFG, reg);
+
+		reg = ((pdp_op->split_num - 1)
+			 << SHIFT(PDP_RDMA_D_OPERATION_MODE_CFG_0, SPLIT_NUM));
+		pdp_rdma_reg_write(D_OPERATION_MODE_CFG, reg);
+
+		reg = (map_pool_kernel[pdp_op->pool_width]
+			<< SHIFT(PDP_RDMA_D_POOLING_KERNEL_CFG_0,
+							KERNEL_WIDTH)) |
+			((pdp_op->stride_x - 1)
+			<< SHIFT(PDP_RDMA_D_POOLING_KERNEL_CFG_0,
+							KERNEL_STRIDE_WIDTH));
+		pdp_rdma_reg_write(D_POOLING_KERNEL_CFG, reg);
+
+		reg = (pdp_op->pad_left
+			<< SHIFT(PDP_RDMA_D_POOLING_PADDING_CFG_0, PAD_WIDTH));
+		pdp_rdma_reg_write(D_POOLING_PADDING_CFG, reg);
+
+		reg = ((pdp_op->partial_in_width_first == 0 ? 0 :
+				pdp_op->partial_in_width_first - 1)
+			<< SHIFT(PDP_RDMA_D_PARTIAL_WIDTH_IN_0,
+				PARTIAL_WIDTH_IN_FIRST)) |
+			((pdp_op->partial_in_width_mid == 0 ? 0 :
+				pdp_op->partial_in_width_mid - 1)
+			<< SHIFT(PDP_RDMA_D_PARTIAL_WIDTH_IN_0,
+				PARTIAL_WIDTH_IN_MID)) |
+			((pdp_op->partial_in_width_last == 0 ? 0 :
+				pdp_op->partial_in_width_last - 1)
+			<< SHIFT(PDP_RDMA_D_PARTIAL_WIDTH_IN_0,
+				PARTIAL_WIDTH_IN_LAST));
+		pdp_rdma_reg_write(D_PARTIAL_WIDTH_IN, reg);
+	} else {
+		ASSERT_GOTO(pdp_op->split_num == 1, ret,
+					ERR(INVALID_INPUT), exit);
+	}
+
+	reg = ((pdp_surface->src_data.width - 1)
+		<< SHIFT(PDP_D_DATA_CUBE_IN_WIDTH_0, CUBE_IN_WIDTH));
+	pdp_reg_write(D_DATA_CUBE_IN_WIDTH, reg);
+
+	reg = ((pdp_surface->src_data.height - 1)
+		<< SHIFT(PDP_D_DATA_CUBE_IN_HEIGHT_0, CUBE_IN_HEIGHT));
+	pdp_reg_write(D_DATA_CUBE_IN_HEIGHT, reg);
+
+	reg = ((pdp_surface->src_data.channel - 1)
+		<< SHIFT(PDP_D_DATA_CUBE_IN_CHANNEL_0, CUBE_IN_CHANNEL));
+	pdp_reg_write(D_DATA_CUBE_IN_CHANNEL, reg);
+
+	reg = ((pdp_surface->dst_data.width - 1)
+		<< SHIFT(PDP_D_DATA_CUBE_OUT_WIDTH_0, CUBE_OUT_WIDTH));
+	pdp_reg_write(D_DATA_CUBE_OUT_WIDTH, reg);
+
+	reg = ((pdp_surface->dst_data.height - 1)
+		<< SHIFT(PDP_D_DATA_CUBE_OUT_HEIGHT_0, CUBE_OUT_HEIGHT));
+	pdp_reg_write(D_DATA_CUBE_OUT_HEIGHT, reg);
+
+	reg = ((pdp_surface->dst_data.channel - 1)
+		<< SHIFT(PDP_D_DATA_CUBE_OUT_CHANNEL_0, CUBE_OUT_CHANNEL));
+	pdp_reg_write(D_DATA_CUBE_OUT_CHANNEL, reg);
+
+	reg = (map_pool[pdp_op->pool_mode]
+		<< SHIFT(PDP_D_OPERATION_MODE_CFG_0, POOLING_METHOD)) |
+		(get_fly_mode(pdp_surface->src_data.type)
+		<< SHIFT(PDP_D_OPERATION_MODE_CFG_0, FLYING_MODE)) |
+		((pdp_op->split_num - 1)
+		<< SHIFT(PDP_D_OPERATION_MODE_CFG_0, SPLIT_NUM));
+	pdp_reg_write(D_OPERATION_MODE_CFG, reg);
+
+	reg = ((pdp_op->partial_in_width_first == 0 ? 0 :
+			pdp_op->partial_in_width_first-1)
+		<< SHIFT(PDP_D_PARTIAL_WIDTH_IN_0, PARTIAL_WIDTH_IN_FIRST)) |
+		((pdp_op->partial_in_width_mid == 0 ? 0 :
+			pdp_op->partial_in_width_mid-1)
+		<< SHIFT(PDP_D_PARTIAL_WIDTH_IN_0, PARTIAL_WIDTH_IN_MID)) |
+		((pdp_op->partial_in_width_last == 0 ? 0 :
+			pdp_op->partial_in_width_last-1)
+		<< SHIFT(PDP_D_PARTIAL_WIDTH_IN_0, PARTIAL_WIDTH_IN_LAST));
+	pdp_reg_write(D_PARTIAL_WIDTH_IN, reg);
+
+	reg = ((pdp_op->partial_width_first == 0 ? 0 :
+			pdp_op->partial_width_first-1)
+		<< SHIFT(PDP_D_PARTIAL_WIDTH_OUT_0, PARTIAL_WIDTH_OUT_FIRST)) |
+		((pdp_op->partial_width_mid == 0 ? 0 :
+			pdp_op->partial_width_mid-1)
+		<< SHIFT(PDP_D_PARTIAL_WIDTH_OUT_0, PARTIAL_WIDTH_OUT_MID))   |
+		((pdp_op->partial_width_last == 0 ? 0 :
+			pdp_op->partial_width_last-1)
+		<< SHIFT(PDP_D_PARTIAL_WIDTH_OUT_0, PARTIAL_WIDTH_OUT_LAST));
+	pdp_reg_write(D_PARTIAL_WIDTH_OUT, reg);
+
+	reg = (map_pool_kernel[pdp_op->pool_width]
+		<< SHIFT(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_WIDTH)) |
+		(map_pool_kernel[pdp_op->pool_height]
+		<< SHIFT(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_HEIGHT))|
+		((pdp_op->stride_x - 1)
+		<< SHIFT(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_STRIDE_WIDTH)) |
+		((pdp_op->stride_y - 1)
+		<< SHIFT(PDP_D_POOLING_KERNEL_CFG_0, KERNEL_STRIDE_HEIGHT));
+	pdp_reg_write(D_POOLING_KERNEL_CFG, reg);
+
+	pdp_reg_write(D_RECIP_KERNEL_WIDTH,
+			recip_kernel_size[pdp_op->precision ==
+					PRECISION_FP16][pdp_op->pool_width]);
+	pdp_reg_write(D_RECIP_KERNEL_HEIGHT,
+			recip_kernel_size[pdp_op->precision ==
+					PRECISION_FP16][pdp_op->pool_height]);
+
+	reg = (pdp_op->pad_left
+		<< SHIFT(PDP_D_POOLING_PADDING_CFG_0, PAD_LEFT)) |
+		(pdp_op->pad_right
+		<< SHIFT(PDP_D_POOLING_PADDING_CFG_0, PAD_RIGHT)) |
+		(pdp_op->pad_top
+		<< SHIFT(PDP_D_POOLING_PADDING_CFG_0, PAD_TOP)) |
+		(pdp_op->pad_bottom
+		<< SHIFT(PDP_D_POOLING_PADDING_CFG_0, PAD_BOTTOM));
+	if (pdp_op->precision == PRECISION_FP16) {
+		int32_t i;
+
+		for (i = 0; i < 7; i++)
+			ASSERT_GOTO(pdp_op->padding_value[i] == 0, ret,
+						ERR(INVALID_INPUT), exit);
+	}
+
+	pdp_reg_write(D_POOLING_PADDING_CFG, reg);
+	pdp_reg_write(D_POOLING_PADDING_VALUE_1_CFG, pdp_op->padding_value[0]);
+	pdp_reg_write(D_POOLING_PADDING_VALUE_2_CFG, pdp_op->padding_value[1]);
+	pdp_reg_write(D_POOLING_PADDING_VALUE_3_CFG, pdp_op->padding_value[2]);
+	pdp_reg_write(D_POOLING_PADDING_VALUE_4_CFG, pdp_op->padding_value[3]);
+	pdp_reg_write(D_POOLING_PADDING_VALUE_5_CFG, pdp_op->padding_value[4]);
+	pdp_reg_write(D_POOLING_PADDING_VALUE_6_CFG, pdp_op->padding_value[5]);
+	pdp_reg_write(D_POOLING_PADDING_VALUE_7_CFG, pdp_op->padding_value[6]);
+
+	if (pdp_surface->src_data.type != DLA_MEM_HW) {
+		pdp_reg_write(D_SRC_LINE_STRIDE,
+				pdp_surface->src_data.line_stride);
+		pdp_reg_write(D_SRC_SURFACE_STRIDE,
+				pdp_surface->src_data.surf_stride);
+	}
+
+	high = HIGH32BITS(output_address);
+	low = LOW32BITS(output_address);
+	pdp_reg_write(D_DST_BASE_ADDR_LOW, low);
+	pdp_reg_write(D_DST_BASE_ADDR_HIGH, high);
+
+	pdp_reg_write(D_DST_LINE_STRIDE, pdp_surface->dst_data.line_stride);
+	pdp_reg_write(D_DST_SURFACE_STRIDE, pdp_surface->dst_data.surf_stride);
+
+	reg = (map_ram[pdp_surface->dst_data.type]
+		<< SHIFT(PDP_D_DST_RAM_CFG_0, DST_RAM_TYPE));
+	pdp_reg_write(D_DST_RAM_CFG, reg);
+
+	reg = (map_precision[pdp_op->precision]
+		<< SHIFT(PDP_D_DATA_FORMAT_0, INPUT_DATA));
+	pdp_reg_write(D_DATA_FORMAT, reg);
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+int
+dla_pdp_is_ready(struct dla_processor *processor,
+			   struct dla_processor_group *group)
+{
+	return 1;
+}
+
+void
+dla_pdp_dump_config(struct dla_processor_group *group)
+{
+	struct dla_pdp_op_desc *pdp_op;
+	struct dla_pdp_surface_desc *pdp_surface;
+
+	pdp_surface = &group->surface_desc->pdp_surface;
+	pdp_op = &group->operation_desc->pdp_op;
+
+	dla_debug_pdp_surface_desc(pdp_surface, group->roi_index);
+	dla_debug_pdp_op_desc(pdp_op, group->roi_index);
+}
+
+int
+dla_pdp_program(struct dla_processor_group *group)
+{
+	int32_t ret;
+
+	dla_trace("Enter: %s", __func__);
+
+	if (!group) {
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	dla_enable_intr(MASK(GLB_S_INTR_MASK_0, PDP_DONE_MASK1) |
+			MASK(GLB_S_INTR_MASK_0, PDP_DONE_MASK0));
+
+	ret = processor_pdp_program(group);
+	if (ret)
+		goto exit;
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/rubik.c b/drivers/nvdla/rubik.c
new file mode 100644
index 000000000000..dd5196e08df8
--- /dev/null
+++ b/drivers/nvdla/rubik.c
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "common.h"
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+static uint8_t map_rubik_mode[] = {
+	FIELD_ENUM(RBK_D_MISC_CFG_0, RUBIK_MODE, CONTRACT),
+	FIELD_ENUM(RBK_D_MISC_CFG_0, RUBIK_MODE, SPLIT),
+	FIELD_ENUM(RBK_D_MISC_CFG_0, RUBIK_MODE, MERGE),
+};
+
+static uint8_t  map_ram_type[] = {
+	FIELD_ENUM(RBK_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, MCIF),
+	FIELD_ENUM(RBK_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE, CVIF),
+};
+
+static uint8_t  map_precision[] = {
+	FIELD_ENUM(RBK_D_MISC_CFG_0, IN_PRECISION, INT8),
+	FIELD_ENUM(RBK_D_MISC_CFG_0, IN_PRECISION, INT16),
+	FIELD_ENUM(RBK_D_MISC_CFG_0, IN_PRECISION, FP16),
+};
+
+static uint8_t map_bpe[] = {
+	BPE_PRECISION_INT8,
+	BPE_PRECISION_INT16,
+	BPE_PRECISION_FP16,
+};
+
+#if STAT_ENABLE
+void
+dla_rubik_stat_data(struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	uint64_t end_time = 0;
+	struct dla_rubik_stat_desc *rubik_stat;
+
+	rubik_stat = &processor->stat_data_desc->rubik_stat;
+
+	end_time = dla_get_time_us();
+
+	rubik_stat->read_stall = rubik_reg_read(D_PERF_READ_STALL);
+	rubik_stat->write_stall = rubik_reg_read(D_PERF_WRITE_STALL);
+	rubik_stat->runtime = (uint32_t)(end_time - group->start_time);
+}
+
+void
+dla_rubik_dump_stat(struct dla_processor *processor)
+{
+	struct dla_rubik_stat_desc *rubik_stat;
+
+	rubik_stat = &processor->stat_data_desc->rubik_stat;
+
+	dla_debug_rubik_stats(rubik_stat);
+}
+#endif /* STAT_ENABLE */
+
+void
+dla_rubik_set_producer(int32_t group_id, int32_t __unused)
+{
+	uint32_t reg;
+
+	/**
+	 * set producer pointer for all sub-modules
+	 */
+	reg = group_id << SHIFT(RBK_S_POINTER_0, PRODUCER);
+	rubik_reg_write(S_POINTER, reg);
+}
+
+int
+dla_rubik_enable(struct dla_processor_group *group)
+{
+	uint32_t reg;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_trace("Enter: %s", __func__);
+
+	if (engine->stat_enable == (uint32_t)1) {
+		rubik_reg_write(D_PERF_ENABLE, 1);
+		group->start_time = dla_get_time_us();
+	}
+
+	/**
+	 * enable all sub-modules
+	 */
+	reg = FIELD_ENUM(RBK_D_OP_ENABLE_0, OP_EN, ENABLE);
+	rubik_reg_write(D_OP_ENABLE, reg);
+
+	dla_trace("Exit: %s", __func__);
+
+	RETURN(0);
+}
+
+void
+dla_rubik_rdma_check(struct dla_processor_group *group)
+{
+	group->is_rdma_needed = 0;
+}
+
+static int32_t
+processor_rubik_program(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	uint32_t reg, high, low;
+	uint64_t input_address = 0;
+	uint64_t output_address = 0;
+	struct dla_engine *engine = dla_get_engine();
+	struct dla_rubik_op_desc *rubik_op;
+	struct dla_rubik_surface_desc *rubik_surface;
+
+	dla_trace("Enter: %s", __func__);
+
+	rubik_op = &group->operation_desc->rubik_op;
+	rubik_surface = &group->surface_desc->rubik_surface;
+
+	/* Argument check */
+	ASSERT_GOTO((rubik_surface->src_data.type != DLA_MEM_HW),
+		ret, ERR(INVALID_INPUT), exit);
+	ASSERT_GOTO((rubik_surface->dst_data.type != DLA_MEM_HW),
+		ret, ERR(INVALID_INPUT), exit);
+
+	/* get the addresses from task descriptor */
+	ret = dla_read_input_address(&rubik_surface->src_data,
+						&input_address,
+						group->op_desc->index,
+						group->roi_index,
+						1);
+	if (ret)
+		goto exit;
+
+	dla_get_dma_cube_address(engine->driver_context,
+				engine->task->task_data,
+				rubik_surface->dst_data.address,
+				rubik_surface->dst_data.offset,
+				(void *)&output_address,
+				DESTINATION_DMA);
+
+	/* config rubik */
+	reg = (((uint32_t)map_rubik_mode[rubik_op->mode]) <<
+			SHIFT(RBK_D_MISC_CFG_0, RUBIK_MODE)) |
+			(((uint32_t)map_precision[rubik_op->precision]) <<
+			SHIFT(RBK_D_MISC_CFG_0, IN_PRECISION));
+	rubik_reg_write(D_MISC_CFG, reg);
+	reg = (((uint32_t)map_ram_type[rubik_surface->src_data.type]) <<
+			SHIFT(RBK_D_DAIN_RAM_TYPE_0, DATAIN_RAM_TYPE));
+	rubik_reg_write(D_DAIN_RAM_TYPE, reg);
+	reg =  ((rubik_surface->src_data.width-1) <<
+			SHIFT(RBK_D_DATAIN_SIZE_0_0, DATAIN_WIDTH)) |
+			((rubik_surface->src_data.height-1) <<
+			SHIFT(RBK_D_DATAIN_SIZE_0_0, DATAIN_HEIGHT));
+	rubik_reg_write(D_DATAIN_SIZE_0, reg);
+	reg =  ((rubik_surface->src_data.channel-1) <<
+			SHIFT(RBK_D_DATAIN_SIZE_1_0, DATAIN_CHANNEL));
+	rubik_reg_write(D_DATAIN_SIZE_1, reg);
+
+	high = HIGH32BITS(input_address);
+	low = LOW32BITS(input_address);
+	rubik_reg_write(D_DAIN_ADDR_LOW, low);
+	rubik_reg_write(D_DAIN_ADDR_HIGH, high);
+	if (rubik_op->mode == RUBIK_MODE_MERGE) {
+		ASSERT_GOTO((rubik_surface->src_data.plane_stride != 0),
+			ret, ERR(INVALID_INPUT), exit);
+		ASSERT_GOTO(((rubik_surface->src_data.plane_stride&0x1F) == 0),
+			ret, ERR(INVALID_INPUT), exit);
+		rubik_reg_write(D_DAIN_PLANAR_STRIDE,
+			rubik_surface->src_data.plane_stride);
+	} else {
+		rubik_reg_write(D_DAIN_SURF_STRIDE,
+			rubik_surface->src_data.surf_stride);
+	}
+	rubik_reg_write(D_DAIN_LINE_STRIDE,
+				rubik_surface->src_data.line_stride);
+
+	reg = (((uint32_t)map_ram_type[rubik_surface->dst_data.type]) <<
+			SHIFT(RBK_D_DAOUT_RAM_TYPE_0, DATAOUT_RAM_TYPE));
+	rubik_reg_write(D_DAOUT_RAM_TYPE, reg);
+	reg =  ((rubik_surface->dst_data.channel-1) <<
+			SHIFT(RBK_D_DATAOUT_SIZE_1_0, DATAOUT_CHANNEL));
+	rubik_reg_write(D_DATAOUT_SIZE_1, reg);
+
+	high = HIGH32BITS(output_address);
+	low = LOW32BITS(output_address);
+	rubik_reg_write(D_DAOUT_ADDR_LOW, low);
+	rubik_reg_write(D_DAOUT_ADDR_HIGH, high);
+
+	rubik_reg_write(D_DAOUT_LINE_STRIDE,
+			rubik_surface->dst_data.line_stride);
+	if (rubik_op->mode != RUBIK_MODE_SPLIT) {
+		rubik_reg_write(D_DAOUT_SURF_STRIDE,
+				rubik_surface->dst_data.surf_stride);
+		if (rubik_op->mode == RUBIK_MODE_CONTRACT) {
+			reg = ((rubik_surface->dst_data.channel *
+				map_bpe[rubik_op->precision] + 31) >> 5) *
+				rubik_surface->src_data.surf_stride;
+			rubik_reg_write(D_CONTRACT_STRIDE_0, reg);
+
+			reg = rubik_op->stride_y *
+				rubik_surface->dst_data.line_stride;
+			rubik_reg_write(D_CONTRACT_STRIDE_1, reg);
+
+			reg = (((uint32_t)(rubik_op->stride_x-1)) <<
+			SHIFT(RBK_D_DECONV_STRIDE_0, DECONV_X_STRIDE)) |
+				(((uint32_t)(rubik_op->stride_y-1)) <<
+			SHIFT(RBK_D_DECONV_STRIDE_0, DECONV_Y_STRIDE));
+			rubik_reg_write(D_DECONV_STRIDE, reg);
+		}
+	} else {
+		rubik_reg_write(D_DAOUT_PLANAR_STRIDE,
+				rubik_surface->dst_data.plane_stride);
+	}
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+int
+dla_rubik_is_ready(struct dla_processor *processor,
+			     struct dla_processor_group *group)
+{
+	return 1;
+}
+
+void
+dla_rubik_dump_config(struct dla_processor_group *group)
+{
+	struct dla_rubik_op_desc *rubik_op;
+	struct dla_rubik_surface_desc *rubik_surface;
+
+	rubik_surface = &group->surface_desc->rubik_surface;
+	rubik_op = &group->operation_desc->rubik_op;
+
+	dla_debug_rubik_surface_desc(rubik_surface, group->roi_index);
+	dla_debug_rubik_op_desc(rubik_op, group->roi_index);
+}
+
+int
+dla_rubik_program(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_trace("Enter: %s", __func__);
+
+	if (!engine->config_data->rubik_enable) {
+		dla_error("RUBIK is not supported for this configuration\n");
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	dla_enable_intr(MASK(GLB_S_INTR_MASK_0, RUBIK_DONE_MASK1) |
+			MASK(GLB_S_INTR_MASK_0, RUBIK_DONE_MASK0));
+
+	ret = processor_rubik_program(group);
+	if (ret)
+		goto exit;
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
diff --git a/drivers/nvdla/scheduler.c b/drivers/nvdla/scheduler.c
new file mode 100644
index 000000000000..6a4cc24b2f29
--- /dev/null
+++ b/drivers/nvdla/scheduler.c
@@ -0,0 +1,1160 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_engine.h>
+#include <dla_err.h>
+#include <dla_interface.h>
+
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+#define MAX_NUM_ADDRESSES	256
+
+static uint64_t roi_array_length __aligned(8);
+static struct dla_network_desc network;
+
+static int
+dla_update_consumers(struct dla_processor_group *group,
+			struct dla_common_op_desc *op, uint8_t event);
+
+static int32_t
+dla_read_address_list(struct dla_engine *engine)
+{
+	RETURN(0);
+}
+
+int32_t
+dla_read_lut(struct dla_engine *engine, int16_t index, void *dst)
+{
+	int32_t ret = 0;
+	uint64_t src_addr;
+
+	if (index == -1) {
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	src_addr = engine->task->lut_data_addr;
+
+	ret = dla_data_read(engine->driver_context,
+			engine->task->task_data,
+			src_addr, (void *)dst,
+			sizeof(struct dla_lut_param),
+			(sizeof(struct dla_lut_param) * (uint64_t)index));
+
+exit:
+	RETURN(ret);
+}
+
+static int
+dla_op_enabled(struct dla_processor_group *group)
+{
+	int32_t ret;
+	struct dla_common_op_desc *op_desc;
+
+	dla_debug("Enter: %s\n", __func__);
+	op_desc = group->op_desc;
+
+	group->active = 1;
+
+	/* update dependency graph for this task */
+	ret = dla_update_consumers(group, op_desc, DLA_EVENT_OP_ENABLED);
+	dla_debug("Exit: %s\n", __func__);
+
+	RETURN(ret);
+}
+
+static int
+dla_op_programmed(struct dla_processor *processor,
+		  struct dla_processor_group *group,
+		  uint8_t rdma_id)
+{
+	int32_t ret;
+	struct dla_common_op_desc *op_desc;
+
+	dla_debug("Enter: %s\n", __func__);
+	op_desc = group->op_desc;
+
+	group->pending = 0;
+
+	/* update dependency graph for this task */
+	ret = dla_update_consumers(group, op_desc, DLA_EVENT_OP_PROGRAMMED);
+	dla_debug("Exit: %s\n", __func__);
+
+	RETURN(ret);
+}
+
+static int32_t
+dla_read_config(struct dla_task *task, struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	int32_t ret;
+	uint64_t base;
+	int16_t index;
+	uint8_t roi_index;
+	struct dla_engine *engine;
+
+	dla_debug("Enter: %s\n", __func__);
+
+	engine = dla_get_engine();
+
+	roi_index = group->roi_index;
+	index = group->op_desc->index;
+
+	base = (sizeof(union dla_operation_container) *
+			(uint64_t)engine->network->num_operations *
+			(uint64_t)roi_index);
+	base = base + (sizeof(union dla_operation_container) *
+			(uint64_t)index);
+
+	LOG_EVENT(roi_index, group->id, processor->op_type,
+					LOG_READ_OP_CONFIG_START);
+
+	ret = dla_data_read(engine->driver_context, task->task_data,
+				task->operation_desc_addr,
+				(void *)group->operation_desc,
+				sizeof(union dla_operation_container),
+				base);
+	if (ret)
+		goto exit;
+
+	LOG_EVENT(roi_index, group->id, processor->op_type,
+					LOG_READ_OP_CONFIG_END);
+
+	base = (sizeof(union dla_surface_container) *
+			(uint64_t)engine->network->num_operations *
+			(uint64_t)roi_index);
+
+	base = base + (sizeof(union dla_surface_container) *
+			(uint64_t)index);
+
+	LOG_EVENT(roi_index, group->id, processor->op_type,
+					LOG_READ_SURF_CONFIG_START);
+
+	ret = dla_data_read(engine->driver_context, task->task_data,
+				task->surface_desc_addr,
+				(void *)group->surface_desc,
+				sizeof(union dla_surface_container), base);
+	if (ret)
+		goto exit;
+
+	LOG_EVENT(roi_index, group->id, processor->op_type,
+					LOG_READ_SURF_CONFIG_END);
+
+	processor->dump_config(group);
+
+exit:
+	dla_debug("Exit: %s\n", __func__);
+	RETURN(ret);
+}
+
+static void
+dla_reset_group(struct dla_processor_group *group)
+{
+	int32_t i;
+
+	for (i = 0; i < DLA_OP_NUM; i++) {
+		dla_put_op_desc(group->consumers[i]);
+		group->consumers[i] = NULL;
+	}
+
+	dla_put_op_desc(group->fused_parent);
+	group->fused_parent = NULL;
+
+	dla_put_op_desc(group->op_desc);
+	group->op_desc = NULL;
+}
+
+static int
+dla_prepare_operation(struct dla_processor *processor,
+			struct dla_common_op_desc *op_desc,
+			uint8_t roi_index, uint32_t *group_number)
+{
+	int32_t ret = 0;
+	uint8_t group_id;
+	uint8_t rdma_id;
+	struct dla_processor_group *group;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	/*
+	 * If not already programmed then find out if
+	 * processor is free and which group is free
+	 */
+	ret = utils_get_free_group(processor, &group_id, &rdma_id);
+	if (ret) {
+		dla_debug("processor:%s register groups are busy\n",
+			processor->name);
+		goto exit;
+	} else {
+		dla_info("processor:%s group:%d, rdma_group:%d available\n",
+				processor->name, group_id, rdma_id);
+	}
+	*group_number = group_id;
+	group = &processor->groups[group_id];
+
+	/*
+	 * update operation descriptor
+	 */
+	group->op_desc = op_desc;
+	dla_get_refcount(op_desc);
+	group->id = group_id;
+	group->roi_index = roi_index;
+	group->rdma_id = rdma_id;
+
+	ret = dla_read_config(engine->task, processor, group);
+	if (ret)
+		goto exit;
+
+	group->pending = 1;
+
+	processor->group_status |= (1 << group->id);
+
+	processor->rdma_check(group);
+	if (group->is_rdma_needed) {
+		group->rdma_id = rdma_id;
+		processor->rdma_status |= (1 << rdma_id);
+	}
+
+	processor->tail_op = op_desc;
+exit:
+	dla_debug("Exit: %s status=%d\n", __func__, ret);
+	RETURN(ret);
+}
+
+static int
+dla_program_operation(struct dla_processor *processor,
+			struct dla_processor_group *group)
+{
+	int32_t i;
+	int32_t ret = 0;
+	struct dla_common_op_desc *op_desc;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter: %s\n", __func__);
+
+	dla_info("Program %s operation index %d ROI %d Group[%d]\n",
+					processor->name,
+					group->op_desc->index,
+					group->roi_index,
+					group->id);
+
+	group->programming = 1;
+
+	op_desc = group->op_desc;
+
+	processor->set_producer(group->id, group->rdma_id);
+
+	LOG_EVENT(group->roi_index, group->id, processor->op_type,
+						LOG_PROGRAM_START);
+
+	ret = processor->program(group);
+	if (ret)
+		goto exit;
+
+	LOG_EVENT(group->roi_index, group->id, processor->op_type,
+						LOG_PROGRAM_END);
+
+	/*
+	 * Pre-fetch consumers
+	 */
+	for (i = 0; i < DLA_OP_NUM; i++) {
+		group->consumers[i] = dla_get_op_desc(engine->task,
+					op_desc->consumers[i].index, i,
+					group->roi_index);
+	}
+
+	group->fused_parent = dla_get_op_desc(engine->task,
+					op_desc->fused_parent.index,
+					op_desc->op_type - 1,
+					group->roi_index);
+
+	if (group->fused_parent != NULL) {
+		if (group->fused_parent->op_type != (op_desc->op_type - 1)) {
+			dla_warn("Invalid fused op type");
+			ret = ERR(INVALID_INPUT);
+			goto exit;
+		}
+	}
+
+	ret = dla_op_programmed(processor, group, group->rdma_id);
+	if (!ret)
+		goto exit;
+
+exit:
+	group->programming = 0;
+	dla_debug("Exit: %s status=%d\n", __func__, ret);
+	RETURN(ret);
+}
+
+static int
+dla_enable_operation(struct dla_processor *processor,
+			struct dla_common_op_desc *op_desc)
+{
+	int32_t ret = 0;
+	int32_t group_id;
+	struct dla_engine *engine;
+	struct dla_processor_group *group;
+
+	dla_debug("Enter: %s\n", __func__);
+	assert(op_desc->dependency_count == 0);
+
+	/*
+	 * If some operation has reported error then skip
+	 * enabling next operations
+	 */
+	engine = dla_get_engine();
+	if (engine->status)
+		goto exit;
+
+	/*
+	 * Find out if operation is already programmed
+	 */
+	group_id = 0;
+	group = &processor->groups[group_id];
+	if ((processor->group_status & (1 << group_id)) &&
+			group->op_desc->index == op_desc->index &&
+			group->roi_index == op_desc->roi_index &&
+			!group->pending)
+		goto enable_op;
+
+	group_id = 1;
+	group = &processor->groups[group_id];
+	if ((processor->group_status & (1 << group_id)) &&
+			group->op_desc->index == op_desc->index &&
+			group->roi_index == op_desc->roi_index &&
+			!group->pending)
+		goto enable_op;
+
+	/*
+	 * Operation is not programmed yet, ignore
+	 */
+	dla_debug("exit %s without actual enable due to processor "
+				"hasn't been programmed\n", __func__);
+	goto exit;
+
+enable_op:
+	/*
+	 * If this event is triggered as part of programming same
+	 * group then skip enable, it will get enabled after programming
+	 * is complete
+	 */
+	if (group->programming)
+		goto exit;
+
+	if (group->active) {
+		dla_debug("Processor:%s already enabled on group:%d\n",
+			processor->name, group_id);
+		goto exit;
+	}
+
+	dla_info("Enable %s operation index %d ROI %d\n",
+					processor->name,
+					group->op_desc->index,
+					group->roi_index);
+
+	processor->set_producer(group->id, group->rdma_id);
+
+	LOG_EVENT(group->roi_index, group->id, processor->op_type,
+						LOG_OPERATION_START);
+
+	ret = processor->enable(group);
+	if (ret)
+		goto exit;
+
+	ret = dla_op_enabled(group);
+exit:
+	dla_debug("Exit: %s status=%d\n", __func__, ret);
+	RETURN(ret);
+}
+
+static int
+dla_submit_operation(struct dla_processor *processor,
+			struct dla_common_op_desc *op_desc,
+			uint8_t roi_index)
+{
+	int32_t err;
+	uint32_t group_id = 0;
+
+	dla_debug("Enter: %s\n", __func__);
+
+	dla_info("Prepare %s operation index %d ROI %d dep_count %d\n",
+			processor->name, op_desc->index, roi_index,
+			op_desc->dependency_count);
+	err = dla_prepare_operation(processor, op_desc, roi_index, &group_id);
+	if (err)
+		goto exit;
+
+	if (!processor->is_ready(processor, &processor->groups[group_id]))
+		goto exit;
+
+	err = dla_program_operation(processor, &processor->groups[group_id]);
+	if (err)
+		goto exit;
+
+	if (op_desc->dependency_count == 0)
+		err = dla_enable_operation(processor, op_desc);
+
+exit:
+	dla_debug("Exit: %s\n", __func__);
+	RETURN(err);
+}
+
+/*
+ * Dequeue next operation of same type from list of operations
+ */
+static int32_t
+dla_dequeue_operation(struct dla_engine *engine,
+			struct dla_processor *processor)
+{
+	int32_t ret = 0;
+	int16_t index;
+	struct dla_common_op_desc *consumer;
+
+	dla_debug("Enter: %s\n", __func__);
+
+	if (engine->status) {
+		dla_debug("Skip dequeue op as engine has reported error\n");
+		goto exit;
+	}
+
+	/*
+	 * If we are done processing all ROIs for current op then
+	 * load next op of same type otherwise reload same op for
+	 * next ROI.
+	 */
+	if (processor->roi_index == (engine->network->num_rois - 1)) {
+		index = processor->tail_op->consumers[processor->op_type].index;
+		if (-1 == index) {
+			/*
+			 * It means we are done processing
+			 * all ops of this type
+			 */
+			dla_debug("exit %s as there's no further operation\n",
+				processor->name);
+			goto exit;
+		}
+		processor->roi_index = 0;
+	} else {
+		processor->roi_index++;
+		index = processor->tail_op->index;
+	}
+
+	dla_debug("Dequeue op from %s processor, index=%d ROI=%d\n",
+			processor->name, index, processor->roi_index);
+
+	/*
+	 * Get operation descriptor
+	 */
+	consumer = dla_get_op_desc(engine->task, index,
+				processor->op_type, processor->roi_index);
+	if (consumer == NULL) {
+		ret = ERR(NO_MEM);
+		dla_error("Failed to allocate op_desc");
+		goto exit;
+	}
+
+	ret = dla_submit_operation(processor, consumer, processor->roi_index);
+	dla_put_op_desc(consumer);
+
+exit:
+	dla_debug("Exit: %s\n", __func__);
+	RETURN(ret);
+}
+
+static int
+dla_update_dependency(struct dla_consumer *consumer,
+			struct dla_common_op_desc *op_desc,
+			uint8_t event, uint8_t roi_index)
+{
+	int32_t ret = 0;
+	struct dla_processor *processor;
+	struct dla_engine *engine = dla_get_engine();
+
+	if (consumer->index == -1)
+		goto exit;
+
+	/* Update dependency only if event matches */
+	if (event != consumer->event)
+		goto exit;
+
+	/*
+	 * If consumer index is valid but op desc is NULL means
+	 * op desc for consumer was not pre-fetched
+	 */
+	if (op_desc == NULL) {
+		ret = ERR(INVALID_INPUT);
+		dla_error("Operation descriptor is NULL, consumer index %d",
+				consumer->index);
+		goto exit;
+	}
+
+	assert(op_desc->dependency_count > 0);
+
+	dla_debug("Update dependency operation index %d ROI %d DEP_COUNT=%d\n",
+					op_desc->index, op_desc->roi_index,
+					op_desc->dependency_count);
+	op_desc->dependency_count--;
+
+	if (op_desc->dependency_count == 0) {
+		processor = &engine->processors[op_desc->op_type];
+		dla_debug("enable %s in %s as depdency are resolved\n",
+			processor->name, __func__);
+
+		ret = dla_enable_operation(processor, op_desc);
+		if (ret)
+			goto exit;
+	}
+exit:
+	RETURN(ret);
+}
+
+static int
+dla_update_consumers(struct dla_processor_group *group,
+		     struct dla_common_op_desc *op,
+		     uint8_t event)
+{
+	int32_t i;
+	int32_t ret = 0;
+	struct dla_engine *engine = dla_get_engine();
+
+	if (engine->status) {
+		dla_debug("Skip update as engine has reported error\n");
+		goto exit;
+	}
+
+	for (i = 0; i < DLA_OP_NUM; i++) {
+		ret = dla_update_dependency(&op->consumers[i],
+						group->consumers[i],
+						event, group->roi_index);
+		if (ret) {
+			dla_error("Failed to update dependency for "
+				"consumer %d, ROI %d", i, group->roi_index);
+			goto exit;
+		}
+	}
+
+	ret = dla_update_dependency(&op->fused_parent,
+					group->fused_parent,
+					event, group->roi_index);
+	if (ret) {
+		dla_error("Failed to update dependency for "
+			"fused parent, ROI %d", group->roi_index);
+		goto exit;
+	}
+
+exit:
+	RETURN(ret);
+}
+
+/*
+ * Handle operation completion notification
+ */
+int
+dla_op_completion(struct dla_processor *processor,
+		  struct dla_processor_group *group)
+{
+	int32_t ret;
+#if STAT_ENABLE
+	uint64_t stat_data_address;
+	uint64_t stat_base;
+#endif /* STAT_ENABLE */
+	struct dla_task *task;
+	struct dla_common_op_desc *op_desc;
+	struct dla_processor_group *next_group;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_debug("Enter:%s processor %s group%u\n", __func__,
+					processor->name, group->id);
+
+	dla_info("Completed %s operation index %d ROI %d\n",
+					processor->name,
+					group->op_desc->index,
+					group->roi_index);
+
+	task = engine->task;
+
+	/*
+	 * Mark OP as done only when all ROIs are done for that
+	 * operation
+	 */
+	if (group->roi_index == (engine->network->num_rois - 1))
+		engine->num_proc_hwl++;
+
+	op_desc = group->op_desc;
+
+#if STAT_ENABLE
+	if (engine->stat_enable == (uint32_t)1) {
+		processor->get_stat_data(processor, group);
+
+		processor->dump_stat(processor);
+
+		stat_data_address = (uint64_t)(engine->task->stat_data_addr +
+				(sizeof(union dla_stat_container) *
+				(uint64_t)(engine->network->num_operations) *
+				(uint64_t)(op_desc->roi_index)));
+
+		stat_base = (stat_data_address +
+				(sizeof(union dla_stat_container) *
+				(uint64_t)op_desc->index));
+
+		/*
+		 * Flush stat descriptor to DRAM
+		 */
+		ret = dla_data_write(engine->driver_context, task->task_data,
+					(void *)(processor->stat_data_desc),
+					stat_base,
+					sizeof(union dla_stat_container),
+					0);
+		if (ret < 0)
+			dla_error("Failed to write stats to DMA memory\n");
+	}
+#endif /* STAT_ENABLE */
+
+	/*
+	 * Get an extra reference count to keep op descriptor
+	 * in cache until this operation completes
+	 */
+	dla_get_refcount(op_desc);
+
+	LOG_EVENT(group->roi_index, group->id, processor->op_type,
+						LOG_OPERATION_END);
+
+	processor->group_status &= ~(1 << group->id);
+	if (group->is_rdma_needed) {
+		group->is_rdma_needed = 0;
+		processor->rdma_status &= ~(1 << group->rdma_id);
+		group->rdma_id = 0;
+	}
+	group->active = 0;
+	group->lut_index = -1;
+	processor->last_group = group->id;
+
+	/*
+	 * Switch consumer pointer to next group
+	 */
+	processor->consumer_ptr = !group->id;
+
+	/*
+	 * update dependency graph for this task
+	 * TODO: Add proper error handling
+	 */
+	ret = dla_update_consumers(group, op_desc, DLA_EVENT_OP_COMPLETED);
+	if (ret)
+		goto exit;
+
+	dla_info("%d HWLs done, totally %d layers\n",
+				engine->num_proc_hwl,
+				engine->network->num_operations);
+
+	/* free operation descriptor from cache */
+	dla_reset_group(group);
+
+	/* if not hwl pending, means network completed */
+	if (engine->network->num_operations == engine->num_proc_hwl) {
+		dla_put_op_desc(op_desc);
+		goto exit;
+	}
+
+	next_group = &processor->groups[!group->id];
+	if (next_group->pending && !engine->status) {
+		/*
+		 * Next group must be ready here for programming,
+		 * if not means it is an error
+		 */
+		if (!processor->is_ready(processor, next_group))
+			goto dequeue_op;
+
+		ret = dla_program_operation(processor, next_group);
+		if (ret)
+			goto exit;
+
+		if (next_group->op_desc->dependency_count != 0)
+			goto dequeue_op;
+
+		ret = dla_enable_operation(processor,
+					   next_group->op_desc);
+		if (ret)
+			goto exit;
+	}
+
+dequeue_op:
+	/* dequeue operation from this processor */
+	ret = dla_dequeue_operation(engine, processor);
+
+exit:
+	dla_put_op_desc(op_desc);
+	dla_debug("Exit:%s processor %s group%u status=%d\n",
+				__func__, processor->name,
+				group->id, ret);
+
+	RETURN(ret);
+}
+
+/*
+ * Read network configuration from DRAM, network descriptor address
+ * is always first in the address list. Network configuration contains
+ * offset in address list for addresses of other lists used to
+ * execute network
+ *
+ * @engine: Engine instance
+ * @return: 0 for success
+ */
+static int
+dla_read_network_config(struct dla_engine *engine)
+{
+	int32_t ret;
+	uint64_t network_addr;
+	struct dla_task *task = engine->task;
+
+	dla_debug("Enter:%s\n", __func__);
+
+	/*
+	 * Read address list from DRAM to DMEM
+	 */
+	ret = dla_read_address_list(engine);
+	if (ret) {
+		dla_error("Failed to read address list");
+		goto exit;
+	}
+
+	/*
+	 * Read network descriptor address from address list. It is always
+	 * at index 0.
+	 */
+	ret = dla_get_dma_address(engine->driver_context, task->task_data,
+						0, (void *)&network_addr,
+						DESTINATION_PROCESSOR);
+	if (ret) {
+		dla_error("Failed to read network desc address");
+		goto exit;
+	}
+
+	/*
+	 * Read network descriptor, it has information for a network
+	 * such as all address indexes.
+	 */
+	ret = dla_data_read(engine->driver_context, task->task_data,
+				network_addr, (void *)&network,
+				sizeof(struct dla_network_desc),
+				0);
+	if (ret) {
+		dla_error("Failed to read network descriptor");
+		goto exit;
+	}
+
+	dla_debug_network_desc(&network);
+
+	if (network.num_operations == 0)
+		goto exit;
+
+	/*
+	 * Read operation descriptor list address from address list
+	 */
+	ret = dla_get_dma_address(engine->driver_context, task->task_data,
+				network.operation_desc_index,
+				(void *)&task->operation_desc_addr,
+				DESTINATION_PROCESSOR);
+	if (ret) {
+		dla_error("Failed to read operation desc list address");
+		goto exit;
+	}
+
+	/*
+	 * Read surface descriptor list address from address list
+	 */
+	ret = dla_get_dma_address(engine->driver_context, task->task_data,
+				network.surface_desc_index,
+				(void *)&task->surface_desc_addr,
+				DESTINATION_PROCESSOR);
+	if (ret) {
+		dla_error("Failed to read surface desc list address");
+		goto exit;
+	}
+
+	/*
+	 * Read dependency graph address from address list
+	 */
+	ret = dla_get_dma_address(engine->driver_context, task->task_data,
+				network.dependency_graph_index,
+				(void *)&task->dependency_graph_addr,
+				DESTINATION_PROCESSOR);
+	if (ret) {
+		dla_error("Failed to ready dependency graph address");
+		goto exit;
+	}
+
+	/*
+	 * Read LUT data list address from address list
+	 */
+	if (network.num_luts) {
+		ret = dla_get_dma_address(engine->driver_context,
+					task->task_data,
+					network.lut_data_index,
+					(void *)&task->lut_data_addr,
+					DESTINATION_PROCESSOR);
+		if (ret) {
+			dla_error("Failed to read LUT list address");
+			goto exit;
+		}
+	}
+
+	/*
+	 * Read address for ROI information
+	 */
+	if (network.dynamic_roi) {
+		/*
+		 * Read ROI array address from address list
+		 */
+		ret = dla_get_dma_address(engine->driver_context,
+					task->task_data,
+					network.roi_array_index,
+					(void *)&task->roi_array_addr,
+					DESTINATION_PROCESSOR);
+		if (ret) {
+			dla_error("Failed to read ROI array address");
+			goto exit;
+		}
+
+		ret = dla_data_read(engine->driver_context, task->task_data,
+					task->roi_array_addr,
+					(void *)&roi_array_length,
+					sizeof(uint64_t),
+					0);
+		if (ret) {
+			dla_error("Failed to read ROI array length");
+			goto exit;
+		}
+
+		/*
+		 * Number of ROIs detected can't be greater than maximum number
+		 * ROIs this network can process
+		 */
+		if (roi_array_length > network.num_rois) {
+			dla_error("Invalid number of ROIs detected");
+			ret = ERR(INVALID_INPUT);
+			goto exit;
+		}
+
+		network.num_rois = roi_array_length;
+
+		/*
+		 * Read surface address from address list
+		 */
+		ret = dla_get_dma_address(engine->driver_context,
+						task->task_data,
+						network.surface_index,
+						(void *)&task->surface_addr,
+						DESTINATION_DMA);
+		if (ret) {
+			dla_error("Failed to read surface address");
+			goto exit;
+		}
+	}
+
+#if STAT_ENABLE
+	if (network.stat_list_index != -1) {
+		ret = dla_get_dma_address(engine->driver_context,
+						task->task_data,
+						network.stat_list_index,
+						(void *)&task->stat_data_addr,
+						DESTINATION_PROCESSOR);
+		if (ret) {
+			dla_error("Failed to read stat address");
+			goto exit;
+		}
+	}
+#endif /* STAT_ENABLE */
+
+exit:
+	dla_debug("Exit:%s status=%d\n", __func__, ret);
+	RETURN(ret);
+}
+
+static int
+dla_initiate_processors(struct dla_engine *engine)
+{
+	int32_t i;
+	int32_t ret = 0;
+	int16_t index;
+	struct dla_processor *processor;
+	struct dla_common_op_desc *consumer;
+	struct dla_network_desc *nw;
+
+	dla_debug("Enter: %s\n", __func__);
+
+	if (!engine) {
+		ret = ERR(INVALID_INPUT);
+		goto exit;
+	}
+
+	nw = engine->network;
+
+	/* Validate operation heads before initiating processors */
+	for (i = 0; i < DLA_OP_NUM; i++) {
+		if (nw->op_head[i] >= nw->num_operations) {
+			ret = ERR(INVALID_INPUT);
+			dla_error("Invalid op_head %d for op %d",
+						nw->op_head[i], i);
+			goto exit;
+		}
+	}
+
+	for (i = 0; i < DLA_OP_NUM; i++) {
+		index = nw->op_head[i];
+
+		/* If there is no op for this type then continue */
+		if (-1 == index)
+			continue;
+
+		consumer = dla_get_op_desc(engine->task, index, i, 0);
+		/*
+		 * if consumer is NULL, it means either data copy error
+		 * or cache insufficient - we should fix it
+		 */
+		if (consumer == NULL) {
+			dla_error("Failed to allocate memory for op_head[%d]=%d",
+							i, index);
+			ret = ERR(NO_MEM);
+			goto exit;
+		}
+
+		processor = &engine->processors[consumer->op_type];
+
+		ret = dla_submit_operation(processor, consumer, 0);
+		dla_put_op_desc(consumer);
+		if (ret && ret != ERR(PROCESSOR_BUSY)) {
+			dla_error("Failed to submit %s op from index %u\n",
+						processor->name, index);
+			goto exit;
+		}
+
+		ret = dla_dequeue_operation(engine, processor);
+		if (ret) {
+			dla_error("Failed to dequeue op for %s processor",
+							processor->name);
+			goto exit;
+		}
+	}
+exit:
+	dla_debug("Exit: %s status=%d\n", __func__, ret);
+	RETURN(ret);
+}
+
+static int
+dla_handle_events(struct dla_processor *processor)
+{
+	int32_t j;
+	int32_t ret = 0;
+	uint8_t group_id;
+	struct dla_processor_group *group;
+
+	dla_debug("Enter:%s, processor:%s\n", __func__, processor->name);
+
+	group_id = !processor->last_group;
+
+	for (j = 0; j < DLA_NUM_GROUPS; j++) {
+		group = &processor->groups[group_id];
+
+		if ((1 << DLA_EVENT_CDMA_WT_DONE) & group->events) {
+			dla_info("Handle cdma weight done event, processor %s "
+				"group %u\n", processor->name, group->id);
+
+			ret = dla_update_consumers(group,
+						   group->op_desc,
+						   DLA_EVENT_CDMA_WT_DONE);
+			if (ret)
+				goto exit;
+		}
+
+		if ((1 << DLA_EVENT_CDMA_DT_DONE) & group->events) {
+			dla_info("Handle cdma data done event, processor %s "
+				"group %u\n", processor->name, group->id);
+
+			ret = dla_update_consumers(group,
+						   group->op_desc,
+						   DLA_EVENT_CDMA_DT_DONE);
+			if (ret)
+				goto exit;
+		}
+
+		/*
+		 * Handle complete after all other events
+		 */
+		if ((1 << DLA_EVENT_OP_COMPLETED) & group->events) {
+			dla_info("Handle op complete event, processor %s "
+				"group %u\n", processor->name, group->id);
+
+			ret = dla_op_completion(processor, group);
+			if (ret)
+				goto exit;
+		}
+
+		/*
+		 * Clear all events
+		 */
+		group->events = 0;
+		group_id = !group_id;
+	}
+exit:
+	dla_debug("Exit:%s, ret:%x\n", __func__, ret);
+	RETURN(ret);
+}
+
+int
+dla_process_events(void *engine_context, uint32_t *task_complete)
+{
+	int32_t i;
+	int32_t ret = 0;
+	struct dla_engine *engine = (struct dla_engine *)engine_context;
+
+	for (i = 0; i < DLA_OP_NUM; i++) {
+		struct dla_processor *processor;
+
+		processor = &engine->processors[i];
+		ret = dla_handle_events(processor);
+		/*
+		 * Incase engine status is non-zero, then don't
+		 * update the engine status. We should keep its
+		 * status for later cleaning of engine.
+		 */
+		if (!engine->status)
+			engine->status = ret;
+	}
+
+	if (engine->network->num_operations == engine->num_proc_hwl)
+		*task_complete = 1;
+
+	RETURN(ret);
+}
+
+/*
+ * Execute task selected by task scheduler
+ *
+ * 1. Read network configuration for the task
+ * 2. Initiate processors with head of list for same op
+ * 3. Start processing events received
+ */
+int
+dla_execute_task(void *engine_context, void *task_data, void *config_data)
+{
+	int32_t ret;
+	struct dla_engine *engine = (struct dla_engine *)engine_context;
+
+	if (engine == NULL) {
+		dla_error("engine is NULL\n");
+		ret = ERR(INVALID_INPUT);
+		goto complete;
+	}
+
+	if (engine->task == NULL) {
+		dla_error("task is NULL\n");
+		ret = ERR(INVALID_INPUT);
+		goto complete;
+	}
+
+	if (engine->task->task_data != NULL) {
+		/* We have on the fly tasks running */
+		dla_warn("Already some task in progress");
+		ret = ERR(PROCESSOR_BUSY);
+		goto complete;
+	}
+
+	engine->task->task_data = task_data;
+	engine->config_data = config_data;
+	engine->network = &network;
+	engine->num_proc_hwl = 0;
+	engine->stat_enable = 0;
+
+	LOG_EVENT(0, 0, 0, LOG_TASK_START);
+
+	ret = dla_read_network_config(engine);
+	if (ret)
+		goto complete;
+
+	dla_debug_address_info(engine->task);
+
+	/*
+	 * If no operations in a task means nothing to do, NULL task
+	 */
+	if (engine->network->num_operations == 0)
+		goto complete;
+
+#if STAT_ENABLE
+	if (network.stat_list_index != -1)
+		engine->stat_enable = 1;
+#endif /* STAT_ENABLE */
+
+	ret = dla_initiate_processors(engine);
+	engine->status = ret;
+
+complete:
+	LOG_EVENT(0, 0, 0, LOG_TASK_END);
+
+	RETURN(ret);
+}
+
+void
+dla_clear_task(void *engine_context)
+{
+	int32_t i, j;
+	struct dla_engine *engine = (struct dla_engine *)engine_context;
+
+	for (i = 0; i < DLA_OP_NUM; i++) {
+		struct dla_processor *processor = &engine->processors[i];
+
+		processor->roi_index = 0;
+		processor->group_status = 0;
+		processor->rdma_status = 0;
+
+		processor->tail_op = NULL;
+
+		for (j = 0; j < DLA_NUM_GROUPS; j++) {
+			struct dla_processor_group *group =
+						&processor->groups[j];
+
+			group->rdma_id = group->id;
+			group->active = 0;
+			group->events = 0;
+			group->roi_index = 0;
+			group->is_rdma_needed = 0;
+			group->lut_index = -1;
+		}
+	}
+
+	engine->task->task_data = NULL;
+	engine->network = NULL;
+	engine->num_proc_hwl = 0;
+	engine->status = 0;
+	engine->stat_enable = 0;
+
+	dla_info("reset engine done\n");
+}
diff --git a/drivers/nvdla/sdp.c b/drivers/nvdla/sdp.c
new file mode 100644
index 000000000000..44977405a43f
--- /dev/null
+++ b/drivers/nvdla/sdp.c
@@ -0,0 +1,817 @@
+/*
+ * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <opendla.h>
+#include <dla_debug.h>
+#include <dla_interface.h>
+
+#include "common.h"
+#include "dla_engine_internal.h"
+#include "engine_debug.h"
+
+static const uint8_t map_ena[] = {
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DISABLE, YES),
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DISABLE, NO),
+};
+
+static const uint8_t map_prelu[] = {
+	FIELD_ENUM(SDP_D_DP_BS_CFG_0, BS_MUL_PRELU, NO),
+	FIELD_ENUM(SDP_D_DP_BS_CFG_0, BS_MUL_PRELU, YES),
+};
+
+static const uint8_t map_bypass[] = {
+	FIELD_ENUM(SDP_D_DP_BS_CFG_0, BS_BYPASS, YES),
+	FIELD_ENUM(SDP_D_DP_BS_CFG_0, BS_BYPASS, NO),
+};
+
+static const uint8_t map_alu_op[] = {
+	FIELD_ENUM(SDP_D_DP_EW_CFG_0, EW_ALU_ALGO, MAX),
+	FIELD_ENUM(SDP_D_DP_EW_CFG_0, EW_ALU_ALGO, MIN),
+	FIELD_ENUM(SDP_D_DP_EW_CFG_0, EW_ALU_ALGO, SUM),
+	FIELD_ENUM(SDP_D_DP_EW_CFG_0, EW_ALU_ALGO, EQL),
+};
+
+static const uint8_t map_alu_src[] = {
+	FIELD_ENUM(SDP_D_DP_BS_ALU_CFG_0, BS_ALU_SRC, MEM),
+	FIELD_ENUM(SDP_D_DP_BS_ALU_CFG_0, BS_ALU_SRC, REG),
+};
+
+static const uint8_t map_fly[] = {
+	FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, FLYING_MODE, OFF),
+	FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, FLYING_MODE, ON),
+};
+
+static const uint8_t map_dst[] = {
+	FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, OUTPUT_DST, MEM),
+	FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, OUTPUT_DST, PDP),
+};
+
+
+static const uint8_t map_wg[] = {
+	FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, WINOGRAD, OFF),
+	FIELD_ENUM(SDP_D_FEATURE_MODE_CFG_0, WINOGRAD, ON),
+};
+
+static const uint8_t map_precision[] = {
+	FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
+	FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT16),
+	FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, FP16),
+};
+
+static const uint32_t map_proc_precision[3][3] = {
+	{
+		FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
+		FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
+		FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, FP16),
+	},
+	{
+		FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
+		FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT16),
+		FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, FP16),
+	},
+	{
+		FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT8),
+		FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, INT16),
+		FIELD_ENUM(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION, FP16),
+	},
+};
+
+static const uint8_t map_op_type[] = {
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_USE, MUL),
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_USE, MUL),
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_USE, ALU),
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_USE, BOTH),
+};
+
+static const uint8_t map_element_size[] = {
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_SIZE, ONE_BYTE),
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_SIZE, TWO_BYTE),
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_SIZE, TWO_BYTE),
+};
+
+static const uint8_t map_op_mode[] = {
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_MODE, PER_ELEMENT),
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_MODE, PER_KERNEL),
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DATA_MODE, PER_ELEMENT),
+};
+
+static const uint8_t map_ram_type[] = {
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_RAM_TYPE, MC),
+	FIELD_ENUM(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_RAM_TYPE, CV),
+};
+
+static const uint8_t map_perf_dma[] = {
+	FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_DMA_EN, NO),
+	FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_DMA_EN, YES),
+};
+
+static const uint8_t map_perf_lut[] = {
+	FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_LUT_EN, NO),
+	FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_LUT_EN, YES),
+};
+
+static const uint8_t map_perf_sat[] = {
+	FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_SAT_EN, NO),
+	FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_SAT_EN, YES),
+};
+
+static const uint8_t map_perf_nan_inf[] = {
+	FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_NAN_INF_COUNT_EN, NO),
+	FIELD_ENUM(SDP_D_PERF_ENABLE_0, PERF_NAN_INF_COUNT_EN, YES),
+};
+
+#if STAT_ENABLE
+void
+dla_sdp_stat_data(struct dla_processor *processor,
+					struct dla_processor_group *group)
+{
+	uint64_t end_time = 0;
+	struct dla_sdp_stat_desc *sdp_stat;
+
+	sdp_stat = &processor->stat_data_desc->sdp_stat;
+
+	end_time = dla_get_time_us();
+
+	sdp_stat->nan_input_num = sdp_reg_read(D_STATUS_NAN_INPUT_NUM);
+	sdp_stat->inf_input_num = sdp_reg_read(D_STATUS_INF_INPUT_NUM);
+	sdp_stat->nan_output_num = sdp_reg_read(D_STATUS_NAN_OUTPUT_NUM);
+	sdp_stat->wdma_write_stall = sdp_reg_read(D_PERF_WDMA_WRITE_STALL);
+	sdp_stat->runtime = (uint32_t)(end_time - group->start_time);
+}
+
+void
+dla_sdp_dump_stat(struct dla_processor *processor)
+{
+	struct dla_sdp_stat_desc *sdp_stat;
+
+	sdp_stat = &processor->stat_data_desc->sdp_stat;
+
+	dla_debug_sdp_stats(sdp_stat);
+}
+#endif /* STAT_ENABLE */
+
+void
+dla_sdp_set_producer(int32_t group_id, int32_t rdma_group_id)
+{
+	uint32_t reg;
+
+	/**
+	 * set producer pointer for all sub-modules
+	 */
+	reg = group_id << SHIFT(SDP_S_POINTER_0, PRODUCER);
+	sdp_reg_write(S_POINTER, reg);
+	reg = rdma_group_id << SHIFT(SDP_RDMA_S_POINTER_0, PRODUCER);
+	sdp_rdma_reg_write(S_POINTER, reg);
+}
+
+int
+dla_sdp_enable(struct dla_processor_group *group)
+{
+	uint32_t reg;
+	uint8_t perf_reg;
+	struct dla_engine *engine = dla_get_engine();
+
+	dla_trace("Enter: %s", __func__);
+
+	if (engine->stat_enable == (uint32_t)1) {
+		perf_reg = (map_perf_dma[1] <<
+			SHIFT(SDP_D_PERF_ENABLE_0, PERF_DMA_EN)) |
+			(map_perf_lut[1] <<
+			SHIFT(SDP_D_PERF_ENABLE_0, PERF_LUT_EN)) |
+			(map_perf_sat[1] <<
+			SHIFT(SDP_D_PERF_ENABLE_0, PERF_SAT_EN)) |
+			(map_perf_nan_inf[1] <<
+			SHIFT(SDP_D_PERF_ENABLE_0, PERF_NAN_INF_COUNT_EN));
+
+		sdp_reg_write(D_PERF_ENABLE, perf_reg);
+		group->start_time = dla_get_time_us();
+	}
+
+	/**
+	 * enable all sub-modules
+	 */
+	if (group->is_rdma_needed) {
+		reg = FIELD_ENUM(SDP_RDMA_D_OP_ENABLE_0, OP_EN, ENABLE);
+		sdp_rdma_reg_write(D_OP_ENABLE, reg);
+	}
+	reg = FIELD_ENUM(SDP_D_OP_ENABLE_0, OP_EN, ENABLE);
+	sdp_reg_write(D_OP_ENABLE, reg);
+
+	dla_trace("Exit: %s", __func__);
+
+	RETURN(0);
+}
+
+void
+dla_sdp_rdma_check(struct dla_processor_group *group)
+{
+	uint8_t x1_rdma_ena;
+	uint8_t x2_rdma_ena;
+	uint8_t y_rdma_ena;
+	uint8_t fly;
+	struct dla_sdp_op_desc *sdp_op;
+	struct dla_sdp_surface_desc *sdp_surface;
+
+	sdp_op = &group->operation_desc->sdp_op;
+	sdp_surface = &group->surface_desc->sdp_surface;
+
+	x1_rdma_ena = sdp_op->x1_op.enable;
+	x2_rdma_ena = sdp_op->x2_op.enable;
+	y_rdma_ena  = sdp_op->y_op.enable;
+
+	x1_rdma_ena &= (sdp_op->x1_op.mode != SDP_OP_PER_LAYER);
+	x2_rdma_ena &= (sdp_op->x2_op.mode != SDP_OP_PER_LAYER);
+	y_rdma_ena &= (sdp_op->y_op.mode != SDP_OP_PER_LAYER);
+
+	fly = sdp_surface->src_data.type == DLA_MEM_HW;
+
+	group->is_rdma_needed = (!fly) || (x1_rdma_ena ||
+					x2_rdma_ena || y_rdma_ena);
+}
+
+static int32_t
+processor_sdp_program(struct dla_processor_group *group)
+{
+	int32_t ret = 0;
+	uint64_t src_addr = -1, x1_addr = -1, x2_addr = -1;
+	uint64_t  y_addr = -1, dst_addr = -1;
+	uint32_t reg, high, low;
+	uint8_t fly;
+	uint32_t __maybe_unused atom_size;
+	struct dla_sdp_op *x1_op;
+	struct dla_sdp_op *x2_op;
+	struct dla_sdp_op *y_op;
+	uint8_t x1_rdma_ena;
+	uint8_t x2_rdma_ena;
+	uint8_t y_rdma_ena;
+	uint8_t out_dma_ena;
+	struct dla_lut_param lut;
+	struct dla_engine *engine = dla_get_engine();
+	struct dla_sdp_op_desc *sdp_op;
+	struct dla_sdp_surface_desc *sdp_surface;
+
+	dla_trace("Enter: %s", __func__);
+	atom_size = engine->config_data->atom_size;
+
+	sdp_op = &group->operation_desc->sdp_op;
+	sdp_surface = &group->surface_desc->sdp_surface;
+
+	fly = sdp_surface->src_data.type == DLA_MEM_HW;
+	out_dma_ena = sdp_surface->dst_data.type != DLA_MEM_HW;
+	x1_op = &sdp_op->x1_op;
+	x2_op = &sdp_op->x2_op;
+	y_op = &sdp_op->y_op;
+	x1_rdma_ena = x1_op->enable && x1_op->type != SDP_OP_NONE;
+	x2_rdma_ena = x2_op->enable && x2_op->type != SDP_OP_NONE;
+	y_rdma_ena  = y_op->enable && y_op->type != SDP_OP_NONE;
+
+	/* load address */
+	if (!fly) {
+		ret = dla_read_input_address(&sdp_surface->src_data,
+						&src_addr,
+						group->op_desc->index,
+						group->roi_index,
+					    1);
+		if (ret)
+			goto exit;
+		CHECK_ALIGN(src_addr, atom_size);
+	}
+
+	if (out_dma_ena) {
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					sdp_surface->dst_data.address,
+					sdp_surface->dst_data.offset,
+					(void *)&dst_addr,
+					DESTINATION_DMA);
+		CHECK_ALIGN(dst_addr, atom_size);
+	}
+
+	if (sdp_op->lut_index >= 0) {
+		group->lut_index = sdp_op->lut_index;
+		dla_read_lut(engine, sdp_op->lut_index, (void *)&lut);
+		dla_debug_lut_params(&lut);
+	}
+
+
+	x1_rdma_ena &= (x1_op->mode != SDP_OP_PER_LAYER);
+	x2_rdma_ena &= (x2_op->mode != SDP_OP_PER_LAYER);
+	y_rdma_ena &= (y_op->mode != SDP_OP_PER_LAYER);
+
+	if (x1_rdma_ena) {
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					sdp_surface->x1_data.address,
+					sdp_surface->x1_data.offset,
+					(void *)&x1_addr,
+					DESTINATION_DMA);
+		CHECK_ALIGN(x1_addr, atom_size);
+	}
+	if (x2_rdma_ena) {
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					sdp_surface->x2_data.address,
+					sdp_surface->x2_data.offset,
+					(void *)&x2_addr,
+					DESTINATION_DMA);
+		CHECK_ALIGN(x2_addr, atom_size);
+	}
+	if (y_rdma_ena) {
+		dla_get_dma_cube_address(engine->driver_context,
+					engine->task->task_data,
+					sdp_surface->y_data.address,
+					sdp_surface->y_data.offset,
+					(void *)&y_addr,
+					DESTINATION_DMA);
+		CHECK_ALIGN(y_addr, atom_size);
+	}
+
+	reg = (map_fly[0] << SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, FLYING_MODE));
+	sdp_rdma_reg_write(D_FEATURE_MODE_CFG, reg);
+
+	reg = (map_ena[1] << SHIFT(SDP_RDMA_D_BRDMA_CFG_0, BRDMA_DISABLE));
+	sdp_rdma_reg_write(D_BRDMA_CFG, reg);
+	reg = (map_ena[1] << SHIFT(SDP_RDMA_D_NRDMA_CFG_0, NRDMA_DISABLE));
+	sdp_rdma_reg_write(D_NRDMA_CFG, reg);
+	reg = (map_ena[1] << SHIFT(SDP_RDMA_D_ERDMA_CFG_0, ERDMA_DISABLE));
+	sdp_rdma_reg_write(D_ERDMA_CFG, reg);
+
+	reg = (map_fly[fly] <<
+			SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, FLYING_MODE)) |
+	(map_wg[sdp_op->conv_mode == CONV_MODE_WINOGRAD] <<
+			SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, WINOGRAD)) |
+	(map_precision[sdp_op->src_precision] <<
+			SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, IN_PRECISION)) |
+	(map_precision[sdp_op->dst_precision] <<
+			SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, OUT_PRECISION)) |
+	(map_proc_precision[sdp_op->dst_precision][sdp_op->src_precision] <<
+			SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, PROC_PRECISION)) |
+	((sdp_op->batch_num-1) <<
+			SHIFT(SDP_RDMA_D_FEATURE_MODE_CFG_0, BATCH_NUMBER));
+	sdp_rdma_reg_write(D_FEATURE_MODE_CFG, reg);
+
+	if (group->is_rdma_needed) {
+
+		sdp_rdma_reg_write(D_DATA_CUBE_WIDTH,
+					sdp_surface->src_data.width - 1);
+		sdp_rdma_reg_write(D_DATA_CUBE_HEIGHT,
+					sdp_surface->src_data.height - 1);
+		sdp_rdma_reg_write(D_DATA_CUBE_CHANNEL,
+					sdp_surface->src_data.channel - 1);
+
+		/* config SDP source info */
+		if (!fly) {
+			/**
+			 * if not on-the-fly, we have to config
+			 * the source cube info
+			 */
+			high = HIGH32BITS(src_addr);
+			low = LOW32BITS(src_addr);
+			sdp_rdma_reg_write(D_SRC_BASE_ADDR_LOW, low);
+			sdp_rdma_reg_write(D_SRC_BASE_ADDR_HIGH, high);
+			sdp_rdma_reg_write(D_SRC_LINE_STRIDE,
+					sdp_surface->src_data.line_stride);
+			sdp_rdma_reg_write(D_SRC_SURFACE_STRIDE,
+					sdp_surface->src_data.surf_stride);
+			sdp_rdma_reg_write(D_SRC_DMA_CFG,
+				map_ram_type[sdp_surface->src_data.type]);
+		}
+
+		/* config x1 source info */
+		reg = (map_ena[x1_rdma_ena] <<
+				SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
+				BRDMA_DISABLE)) |
+			(map_op_type[x1_op->type] <<
+				SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
+				BRDMA_DATA_USE)) |
+			(map_element_size[x1_op->precision] <<
+				SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
+				BRDMA_DATA_SIZE)) |
+			(map_op_mode[x1_op->mode] <<
+				SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
+				BRDMA_DATA_MODE)) |
+			(map_ram_type[sdp_surface->x1_data.type] <<
+				SHIFT(SDP_RDMA_D_BRDMA_CFG_0,
+				BRDMA_RAM_TYPE));
+		sdp_rdma_reg_write(D_BRDMA_CFG, reg);
+
+		if (x1_rdma_ena) {
+			high = HIGH32BITS(x1_addr);
+			low = LOW32BITS(x1_addr);
+			sdp_rdma_reg_write(D_BS_BASE_ADDR_LOW,
+					low);
+			sdp_rdma_reg_write(D_BS_BASE_ADDR_HIGH,
+					high);
+			sdp_rdma_reg_write(D_BS_LINE_STRIDE,
+					sdp_surface->x1_data.line_stride);
+			sdp_rdma_reg_write(D_BS_SURFACE_STRIDE,
+					sdp_surface->x1_data.surf_stride);
+		}
+
+		/* config x2 source info */
+		reg = (map_ena[x2_rdma_ena] <<
+					SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
+					NRDMA_DISABLE)) |
+			(map_op_type[x2_op->type] <<
+					SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
+					NRDMA_DATA_USE)) |
+			(map_element_size[x2_op->precision] <<
+					SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
+					NRDMA_DATA_SIZE)) |
+			(map_op_mode[x2_op->mode] <<
+					SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
+					NRDMA_DATA_MODE)) |
+			(map_ram_type[sdp_surface->x2_data.type] <<
+					SHIFT(SDP_RDMA_D_NRDMA_CFG_0,
+					NRDMA_RAM_TYPE));
+
+		sdp_rdma_reg_write(D_NRDMA_CFG, reg);
+
+		if (x2_rdma_ena) {
+			high = HIGH32BITS(x2_addr);
+			low = LOW32BITS(x2_addr);
+			sdp_rdma_reg_write(D_BN_BASE_ADDR_LOW,
+					low);
+			sdp_rdma_reg_write(D_BN_BASE_ADDR_HIGH,
+					high);
+			sdp_rdma_reg_write(D_BN_LINE_STRIDE,
+					sdp_surface->x2_data.line_stride);
+			sdp_rdma_reg_write(D_BN_SURFACE_STRIDE,
+					sdp_surface->x2_data.surf_stride);
+		}
+
+		/* config y source info */
+		reg = (map_ena[y_rdma_ena] <<
+				SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
+				ERDMA_DISABLE)) |
+			(map_op_type[y_op->type] <<
+				SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
+				ERDMA_DATA_USE)) |
+			(map_element_size[y_op->precision] <<
+				SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
+				ERDMA_DATA_SIZE)) |
+			(map_op_mode[y_op->mode] <<
+				SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
+				ERDMA_DATA_MODE)) |
+			(map_ram_type[sdp_surface->y_data.type] <<
+				SHIFT(SDP_RDMA_D_ERDMA_CFG_0,
+				ERDMA_RAM_TYPE));
+
+		sdp_rdma_reg_write(D_ERDMA_CFG, reg);
+		if (y_rdma_ena) {
+			high = HIGH32BITS(y_addr);
+			low = LOW32BITS(y_addr);
+			sdp_rdma_reg_write(D_EW_BASE_ADDR_LOW,
+					low);
+			sdp_rdma_reg_write(D_EW_BASE_ADDR_HIGH,
+					high);
+			sdp_rdma_reg_write(D_EW_LINE_STRIDE,
+					sdp_surface->y_data.line_stride);
+			sdp_rdma_reg_write(D_EW_SURFACE_STRIDE,
+					sdp_surface->y_data.surf_stride);
+		}
+	}
+
+	if (sdp_op->lut_index >= 0)
+		update_lut(SDP_S_LUT_ACCESS_CFG_0, &lut,
+					sdp_op->src_precision);
+
+	sdp_reg_write(D_DATA_CUBE_WIDTH, sdp_surface->src_data.width - 1);
+	sdp_reg_write(D_DATA_CUBE_HEIGHT, sdp_surface->src_data.height - 1);
+	sdp_reg_write(D_DATA_CUBE_CHANNEL, sdp_surface->src_data.channel - 1);
+
+	if (out_dma_ena) {
+		high = HIGH32BITS(dst_addr);
+		low = LOW32BITS(dst_addr);
+		sdp_reg_write(D_DST_BASE_ADDR_HIGH,
+				high);
+		sdp_reg_write(D_DST_BASE_ADDR_LOW,
+				low);
+		sdp_reg_write(D_DST_LINE_STRIDE,
+				sdp_surface->dst_data.line_stride);
+		sdp_reg_write(D_DST_SURFACE_STRIDE,
+				sdp_surface->dst_data.surf_stride);
+	}
+
+	/* Config BS module */
+	reg = (map_bypass[x1_op->enable] <<
+			SHIFT(SDP_D_DP_BS_CFG_0,
+			BS_BYPASS)) |
+		(map_bypass[x1_op->type != SDP_OP_MUL &&
+				x1_op->type != SDP_OP_NONE] <<
+			SHIFT(SDP_D_DP_BS_CFG_0,
+			BS_ALU_BYPASS)) |
+		(map_alu_op[x1_op->alu_type] <<
+			SHIFT(SDP_D_DP_BS_CFG_0,
+			BS_ALU_ALGO)) |
+		(map_bypass[x1_op->type != SDP_OP_ADD &&
+			x1_op->type != SDP_OP_NONE] <<
+			SHIFT(SDP_D_DP_BS_CFG_0,
+			BS_MUL_BYPASS)) |
+		(map_prelu[x1_op->act == ACTIVATION_PRELU]
+			<< SHIFT(SDP_D_DP_BS_CFG_0,
+			BS_MUL_PRELU)) |
+		(map_bypass[x1_op->act == ACTIVATION_RELU] <<
+			SHIFT(SDP_D_DP_BS_CFG_0,
+			BS_RELU_BYPASS));
+	sdp_reg_write(D_DP_BS_CFG, reg);
+
+	if (x1_op->enable) {
+		if (x1_op->type == SDP_OP_ADD ||
+				x1_op->type == SDP_OP_BOTH) {
+			reg = (map_alu_src[x1_op->mode == SDP_OP_PER_LAYER] <<
+					SHIFT(SDP_D_DP_BS_ALU_CFG_0,
+					BS_ALU_SRC)) |
+				(x1_op->shift_value <<
+					SHIFT(SDP_D_DP_BS_ALU_CFG_0,
+					BS_ALU_SHIFT_VALUE));
+			sdp_reg_write(D_DP_BS_ALU_CFG, reg);
+		}
+
+		if (x1_op->mode == SDP_OP_PER_LAYER) {
+			sdp_reg_write(D_DP_BS_ALU_SRC_VALUE,
+					x1_op->alu_operand);
+			sdp_reg_write(D_DP_BS_MUL_SRC_VALUE,
+					x1_op->mul_operand);
+		}
+
+		/**
+		 * MUL truncate will take effect no matter
+		 * MUL is bypassed or not
+		 */
+		reg = (map_alu_src[x1_op->mode == SDP_OP_PER_LAYER] <<
+			SHIFT(SDP_D_DP_BS_MUL_CFG_0,
+			BS_MUL_SRC)) |
+		(x1_op->truncate <<
+			SHIFT(SDP_D_DP_BS_MUL_CFG_0,
+			BS_MUL_SHIFT_VALUE));
+		sdp_reg_write(D_DP_BS_MUL_CFG, reg);
+	}
+
+	/* Config BN module */
+	reg = (map_bypass[x2_op->enable] <<
+			SHIFT(SDP_D_DP_BN_CFG_0,
+			BN_BYPASS)) |
+		(map_bypass[x2_op->type != SDP_OP_MUL &&
+			x2_op->type != SDP_OP_NONE] <<
+			SHIFT(SDP_D_DP_BN_CFG_0,
+			BN_ALU_BYPASS)) |
+		(map_alu_op[x2_op->alu_type] <<
+			SHIFT(SDP_D_DP_BN_CFG_0,
+			BN_ALU_ALGO)) |
+		(map_bypass[x2_op->type != SDP_OP_ADD &&
+			x2_op->type != SDP_OP_NONE] <<
+			SHIFT(SDP_D_DP_BN_CFG_0,
+			BN_MUL_BYPASS)) |
+		(map_prelu[x2_op->act == ACTIVATION_PRELU]
+			<< SHIFT(SDP_D_DP_BN_CFG_0,
+			BN_MUL_PRELU)) |
+		(map_bypass[x2_op->act == ACTIVATION_RELU]
+			<< SHIFT(SDP_D_DP_BN_CFG_0,
+			BN_RELU_BYPASS));
+	sdp_reg_write(D_DP_BN_CFG, reg);
+
+	if (x2_op->enable) {
+		if (x2_op->type == SDP_OP_ADD ||
+			x2_op->type == SDP_OP_BOTH) {
+			reg = (map_alu_src[x2_op->mode == SDP_OP_PER_LAYER] <<
+					SHIFT(SDP_D_DP_BN_ALU_CFG_0,
+					BN_ALU_SRC)) |
+				(x2_op->shift_value <<
+					SHIFT(SDP_D_DP_BN_ALU_CFG_0,
+					BN_ALU_SHIFT_VALUE));
+			sdp_reg_write(D_DP_BN_ALU_CFG, reg);
+		}
+
+		if (x2_op->mode == SDP_OP_PER_LAYER) {
+			sdp_reg_write(D_DP_BN_ALU_SRC_VALUE,
+					x2_op->alu_operand);
+			sdp_reg_write(D_DP_BN_MUL_SRC_VALUE,
+					x2_op->mul_operand);
+		}
+
+		reg = (map_alu_src[x2_op->mode == SDP_OP_PER_LAYER] <<
+				SHIFT(SDP_D_DP_BN_MUL_CFG_0,
+				BN_MUL_SRC)) |
+			(x2_op->truncate <<
+				SHIFT(SDP_D_DP_BN_MUL_CFG_0,
+				BN_MUL_SHIFT_VALUE));
+		sdp_reg_write(D_DP_BN_MUL_CFG, reg);
+	}
+
+	/* Config EW module */
+	reg = (map_bypass[y_op->enable] <<
+			SHIFT(SDP_D_DP_EW_CFG_0,
+			EW_BYPASS)) |
+		(map_bypass[y_op->type != SDP_OP_MUL &&
+			y_op->type != SDP_OP_NONE] <<
+			SHIFT(SDP_D_DP_EW_CFG_0,
+			EW_ALU_BYPASS)) |
+		(map_alu_op[y_op->alu_type] <<
+			SHIFT(SDP_D_DP_EW_CFG_0,
+			EW_ALU_ALGO)) |
+		(map_bypass[y_op->type != SDP_OP_ADD &&
+			y_op->type != SDP_OP_NONE] <<
+			SHIFT(SDP_D_DP_EW_CFG_0,
+			EW_MUL_BYPASS)) |
+		((map_prelu[y_op->act == ACTIVATION_PRELU]) <<
+			SHIFT(SDP_D_DP_EW_CFG_0,
+			EW_MUL_PRELU)) |
+		(map_bypass[y_op->act == ACTIVATION_LUT] <<
+			SHIFT(SDP_D_DP_EW_CFG_0,
+			EW_LUT_BYPASS));
+	sdp_reg_write(D_DP_EW_CFG, reg);
+
+	if (y_op->enable) {
+		if (y_op->type == SDP_OP_ADD || y_op->type == SDP_OP_BOTH) {
+			reg = (map_alu_src[y_op->mode == SDP_OP_PER_LAYER] <<
+					SHIFT(SDP_D_DP_EW_ALU_CFG_0,
+					EW_ALU_SRC)) |
+				(map_bypass[y_op->cvt.alu_cvt.enable] <<
+					SHIFT(SDP_D_DP_EW_ALU_CFG_0,
+					EW_ALU_CVT_BYPASS));
+			sdp_reg_write(D_DP_EW_ALU_CFG, reg);
+
+			if (y_op->mode == SDP_OP_PER_LAYER) {
+				sdp_reg_write(D_DP_EW_ALU_SRC_VALUE,
+						y_op->alu_operand);
+			} else {
+				sdp_reg_write(D_DP_EW_ALU_CVT_OFFSET_VALUE,
+						y_op->cvt.alu_cvt.offset);
+				sdp_reg_write(D_DP_EW_ALU_CVT_SCALE_VALUE,
+						y_op->cvt.alu_cvt.scale);
+				sdp_reg_write(D_DP_EW_ALU_CVT_TRUNCATE_VALUE,
+						y_op->cvt.alu_cvt.truncate);
+			}
+		}
+
+		if (y_op->type == SDP_OP_MUL || y_op->type == SDP_OP_BOTH) {
+			reg = (map_alu_src[y_op->mode == SDP_OP_PER_LAYER] <<
+					SHIFT(SDP_D_DP_EW_MUL_CFG_0,
+					EW_MUL_SRC)) |
+				(map_bypass[y_op->cvt.mul_cvt.enable] <<
+					SHIFT(SDP_D_DP_EW_MUL_CFG_0,
+					EW_MUL_CVT_BYPASS));
+			sdp_reg_write(D_DP_EW_MUL_CFG, reg);
+
+			if (y_op->mode == SDP_OP_PER_LAYER) {
+				sdp_reg_write(D_DP_EW_MUL_SRC_VALUE,
+						y_op->mul_operand);
+			} else {
+				sdp_reg_write(D_DP_EW_MUL_CVT_OFFSET_VALUE,
+						y_op->cvt.mul_cvt.offset);
+				sdp_reg_write(D_DP_EW_MUL_CVT_SCALE_VALUE,
+						y_op->cvt.mul_cvt.scale);
+				sdp_reg_write(D_DP_EW_MUL_CVT_TRUNCATE_VALUE,
+						y_op->cvt.mul_cvt.truncate);
+			}
+		}
+
+		sdp_reg_write(D_DP_EW_TRUNCATE_VALUE, y_op->truncate);
+	}
+
+	reg = (map_fly[sdp_surface->src_data.type == DLA_MEM_HW] <<
+			SHIFT(SDP_D_FEATURE_MODE_CFG_0,
+			FLYING_MODE)) |
+		(map_dst[sdp_surface->dst_data.type == DLA_MEM_HW] <<
+			SHIFT(SDP_D_FEATURE_MODE_CFG_0,
+			OUTPUT_DST)) |
+		(map_wg[sdp_op->conv_mode == CONV_MODE_WINOGRAD] <<
+			SHIFT(SDP_D_FEATURE_MODE_CFG_0,
+			WINOGRAD)) |
+		((sdp_op->batch_num - 1) <<
+			SHIFT(SDP_D_FEATURE_MODE_CFG_0,
+			BATCH_NUMBER));
+	sdp_reg_write(D_FEATURE_MODE_CFG, reg);
+	sdp_reg_write(D_DST_DMA_CFG,
+			map_ram_type[sdp_surface->dst_data.type]);
+	if (sdp_op->batch_num > 1)
+		sdp_reg_write(D_DST_BATCH_STRIDE, sdp_op->batch_stride);
+
+	reg =
+	(map_proc_precision[sdp_op->dst_precision][sdp_op->src_precision] <<
+			SHIFT(SDP_D_DATA_FORMAT_0,
+			PROC_PRECISION)) |
+		(map_precision[sdp_op->dst_precision] <<
+			SHIFT(SDP_D_DATA_FORMAT_0,
+			OUT_PRECISION));
+	sdp_reg_write(D_DATA_FORMAT, reg);
+	sdp_reg_write(D_CVT_OFFSET, sdp_op->out_cvt.offset);
+	sdp_reg_write(D_CVT_SCALE, sdp_op->out_cvt.scale);
+	sdp_reg_write(D_CVT_SHIFT, sdp_op->out_cvt.truncate);
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
+
+int
+dla_sdp_is_ready(struct dla_processor *processor,
+			   struct dla_processor_group *group)
+{
+	struct dla_processor_group *next_group;
+	struct dla_sdp_op_desc *sdp_op;
+
+	sdp_op = &group->operation_desc->sdp_op;
+	next_group = &processor->groups[!group->id];
+
+	/**
+	 * Single LUT is shared between two SDP groups, need to make
+	 * sure that usage does not conflict. Also, LUT write
+	 * access is locked when SDP sub-engine is active, so delay
+	 * writing LUT when another group is active.
+	 */
+
+	/**
+	 * if no LUT required for current group then it can be programmed
+	 * without further checks
+	 */
+	if (sdp_op->lut_index == -1)
+		return 1;
+
+	/**
+	 * if same LUT is used for both groups then it can be programmed
+	 * without more checks. Even if another group is active and LUT
+	 * is locked, it would have been programmed by another group.
+	 */
+	if (next_group->lut_index == sdp_op->lut_index)
+		return 1;
+
+	/**
+	 * if LUT index of another group is not -1 means some LUT is programmed,
+	 * then do not program current LUT as we already know current LUT is not
+	 * -1 and neither same as another group.
+	 */
+	if (next_group->lut_index != -1)
+		return 0;
+
+	/**
+	 * if current group needs LUT different than another group and that
+	 * group is not active then program it.
+	 */
+	if (!next_group->active)
+		return 1;
+
+	/**
+	 * if control is here it means current group is using LUT different than
+	 * another group and that group is active. Wait for another group to
+	 * become idle.
+	 */
+	return 0;
+}
+
+void
+dla_sdp_dump_config(struct dla_processor_group *group)
+{
+	struct dla_sdp_op_desc *sdp_op;
+	struct dla_sdp_surface_desc *sdp_surface;
+
+	sdp_surface = &group->surface_desc->sdp_surface;
+	sdp_op = &group->operation_desc->sdp_op;
+
+	dla_debug_sdp_surface_desc(sdp_surface, group->roi_index);
+	dla_debug_sdp_op_desc(sdp_op, group->roi_index);
+}
+
+int
+dla_sdp_program(struct dla_processor_group *group)
+{
+	int32_t ret;
+
+	dla_trace("Enter: %s", __func__);
+	dla_enable_intr(MASK(GLB_S_INTR_MASK_0, SDP_DONE_MASK1) |
+			MASK(GLB_S_INTR_MASK_0, SDP_DONE_MASK0));
+
+	ret = processor_sdp_program(group);
+	if (ret)
+		goto exit;
+
+exit:
+	dla_trace("Exit: %s", __func__);
+	RETURN(ret);
+}
diff --git a/kernel/dma/coherent.c b/kernel/dma/coherent.c
index c21abc77c53e..e3237a2395c4 100644
--- a/kernel/dma/coherent.c
+++ b/kernel/dma/coherent.c
@@ -129,6 +129,7 @@ int dma_declare_coherent_memory(struct device *dev, phys_addr_t phys_addr,
 		_dma_release_coherent_memory(mem);
 	return ret;
 }
+EXPORT_SYMBOL_GPL(dma_declare_coherent_memory);
 
 void dma_release_coherent_memory(struct device *dev)
 {
-- 
2.41.0


From 950565c49809f9744229da24a5c88176f577ade8 Mon Sep 17 00:00:00 2001
From: Emil Renner Berthing <kernel@esmil.dk>
Date: Sun, 31 Oct 2021 17:15:58 +0100
Subject: [PATCH 72/72] riscv: dts: Add full JH7100, Starlight and VisionFive
 support

Based on the device tree in https://github.com/starfive-tech/u-boot/
with contributions from:
yanhong.wang <yanhong.wang@starfivetech.com>
Huan.Feng <huan.feng@starfivetech.com>
ke.zhu <ke.zhu@starfivetech.com>
yiming.li <yiming.li@starfivetech.com>
jack.zhu <jack.zhu@starfivetech.com>
Samin Guo <samin.guo@starfivetech.com>
Chenjieqin <Jessica.Chen@starfivetech.com>
bo.li <bo.li@starfivetech.com>

Rearranged, cleanups, fixes, pins and resets added by Emil.
Cleanups, fixes, clocks added by Geert.
Cleanups and GPIO fixes from Drew.
Thermal zone added by Stephen.
PWM pins added by Jianlong.
cpu-map added by Jonas.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Stephen L Arnold <nerdboy@gentoo.org>
Signed-off-by: Drew Fustini <drew@beagleboard.org>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jonas Hahnfeld <hahnjo@hahnjo.de>
---
 arch/riscv/boot/dts/starfive/Makefile         |   1 +
 .../starfive/jh7100-beaglev-starlight-a1.dts  |  30 ++
 .../dts/starfive/jh7100-beaglev-starlight.dts |   6 +
 .../boot/dts/starfive/jh7100-common.dtsi      | 256 +++++++++++
 .../jh7100-starfive-visionfive-v1.dts         |  13 +
 arch/riscv/boot/dts/starfive/jh7100.dtsi      | 427 +++++++++++++++++-
 6 files changed, 732 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts

diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 170956846d49..6535e1d39b9e 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight-a1.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
 
diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
new file mode 100644
index 000000000000..648697b386f5
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight-a1.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7100-common.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "BeagleV Starlight Beta A1";
+	compatible = "beagle,beaglev-starlight-jh7100-a1", "starfive,jh7100";
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
+		priority = <224>;
+	};
+};
+
+&gpio {
+	/* don't reset gpio mux for serial console and reset gpio */
+	starfive,keep-gpiomux = <13 14 63>;
+};
+
+&mdio {
+	phy: ethernet-phy@7 {
+		reg = <7>;
+	};
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
index 22dfeddeee17..26d480954484 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
+++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 #include "jh7100-common.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "BeagleV Starlight Beta";
@@ -16,6 +17,11 @@ &gmac {
 	snps,reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
 };
 
+&gpio {
+	/* don't reset gpio mux for serial console on uart3 */
+	starfive,keep-gpiomux = <13 14>;
+};
+
 &mdio {
 	phy: ethernet-phy@7 {
 		reg = <7>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index 6fc5a1bc9316..296e83afd554 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -12,7 +12,10 @@
 
 / {
 	aliases {
+		mmc0 = &sdio0;
+		mmc1 = &sdio1;
 		serial0 = &uart3;
+		serial1 = &uart0;
 	};
 
 	chosen {
@@ -45,11 +48,41 @@ reserved-memory {
 		#size-cells = <2>;
 		ranges;
 
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0xa0000000 0x0 0x28000000>;
+			size = <0x0 0x28000000>;
+			alignment = <0x0 0x1000>;
+			reusable;
+			linux,cma-default;
+		};
+
+		jpu_reserved: framebuffer@c9000000 {
+			reg = <0x0 0xc9000000 0x0 0x4000000>;
+		};
+
+		nvdla_reserved: framebuffer@d0000000 {
+			reg = <0x0 0xd0000000 0x0 0x28000000>;
+			no-map;
+		};
+
+		vin_reserved: framebuffer@f9000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0xf9000000 0x0 0x1000000>;
+			no-map;
+		};
+
 		dma-reserved {
 			reg = <0x0 0xfa000000 0x0 0x1000000>;
 			no-map;
 		};
 
+		sffb_reserved: framebuffer@fb000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0xfb000000 0x0 0x2000000>;
+			no-map;
+		};
+
 		linux,dma {
 			compatible = "shared-dma-pool";
 			reg = <0x10 0x7a000000 0x0 0x1000000>;
@@ -63,6 +96,49 @@ soc {
 			     <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
 			     <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
 	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&display {
+	memory-region = <&sffb_reserved>;
+	status = "okay";
+};
+
+&crtc {
+	ddr-format = <4>; //<WIN_FMT_RGB565>;
+	status = "okay";
+
+	port: port@0 {
+		reg = <0>;
+
+		crtc_0_out: endpoint {
+			remote-endpoint = <&hdmi_input0>;
+		};
+	};
+};
+
+&encoder {
+	encoder-type = <2>; // 2-TMDS, 3-LVDS, 6-DSI, 8-DPI
+	status = "okay";
+
+	ports {
+		port@0 {
+			hdmi_out: endpoint {
+				remote-endpoint = <&tda998x_0_input>;
+			};
+		};
+
+		port@1 {
+			hdmi_input0: endpoint {
+				remote-endpoint = <&crtc_0_out>;
+			};
+		};
+
+	};
 };
 
 &gmac {
@@ -194,6 +270,38 @@ GPO_I2C2_PAD_SDA_OEN,
 		};
 	};
 
+	pwmdac_pins: pwmdac-0 {
+		pwmdac-pins {
+			pinmux = <GPIOMUX(23, GPO_PWMDAC_LEFT_OUT,
+				  GPO_ENABLE, GPI_NONE)>,
+				 <GPIOMUX(24, GPO_PWMDAC_RIGHT_OUT,
+				  GPO_ENABLE, GPI_NONE)>;
+			bias-disable;
+			drive-strength = <35>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pwm_pins: pwm-0 {
+		pwm-pins {
+			pinmux = <GPIOMUX(7,
+				  GPO_PWM_PAD_OUT_BIT0,
+				  GPO_PWM_PAD_OE_N_BIT0,
+				  GPI_NONE)>,
+				 <GPIOMUX(5,
+				  GPO_PWM_PAD_OUT_BIT1,
+				  GPO_PWM_PAD_OE_N_BIT1,
+				  GPI_NONE)>;
+			bias-disable;
+			drive-strength = <35>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
 	sdio0_pins: sdio0-0 {
 		clk-pins {
 			pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT,
@@ -266,6 +374,62 @@ GPO_SDIO1_PAD_CDATA_OEN_BIT3,
 		};
 	};
 
+	spi2_pins: spi2-0 {
+		mosi-pins {
+			pinmux = <GPIOMUX(18, GPO_SPI2_PAD_TXD,
+				  GPO_ENABLE, GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+		miso-pins {
+			pinmux = <GPIOMUX(16, GPO_LOW, GPO_DISABLE,
+				  GPI_SPI2_PAD_RXD)>;
+			bias-pull-up;
+			input-enable;
+			input-schmitt-enable;
+		};
+		sck-pins {
+			pinmux = <GPIOMUX(12, GPO_SPI2_PAD_SCK_OUT,
+				  GPO_ENABLE, GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+		ss-pins {
+			pinmux = <GPIOMUX(15, GPO_SPI2_PAD_SS_0_N,
+				  GPO_ENABLE, GPI_NONE)>,
+				 <GPIOMUX(11, GPO_SPI2_PAD_SS_1_N,
+				  GPO_ENABLE, GPI_NONE)>;
+			bias-disable;
+			input-disable;
+			input-schmitt-disable;
+		};
+	};
+
+	uart0_pins: uart0-0 {
+		rx-pins {
+			pinmux = <GPIOMUX(40, GPO_LOW, GPO_DISABLE,
+				  GPI_UART0_PAD_SIN)>,
+				 <GPIOMUX(39, GPO_LOW, GPO_DISABLE,
+				  GPI_UART0_PAD_CTSN)>;
+			bias-pull-up;
+			drive-strength = <14>;
+			input-enable;
+			input-schmitt-enable;
+		};
+		tx-pins {
+			pinmux = <GPIOMUX(41, GPO_UART0_PAD_SOUT,
+				  GPO_ENABLE, GPI_NONE)>,
+				 <GPIOMUX(42, GPO_UART0_PAD_RTSN,
+				  GPO_ENABLE, GPI_NONE)>;
+			bias-disable;
+			drive-strength = <35>;
+			input-disable;
+			input-schmitt-disable;
+		};
+	};
+
 	uart3_pins: uart3-0 {
 		rx-pins {
 			pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
@@ -306,6 +470,17 @@ pmic@5e {
 		regulators {
 		};
 	};
+
+	tda998x@70 {
+		compatible = "nxp,tda998x";
+		reg = <0x70>;
+
+		port {
+			tda998x_0_input: endpoint {
+				remote-endpoint = <&hdmi_out>;
+			};
+		};
+	};
 };
 
 &i2c1 {
@@ -336,6 +511,50 @@ &osc_aud {
 	clock-frequency = <27000000>;
 };
 
+&ptc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm_pins>;
+	status = "okay";
+};
+
+&pwmdac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwmdac_pins>;
+	status = "okay";
+};
+
+&qspi {
+	nor_flash: nor-flash@0 {
+		compatible = "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <31250000>;
+		page-size = <256>;
+		block-size = <16>;
+		cdns,read-delay = <4>;
+		cdns,tshsl-ns = <1>;
+		cdns,tsd2d-ns = <1>;
+		cdns,tchsh-ns = <1>;
+		cdns,tslch-ns = <1>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+
+	nand_flash: nand-flash@1 {
+		compatible = "spi-flash-nand";
+		reg = <1>;
+		spi-max-frequency = <31250000>;
+		page-size = <2048>;
+		block-size = <17>;
+		cdns,read-delay = <4>;
+		cdns,tshsl-ns = <1>;
+		cdns,tsd2d-ns = <1>;
+		cdns,tchsh-ns = <1>;
+		cdns,tslch-ns = <1>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
+
 &sdio0 {
 	broken-cd;
 	bus-width = <4>;
@@ -345,6 +564,43 @@ &sdio0 {
 	status = "okay";
 };
 
+&sdio1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	cap-power-off-card;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio1_pins>;
+	status = "okay";
+
+	wifi@1 {
+		compatible = "brcm,bcm4329-fmac";
+		reg = <1>;
+	};
+};
+
+&spi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi2_pins>;
+	status = "okay";
+
+	spi_dev0: spi@0 {
+		compatible = "rohm,dh2228fv";
+		spi-max-frequency = <10000000>;
+		reg = <0>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
 &uart3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart3_pins>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
index f9744938f0ce..4778653f0ce3 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
+++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts
@@ -19,6 +19,19 @@ gpio-restart {
 	};
 };
 
+&gpio {
+	/* don't reset gpio mux for serial console and reset gpio */
+	starfive,keep-gpiomux = <13 14 63>;
+};
+
+&i2c0 {
+	eeprom@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
 &mdio {
 	phy: ethernet-phy@0 {
 		reg = <0>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index ad03dabcddd0..f33775c6593a 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -6,7 +6,9 @@
 
 /dts-v1/;
 #include <dt-bindings/clock/starfive-jh7100.h>
+#include <dt-bindings/clock/starfive-jh7100-audio.h>
 #include <dt-bindings/reset/starfive-jh7100.h>
+#include <dt-bindings/reset/starfive-jh7100-audio.h>
 
 / {
 	compatible = "starfive,jh7100";
@@ -34,6 +36,7 @@ U74_0: cpu@0 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc";
+			starfive,itim = <&itim0>;
 			tlb-split;
 
 			cpu0_intc: interrupt-controller {
@@ -60,6 +63,7 @@ U74_1: cpu@1 {
 			mmu-type = "riscv,sv39";
 			next-level-cache = <&ccache>;
 			riscv,isa = "rv64imafdc";
+			starfive,itim = <&itim1>;
 			tlb-split;
 
 			cpu1_intc: interrupt-controller {
@@ -150,6 +154,24 @@ soc {
 		#size-cells = <2>;
 		ranges;
 
+		dtim: dtim@1000000 {
+			compatible = "starfive,dtim0";
+			reg = <0x0 0x1000000 0x0 0x2000>;
+			reg-names = "mem";
+		};
+
+		itim0: itim@1808000 {
+			compatible = "starfive,itim0";
+			reg = <0x0 0x1808000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+
+		itim1: itim@1820000 {
+			compatible = "starfive,itim0";
+			reg = <0x0 0x1820000 0x0 0x8000>;
+			reg-names = "mem";
+		};
+
 		clint: clint@2000000 {
 			compatible = "starfive,jh7100-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
@@ -216,7 +238,7 @@ gmac: ethernet@10020000 {
 				 <&clkgen JH7100_CLK_GMAC_GTX>;
 			clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
 			resets = <&rstgen JH7100_RSTN_GMAC_AHB>;
-			reset-names = "stmmaceth";
+			reset-names = "ahb";
 			interrupts = <6>, <7>;
 			interrupt-names = "macirq", "eth_wake_irq";
 			max-frame-size = <9000>;
@@ -232,6 +254,124 @@ gmac: ethernet@10020000 {
 			status = "disabled";
 		};
 
+		dma2p: dma-controller@100b0000 {
+			compatible = "starfive,jh7100-axi-dma";
+			reg = <0x0 0x100b0000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
+				 <&clkgen JH7100_CLK_SGDMA2P_AHB>;
+			clock-names = "core-clk", "cfgr-clk";
+			resets = <&rstgen JH7100_RSTN_SGDMA2P_AXI>,
+				 <&rstgen JH7100_RSTN_SGDMA2P_AHB>;
+			reset-names = "axi", "ahb";
+			interrupts = <2>;
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			snps,dma-masters = <1>;
+			snps,data-width = <4>;
+			snps,block-size = <4096 4096 4096 4096>;
+			snps,priority = <0 1 2 3>;
+			snps,axi-max-burst-len = <128>;
+			dma-coherent;
+		};
+
+		crypto: crypto@100d0000 {
+			compatible = "starfive,vic-sec";
+			reg = <0x0 0x100d0000 0x0 0x20000>,
+			      <0x0 0x11800234 0x0 0xc>;
+			reg-names = "secmem", "secclk";
+			clocks = <&clkgen JH7100_CLK_SEC_AHB>;
+			interrupts = <31>;
+		};
+
+		i2sadc0: i2sadc0@10400000 {
+			compatible = "snps,designware-i2sadc0";
+			reg = <0x0 0x10400000 0x0 0x1000>;
+			clocks = <&clkgen JH7100_CLK_APB1_BUS>;
+			clock-names = "i2sclk";
+			interrupt-parent = <&plic>;
+			#sound-dai-cells = <0>;
+			dmas = <&dma2p 28>;
+			dma-names = "rx";
+		};
+
+		i2svad: i2svad@10420000 {
+			compatible = "starfive,sf-i2svad";
+			reg = <0x0 0x10420000 0x0 0x1000> ;
+			clocks = <&audclk JH7100_AUDCLK_I2SVAD_APB>;
+			clock-names = "i2svad_apb";
+			resets = <&audrst JH7100_AUDRSTN_I2SVAD_APB>,
+				 <&audrst JH7100_AUDRSTN_I2SVAD_SRST>;
+			reset-names = "apb_i2svad", "i2svad_srst";
+			interrupts = <60>, <61>;
+			interrupt-names = "spintr", "slintr";
+			#sound-dai-cells = <0>;
+		};
+
+		pwmdac: pwmdac@10440000 {
+			compatible = "starfive,pwmdac";
+			reg = <0x0 0x10440000 0x0 0x1000>;
+			clocks = <&clkgen JH7100_CLK_AUDIO_ROOT>,
+				 <&clkgen JH7100_CLK_AUDIO_SRC>,
+				 <&clkgen JH7100_CLK_AUDIO_12288>,
+				 <&audclk JH7100_AUDCLK_DMA1P_AHB>,
+				 <&audclk JH7100_AUDCLK_PWMDAC_APB>,
+				 <&audclk JH7100_AUDCLK_DAC_MCLK>;
+			clock-names = "audio_root",
+				      "audio_src",
+				      "audio_12288",
+				      "dma1p_ahb",
+				      "pwmdac_apb",
+				      "dac_mclk";
+			resets = <&audrst JH7100_AUDRSTN_APB_BUS>,
+				 <&audrst JH7100_AUDRSTN_DMA1P_AHB>,
+				 <&audrst JH7100_AUDRSTN_PWMDAC_APB>;
+			reset-names = "apb_bus", "dma1p_ahb", "apb_pwmdac";
+			dmas = <&dma2p 23>;
+			dma-names = "tx";
+			#sound-dai-cells = <0>;
+		};
+
+		i2sdac0: i2sdac0@10450000 {
+			compatible = "snps,designware-i2sdac0";
+			reg = <0x0 0x10450000 0x0 0x1000>;
+			clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
+				 <&audclk JH7100_AUDCLK_I2SDAC_BCLK>,
+				 <&audclk JH7100_AUDCLK_I2SDAC_LRCLK>,
+				 <&audclk JH7100_AUDCLK_I2SDAC_APB>;
+			clock-names = "dac_mclk", "i2sdac0_bclk", "i2sdac0_lrclk", "i2sdac_apb";
+			resets = <&audrst JH7100_AUDRSTN_I2SDAC_APB>,
+				 <&audrst JH7100_AUDRSTN_I2SDAC_SRST>;
+			reset-names = "apb_i2sdac", "i2sdac_srst";
+			#sound-dai-cells = <0>;
+			dmas = <&dma2p 30>;
+			dma-names = "tx";
+		};
+
+		i2sdac1: i2sdac1@10460000 {
+			compatible = "snps,designware-i2sdac1";
+			reg = <0x0 0x10460000 0x0 0x1000>;
+			clocks = <&audclk JH7100_AUDCLK_DAC_MCLK>,
+				 <&audclk JH7100_AUDCLK_I2S1_BCLK>,
+				 <&audclk JH7100_AUDCLK_I2S1_LRCLK>,
+				 <&audclk JH7100_AUDCLK_I2S1_APB>;
+			clock-names = "dac_mclk", "i2sdac1_bclk", "i2sdac1_lrclk", "i2s1_apb";
+			resets = <&audrst JH7100_AUDRSTN_I2S1_APB>,
+				 <&audrst JH7100_AUDRSTN_I2S1_SRST>;
+			#sound-dai-cells = <0>;
+			dmas = <&dma2p 31>;
+			dma-names = "tx";
+		};
+
+		i2sdac16k: i2sdac16k@10470000 {
+			compatible = "snps,designware-i2sdac16k";
+			reg = <0x0 0x10470000 0x0 0x1000>;
+			clocks = <&clkgen JH7100_CLK_APB1_BUS>;
+			clock-names = "i2sclk";
+			#sound-dai-cells = <0>;
+			dmas = <&dma2p 29>;
+			dma-names = "tx";
+		};
+
 		audclk: clock-controller@10480000 {
 			compatible = "starfive,jh7100-audclk";
 			reg = <0x0 0x10480000 0x0 0x10000>;
@@ -248,6 +388,50 @@ audrst: reset-controller@10490000 {
 			#reset-cells = <1>;
 		};
 
+		spdif_transmitter: spdif-transmitter {
+			compatible = "linux,spdif-dit";
+			#sound-dai-cells = <0>;
+		};
+
+		spdif_receiver: spdif-receiver {
+			compatible = "linux,spdif-dir";
+			#sound-dai-cells = <0>;
+		};
+
+		pwmdac_codec: pwmdac-transmitter {
+			compatible = "linux,pwmdac-dit";
+			#sound-dai-cells = <0>;
+		};
+
+		dmic_codec: dmic {
+			compatible = "dmic-codec";
+			#sound-dai-cells = <0>;
+		};
+
+		sound: snd-card {
+			compatible = "simple-audio-card";
+			simple-audio-card,name = "Starfive-Multi-Sound-Card";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/* pwmdac */
+			simple-audio-card,dai-link@0 {
+				reg = <0>;
+				status = "okay";
+				format = "left_j";
+				bitclock-master = <&sndcpu0>;
+				frame-master = <&sndcpu0>;
+
+				sndcpu0: cpu {
+					sound-dai = <&pwmdac>;
+				};
+
+				codec {
+					sound-dai = <&pwmdac_codec>;
+				};
+			};
+		};
+
 		sysaudio: syscon@104a0000 {
 			compatible = "starfive,jh7100-sysaudio", "syscon";
 			reg = <0x0 0x104a0000 0x0 0x10000>;
@@ -280,6 +464,25 @@ usb_cdns3: usb@0 {
 			};
 		};
 
+		dma1p: dma-controller@10500000 {
+			compatible = "starfive,jh7100-axi-dma";
+			reg = <0x0 0x10500000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
+				 <&clkgen JH7100_CLK_SGDMA1P_BUS>;
+			clock-names = "core-clk", "cfgr-clk";
+			resets = <&rstgen JH7100_RSTN_DMA1P_AXI>,
+				 <&rstgen JH7100_RSTN_SGDMA1P_AXI>;
+			reset-names = "axi", "ahb";
+			interrupts = <1>;
+			#dma-cells = <1>;
+			dma-channels = <16>;
+			snps,dma-masters = <1>;
+			snps,data-width = <3>;
+			snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
+			snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+			snps,axi-max-burst-len = <64>;
+		};
+
 		clkgen: clock-controller@11800000 {
 			compatible = "starfive,jh7100-clkgen";
 			reg = <0x0 0x11800000 0x0 0x10000>;
@@ -288,6 +491,13 @@ clkgen: clock-controller@11800000 {
 			#clock-cells = <1>;
 		};
 
+		otp: otp@11810000 {
+			compatible = "starfive,fu740-otp";
+			reg = <0x0 0x11810000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_OTP_APB>;
+			fuse-count = <0x200>;
+		};
+
 		rstgen: reset-controller@11840000 {
 			compatible = "starfive,jh7100-reset";
 			reg = <0x0 0x11840000 0x0 0x10000>;
@@ -299,6 +509,75 @@ sysmain: syscon@11850000 {
 			reg = <0x0 0x11850000 0x0 0x10000>;
 		};
 
+		qspi: spi@11860000 {
+			compatible = "cdns,qspi-nor";
+			reg = <0x0 0x11860000 0x0 0x10000>,
+			      <0x0 0x20000000 0x0 0x20000000>;
+			clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
+			interrupts = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x0>;
+			spi-max-frequency = <250000000>;
+			status = "disabled";
+		};
+
+		uart0: serial@11870000 {
+			compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
+			reg = <0x0 0x11870000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_UART0_CORE>,
+				 <&clkgen JH7100_CLK_UART0_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&rstgen JH7100_RSTN_UART0_APB>;
+			interrupts = <92>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart1: serial@11880000 {
+			compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
+			reg = <0x0 0x11880000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_UART1_CORE>,
+				 <&clkgen JH7100_CLK_UART1_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			resets = <&rstgen JH7100_RSTN_UART1_APB>;
+			interrupts = <93>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		spi0: spi@11890000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x0 0x11890000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
+				 <&clkgen JH7100_CLK_SPI0_APB>;
+			clock-names = "ssi_clk", "pclk";
+			resets = <&rstgen JH7100_RSTN_SPI0_APB>;
+			reset-names = "spi";
+			interrupts = <94>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi@118a0000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x0 0x118a0000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
+				 <&clkgen JH7100_CLK_SPI1_APB>;
+			clock-names = "ssi_clk", "pclk";
+			resets = <&rstgen JH7100_RSTN_SPI1_APB>;
+			reset-names = "spi";
+			interrupts = <95>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@118b0000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x0 0x118b0000 0x0 0x10000>;
@@ -325,6 +604,41 @@ i2c1: i2c@118c0000 {
 			status = "disabled";
 		};
 
+		trng: trng@118d0000 {
+			compatible = "starfive,vic-rng";
+			reg = <0x0 0x118d0000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_TRNG_APB>;
+			interrupts = <98>;
+		};
+
+		vpu_enc: vpu_enc@118e0000 {
+			compatible = "cm,cm521-vpu";
+			reg = <0x0 0x118e0000 0x0 0x4000>;
+			reg-names = "control";
+			clocks = <&clkgen JH7100_CLK_VP6_CORE>;
+			clock-names = "vcodec";
+			interrupts = <26>;
+		};
+
+		vpu_dec: vpu_dec@118f0000 {
+			compatible = "c&m,cm511-vpu";
+			reg = <0 0x118f0000 0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_VP6_CORE>;
+			clock-names = "vcodec";
+			interrupts = <23>;
+			//memory-region = <&vpu_reserved>;
+		};
+
+		jpu: coadj12@11900000 {
+			compatible = "cm,codaj12-jpu-1";
+			reg = <0x0 0x11900000 0x0 0x300>;
+			reg-names = "control";
+			clocks = <&clkgen JH7100_CLK_JPEG_APB>;
+			clock-names = "jpege";
+			interrupts = <24>;
+			memory-region = <&jpu_reserved>;
+		};
+
 		gpio: pinctrl@11910000 {
 			compatible = "starfive,jh7100-pinctrl";
 			reg = <0x0 0x11910000 0x0 0x10000>,
@@ -339,6 +653,86 @@ gpio: pinctrl@11910000 {
 			#interrupt-cells = <2>;
 		};
 
+		nvdla@11940000 {
+			compatible = "nvidia,nvdla_os_initial";
+			interrupts = <22>;
+			memory-region = <&nvdla_reserved>;
+			reg = <0x0 0x11940000 0x0 0x40000>;
+			status = "okay";
+		};
+
+		display: display-subsystem {
+			compatible = "starfive,display-subsystem";
+			dma-coherent;
+			status = "disabled";
+		};
+
+		encoder: display-encoder {
+			compatible = "starfive,display-encoder";
+			status = "disabled";
+		};
+
+		crtc: crtc@12000000 {
+			compatible = "starfive,jh7100-crtc";
+			reg = <0x0 0x12000000 0x0 0x10000>,
+			      <0x0 0x12040000 0x0 0x10000>,
+			      <0x0 0x12080000 0x0 0x10000>,
+			      <0x0 0x120c0000 0x0 0x10000>,
+			      <0x0 0x12240000 0x0 0x10000>,
+			      <0x0 0x12250000 0x0 0x10000>,
+			      <0x0 0x12260000 0x0 0x10000>;
+			reg-names = "lcdc", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
+			clocks = <&clkgen JH7100_CLK_DISP_AXI>, <&clkgen JH7100_CLK_VOUT_SRC>;
+			clock-names = "disp_axi", "vout_src";
+			resets = <&rstgen JH7100_RSTN_DISP_AXI>, <&rstgen JH7100_RSTN_VOUT_SRC>;
+			reset-names = "disp_axi", "vout_src";
+			interrupts = <101>, <103>;
+			interrupt-names = "lcdc_irq", "vpp1_irq";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			pp1 {
+				pp-id = <1>;
+				fifo-out;
+				//sys-bus-out;
+				src-format = <11>; //<COLOR_RGB565>;
+				src-width = <1920>;
+				src-height = <1080>;
+				dst-format = <7>; //<COLOR_RGB888_ARGB>;
+				dst-width = <1920>;
+				dst-height = <1080>;
+			};
+		};
+
+		spi2: spi@12410000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x0 0x12410000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
+				 <&clkgen JH7100_CLK_SPI2_APB>;
+			clock-names = "ssi_clk", "pclk";
+			resets = <&rstgen JH7100_RSTN_SPI2_APB>;
+			reset-names = "spi";
+			interrupts = <70>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi3: spi@12420000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0x0 0x12420000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
+				 <&clkgen JH7100_CLK_SPI3_APB>;
+			clock-names = "ssi_clk", "pclk";
+			resets = <&rstgen JH7100_RSTN_SPI3_APB>;
+			reset-names = "spi";
+			interrupts = <71>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		uart2: serial@12430000 {
 			compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
 			reg = <0x0 0x12430000 0x0 0x10000>;
@@ -401,6 +795,16 @@ watchdog@12480000 {
 				 <&rstgen JH7100_RSTN_WDT>;
 		};
 
+		ptc: pwm@12490000 {
+			compatible = "starfive,pwm0";
+			reg = <0x0 0x12490000 0x0 0x10000>;
+			clocks = <&clkgen JH7100_CLK_PWM_APB>;
+			resets = <&rstgen JH7100_RSTN_PWM_APB>;
+			#pwm-cells = <3>;
+			sifive,npwm = <8>;
+			status = "disabled";
+		};
+
 		sfctemp: temperature-sensor@124a0000 {
 			compatible = "starfive,jh7100-temp";
 			reg = <0x0 0x124a0000 0x0 0x10000>;
@@ -412,5 +816,26 @@ sfctemp: temperature-sensor@124a0000 {
 			reset-names = "sense", "bus";
 			#thermal-sensor-cells = <0>;
 		};
+
+		xrp@f0000000 {
+			compatible = "cdns,xrp";
+			reg = <0x0  0xf0000000 0x0 0x01ffffff>,
+			      <0x10 0x72000000 0x0 0x00001000>,
+			      <0x10 0x72001000 0x0 0x00fff000>,
+			      <0x0  0x124b0000 0x0 0x00010000>;
+			clocks = <&clkgen JH7100_CLK_VP6_CORE>;
+			interrupts = <27>, <28>;
+			firmware-name = "vp6_elf";
+			dsp-irq = <19 20>;
+			dsp-irq-src = <0x20 0x21>;
+			intc-irq-mode = <1>;
+			intc-irq = <0 1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x40000000 0x0  0x40000000 0x01000000>,
+				 <0xb0000000 0x10 0x70000000 0x3000000>;
+			dsp@0 {
+			};
+		};
 	};
 };
-- 
2.41.0

